WO1994001953A1 - Time domain manchester decoder with ansi synchronization - Google Patents

Abstract

A method and apparatus is described for decoding a data stream in Manchester I encoded format with an ANSI sync, wherein the apparatus includes a first counter for counting clock pulses for a one-half data bit cell interval in increments of 1/4 the data bit cell interval, and a second counter for counting for two data one-half bit cell intervals. For decoding, there is provided a two input (plus sample clock) state machine responsive at one input to the detection of transitions or edges in the sampled encoded data stream, and at the other input, responsive to conditional and comparative determinations based on the input data and the processed outputs of the two counters and memory (the register). The logic for the other input provides a count of clock pulses for a given transition interval and utilizes the most recent stored count information from a preceding bit cell for processing bits in the next bit processing interval, with the processing in each bit period being iterated and updated until a prescribed state transition sequence is detected, after which the decoder is locked. The logic includes the first counter for counting the duration of one half bit cell intervals, the second counter for counting the duration of full bit cell intervals, first and second comparators, a register which stores the half bit cell count, and a multiplexer for selectively storing in the register either the present full interval count or the full interval count divided by two. The determination of the output of the multiplexer is dependent upon the output of the state machine, which determines which of the two values to load into the register. The output of the register is compared in the first comparator to clear the first counter at a time interval equal to the last stored one-half bit period, or after two successive quarter bit cell intervals. The inputs to the second comparator include the output of the first counter and the output of the register divided by two, with the output of the second comparator providing the second input to the state machine.

Description

TTME POMATN MANCHESTER DECODER

WTTH ANST SYNCHRONIZATION

TECHNICAL FIELD

This invention relates generally to a detector method and apparatus for serial data transmissions, and more particularly to a decoder for serial data encoded in accordance with the Manchester I code with ANSI synchronization.

CKCTROTΪNP ART Manchester code is a self -clocking code and is a common method employed for transmitting a serial data stream for reception without including a separate clock stream and, for the most part, has found widespread application for use in digital tape recorders, whether digital video or digital data format. The clock is included with the data since, in accordance with Manchester encoding format, at least one transition occurs for every (NRZ) data bit In accordance with Manchester I encoding, and for purposes of this invention, for decoding as a logical one, a bit cell (an NRZ bit cell) must have a level transition in the middle of the bit cell and one at the end of the bit cell; and for a logical zero, a transition at the end of the bit cell. Since Manchester code has at least one transition for every bit cell, the transitions enable extraction of the clock signal from the data to allow the receiver circuitry to remain synchronized to the incoming data.

In Manchester codes, whether Manchester I or Manchester π, transitions in data bits are either one half bit cell or one bit cell apart. In the ANSI-standard synchronization marks used with these codes, one pair of half-cell transitions are separated by a given level transition lasting for three half bit cells. Thus, the ratio of the longest time between transitions to the shortest time between transitions is nominally restricted to a fixed ratio. This constraint on allowable periods is used for synchronization and to establish timing windows for the detection process.

Typically, frequency domain bit synchronization techniques have been employed in conjunction with Manchester coding to clock the data, such systems including phase-locked loop (PLL) systems. In such phase-locked loop systems, timing or servo control signal data from the magnetic media is extracted and compared in a phase detector to a reference clock to generate a tape transport correction signal. Such phase-locked loop circuits normally employ sample and hold circuitry which must provide fast and accurate acquisition times, and the timing requirement is considerable. Such PLL systems are more than adequate for use in

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SUBSTITUTE SHEET hard disk drives where the rotational speed of the magnetic media or disc is intended to be relatively constant within narrow tolerance limits.

However, when the magnetic media is tape, moving in the forward and reverse direction, with speed differential ranges, by way of example, between 0.1 times normal to 60 times normal, PLL systems suffer from an inability to track such wide firequency ranges. In addition, such systems, at certain tape movement speeds have relatively long acquisition times. Furthermore, decoders for use with such systems may have "blind spots" at certain shuttle speeds, or may not work reliably over the full range.

The tape is recorded at a known fixed rate, that is at a predetermined number of bits/inch. However, when reading from tape, with a fixed sample clock and varying tape movement speed, the data pulse or bit cell interval varies as the tape speed varies, that is, when the tape slows down, the number of clock pulses for a given data pulse or bit cell interval increases, while at higher tape speeds, the number of clock pulses for a given data pulse interval is correspondingly lower. The tracking of such clock pulses is normally accomplished with a counter, however, the size or depth of the counter for very slow moving tape must be very large since the time from one transition to another increases. With a fixed sample rate, the greater the range of shuttle speeds, the larger the size of counter which must be employed.

In accordance with an aspect of the present invention there is provided a system which utilizes counters of limited depth in a decoding system which divides the time domain for facilitating decoding.

The present invention obviates many of the disadvantages of the prior art and provides further related advantages.

ΠTSCT OSTTRF OF TNVENTTQN

The foregoing and other objects of the invention are accomplished by providing a method and apparatus for decoding a data stream in Manchester I encoded format with an ANSI sync, wherein the apparatus includes a first counter for counting clock pulses for a one-half data bit cell interval in increments of 1/4 the data bit cell interval, and a second counter for counting for two data one-half bit cell intervals. For decoding, there is provided a two input state machine responsive at one input to the detection of transitions or edges in the sampled encoded data stream, and at the other input, responsive to conditional and comparative determinations based on the input data and the processed outputs of the two counters and memory (the register). The logic for the other input provides a count of clock pulses for a given transition interval and utilizes the most recent stored count information

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SUBSTITUTE SHEET from the preceding bit cell for processing bits in the next bit processing interval, with the processing in each bit period being iterated and updated until a prescribed state transition sequence is detected, after which the decoder is locked. The logic includes the first counter for counting the duration of one half bit cell intervals, the second counter for counting the duration of full bit cell intervals, first and second comparators, a register which stores the half bit cell count, and a multiplexer for selectively storing in the register either the present full interval count or the full interval count divided by two. The determination of the output of the multiplexer is dependent upon the output of the state machine, which determines which of the two values to load into the register. The output of the register is compared in the first comparator to clear the first counter at a time interval equal to the last stored one-half bit period, or after two successive quarter bit cell intervals. The inputs to the second comparator include the output of the first counter and the output of the register divided by two, with the output of the second comparator providing the second input to the state machine.

Other features and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings in which like reference numerals refer to like elements in the several views.

BRTEF DESCRIPTION OF DRAWTNOS

Figure 1 is a block diagram of the time domain decoder system according to the invention;

Figure 2 is a time line diagram showing the Manchester code format;

Figure 3 is a time line diagram showing the ANSI synchronization code;

Figure 4 is a time line diagram showing the time domain transitions utilized in the decoder system of Figure 1 for the Manchester I code witii ANSI synchronization;

Figure 5 is a diagram depicting an example of Manchester encoding of a binary data stream;

Figures 6 is a diagram depicting decoding of the Manchester encoded data stream of Figure 5 in accordance with the invention;

Figure 7 is a time line diagram and waveforms showing transitions and outputs arising from the decoding process correlated to states; and

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SUBSTITUTE SHEET Figures 8A-8C, taken collectively, are a state diagram depicting the conditions and results of the decoder system of Figure 1 for discussion and correlation of the transition states in Figure 7.

MODEfS FOR CARRYTNC OUT THE TNVENTTON

General

Referring now to the drawings, and particularly to Figure 1, there is shown a block diagram of the time domain decoder system, generally designated 10, in accordance with the invention. The system generally includes a first sample clock input line 12 and a second bi¬ phase code input line 14, a transition detector/synchronizer 16, a first interval counter 18, a second interval counter 20, a multiplexer 22, a register 24, first and second comparators 26, 28, and a main state controller or state machine 30.

For reasons which will become apparent, the counter 18 will be referred to as the T/2 counter, the counter 20 will be referred to as the T interval counter, the multiplexer 22 will be referred to as the t^! or t'/2 multiplexer, the register 24 will be referred to as the T register, the comparator 26 will be referred to as the T comparator; and the comparator 28 will be referred to as the T 2 comparator.

Since, in Manchester code, a logical one decode includes a transition at one half of a bit cell interval, the term "T" is utilized herein to represent the duration of transitions for a one half bit cell interval and is the binary counter value of a previously processed 1/2 bit cell interval count at a given point in time. The designation t' is used to represent the present binary counter value of the present bit interval being processed at the time and state a transition occurs. The processed value of this counter is used for the next T registered value. The designation t is used to represent the present binary counter value of multiples of the T value, but more importantly repeat 1 2 T values at T intervals, i.e., T 2, 3T/2, 5T/2 and 7T 2. Comparisons are repetitively made between the value t against any previously derived T value in the T 2 comparator 28 to determine the multiple T 2 intervals on a dynamic bit by bit basis to account for the situation where the number of sample clock pulses between transitions vary according to tape speed.

As will be discussed, the "T" value correlates to the number of sample clock pulses for a half-bit cell duration and, with a tape varying in speed, the number of counts per "T" value will vary according to tape speed, and hence, must be derived in real time as tape speed changes within a given range, limited, of course, by the inherent inertial moment of the tape transport mechanism. The sample clock count for each present bit interval is constantly updated by comparison against a previously derived sample clock count so that

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SUBSTITUTE SHEET any determination as to the value of any given bit interval is with reference to the count determined for the immediately preceding bit interval, or, as a minimum, the last processed bit interval. In this way, any changes in tape speed occurring in the time of reading of one bit cell to the next is taken into consideration.

The device designations and the block diagram of Figure 1 may be better understood with reference to Figures 2, 3 and 4. Figure 2 depicts the Manchester I phase modulation format for data transmission, in which the lower row designates the occurrence of clock timing edges, while the upper row designates the logical value associated with the transitions in the pulse diagram therebetween. The Manchester I code is a 2/ self-clocking code, i.e., the decoder data separation clock rate is twice the data rate. In the Manchester I encoding technique, a logical "1" occurs when there are two half-bit cell transitions in a bit cell duration. This effectively represents two transitions within a single bit cell duration, that is, two half-bit cell transitions in the same bit cell interval, and a logical "0" is a given (high or low) transition level which lasts for two consecutive half bit cell intervals. However, since the code rules require at least one transition for every data bit cell, a logical one may be thought of as being represented by an extra transition half-way between data bit cell edges. Similarly, a logical zero is represented by the absence of the extra transition.

Figure 3 shows an ANSI sync time diagram, which has been designated with time intervals designated "3T" and "T". The ANSI sync pulse, for purposes of discussion, will be referred to as 3T-T-T-3T, that is a high (or low) level signal for a duration of three time intervals, followed by a transition to a low (or high) level for one time interval (one-half bit cell duration), followed by a transition to a high (or low) level for one time interval, followed by a low (or high) level signal for three time intervals (for the purpose of this invention a time interval is equal to a one-half bit cell interval). ANSI sync detection occurs upon receipt of this unique sequence of time intervals.

When used with Manchester encoded data, the ANSI sync signal, in effect, has a portion thereof which violates the Manchester code. If a logic level remains "high" or "low" for more than one data bit cycle, this constitutes a Manchester code violation. However, the ANSI sync signal is more than just a piece or a single segment of a Manchester code violation. It is comprised of multiple pieces of code violation mixed with actual valid data. The ANSI-sync itself, termed a 3T-T-T-3T sync, where each "3T" component is a code violation (relative to the Manchester code) and in the middle are 2 legal "T" intervals. The 2 legal "T" intervals include half-bit cell transitions relative to a bit cell duration which are consistent with Manchester encoding, and provide a time interval during which "T" values may be updated for further processing.

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SUBSTITUTE SHEET To discriminate between l's, 0's and SYNC in this encoded data, in accordance with the invention, as will be described, the time has been divided into fractional time periods, or multiples of half bit intervals (with a half bit interval -T), with the duration of each period being related to or derived from the duration of the transition interval for a previous bit or sequence of bits. By dividing the time duration of the pulse train, then two transitions (a T- T sequence) in a bit cell translates to a logical "1" and one transition in a bit cell (a 2T duration) translates to a logical zero.

By reference to Figure 4, there is shown a time line diagram, depicting time (t) on the horizontal axis 40 divided into five unique intervals showing state operations, identified as "Slip", "One", Zero", "Sync" and "Slip", these being set forth in a row beneath the time line. The time line is divided into segments from the vertical axis 39 by vertical space marks with designations therebelow of "T/2, T, 3T/2, 2T, 5T 2, 3T and 7T/2". Certain vertical space marks 41a-41d, that is, T/2, 3T/2, 5T 2, and 7T/2, respectively, delineate the state operations, with the Slip within the first segment of T/2 (vertical axis 39 to mark 41a), the One in the segment between T 2 and 3T 2 (between marks 41a, 41b), the Zero in the segment between 3T 2 and 5T/2 (between marks 41b, 41c), the Sync in the segment between 5T/2 and 7T/2 (between marks 41c, 41d), and the Slip in the interval between 7T/2 and infinity (beyond mark 4 Id). Immediately above the time line, there are transition value designations which will be more fully understood with reference to the discussion of the block diagram and state diagrams, but briefly, in the second and third half bit cell intervals, designated thereabove is t' — >T (for "One"), while in the next period of two half bit cell intervals, designated thereabove is t' 2 — >T (for "Zero"). These designations refer to which T value (or count) is to be loaded into the T-register 24 during the delineated segment for the given state operation, as determined by the state output of the state machine 30. State machine 30 has, in addition to the present state bit outputs ST0-ST4, two outputs labeled SEL (on lead 66) and LOAD (on lead 49). The select signal SEL determines which input value of the multiplexer 22 will be loaded into the T-register 24, and the LOAD signal occurring concurrently with an Edge signal on lead 42 enables the loading of the selected value into the register 24 (via the RE or register enable input) at the end of a data bit cell transition interval. The "Hold T" likewise refers to the condition of the T register 24 at the "3T" portions of a Sync interval, and signifies "Hold T" during Sync, that is, decoding of the ANSI sync code.

The significance of the time line 40 of Figure 4 can be understood by viewing it as a line of state operations, the boundaries of which are initiated by a first transition (an Edge signal) and determined by the next successive transition, with the time position of the latter transition on the time line defining the state operation performed, and that state operation being the one defined for the most recent segment of the time line of which the latter

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SUBSTITUTE SHEET transition is a part. In effect, the state operations shown are mutually exclusive for processing of a given bit at any point in time. The vertical axis 39 on the time line 40 of Figure 4, for a given bit processing interval, is the time at which a transition (or Edge) signal is detected and is the beginning line for initiation of any bit processing cycle, be it a "1", a "0" or the 3T interval for a "Sync". Each vertical space mark 41 a-4 Id thereafter represents time periods measured by both of the counters 18 and 20. In the event of a second transition, that is an Edge signal, on or between any of these marks, the state operation performed (that is, the bit processing) corresponds to the operation set forth therebelow (i.e., Slip, One, Zero, Sync, Slip), so long as the second transition is at the end of or between the space marks which define the limits between state operations, that is, at the T/2, 3T/2, 5T, 2 and 7T 2 space marks, 41a-41d, respectively).

By way of example for a One state operation, assuming a first Edge signal on lead 42, and viewing this edge as having occurred at the initial vertical axis 39, the counter 18 commences counting T/2 intervals. Assuming no Edge signal at the T/2 interval, the operation continues on to "T\ Assuming no Edge signal, the counter 18 is reset and the operation continues to a third T 2 interval which takes the operation to the 3T 2 space mark 41b. If this space mark 41b is not reached with a transition (a second Edge signal), potentially, the first portion of a logical "1" has been detected (corresponding to the half-bit transition of a " 1" in Manchester code), whereupon the cycle must be repeated to determine if the portion processed is, in fact, the first portion of a logical "1" decode. On the time line 40, the state operation then restarts at the left vertical axis 39 at the onset of this second Edge signal. Again, if no Edge is detected during the T/2 count, but a third transition or Edge is detected between T 2 and the 3T/2 count (mark 41a to 41b), this verifies that the first portion processed was the initial portion of a logical "1" decode, and a data one is output at the NRZ DATA output of the state machine. It is noted that this data bit output does not occur until the end of the second portion of the logical "1" has been decoded.

Correspondingly, for a Zero state operation for detection of a logical "0", on the time line 40, from detection of the first transition and starring at the vertical axis 39, if no Edge signal is detected until between 3T/2 and 5T 2, that is, a second transition is detected between space mark 41b and space mark 41c, this is consistent with a Manchester "0" decode, and a "0" data bit is output at NRZ DATA.

From the time line 40 of Figure 4, the segments below T 2 and above 7T/2 are designated "Slip", which is an error. Briefly, if a transition occurs at or before a T/2 interval after a first transition, it is an error, since, in accordance with this invention for decoding

Manchester encoding, the interval between transitions should not be less than a one quarter bit interval or T/2; and, correspondingly, if a transition occurs later than 7T/2, that is, a

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SUBSTΪTUTE SHEET transition which takes longer than 3. 5 T after a first transition, this likewise is an error. In the latter instance, the 3T interval is the interval established for the first and last portions of the ANSI sync.

Theory of Operation

The time line 40 of Figure 4 can be visualized with a specific example of encoding and decoding with reference to Figures 5 and 6. By reference to Figure 5, and by way of example for explanatory purposes, there is depicted a simplified encoding diagram showing a line of binary data with the corresponding NRZ waveform and Manchester encoded waveform therebelow in vertical alignment. The data is represented as 11010011, with the NRZ waveform showing high levels at the "1" locations and low levels at the "0" locations. The Manchester encoded waveform shows half bit interval transitions for logical "1" and a full bit interval transition for a logical "0", the designations T-T and 2T on the waveform being used to denote the "1" and "0", respectively.

It will be observed that in this case the time interval between transitions in the Manchester waveform will be either a half bit interval T, or a full bit interval 2T. In accordance with the present invention, for decoding, the basic process rules are as follows:

1.Wait for a transition.

2.Measure the time from this transition to the next

3.Measure the time from the latest transition to the next

Observe that t' must have one of the following relations to T, with the ideal case of no waveform jitter and a fixed data rate being represented in the first column; the normal case with waveform jitter, in the second column; with the third column representing the correlation with the state operation

Ideal Case With Jitter State Operation

(a) t' = l/2 T t' < l/2 T SLIP

(b) t' = T l/2 T ≤t' < 3/2 T ONE

(c) t' = 2T 3/2 T ≤ t' < 5/2 T ZERO

(d) t' > 5/2 T SLIP

4.1n the case of (a) or (d) the result is indeterminate and the state operation is defined as Slip; in the case of two sequential occurrences of (b), "clock out" a logical "1"

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SUBSTITUTE SHEET on the second occurrence, and replace T with t' (represented in Figure 4 as t' -> T); and in the case of (c) "clock out" a logical zero during the second T of the bit cell interval and replace T with 1 21' [listed in step 3(c) as t' = 2T and represented in Figure 4 as t'/2 -> T]

5.The clocked out data is thus the original data recovered.

6. After acquisition, repeat steps 3 through 5.

Steps 1 and 2 occur during the acquire phase of the operation, whereupon, steps 3 through 5 are iterated during processing thereafter. Figure 6 depicts the result of the application of this decoding process in graphical form where the Manchester encoded data stream of Figure 5 is reproduced, with the "Measurements "row therebelow showing the corresponding value of t' relative to T according to Step 4. The "Recovered Data" row shows the binary result in accordance with Steps 4 and 5, with the recovered data corresponding to the original input data in the first row of Figure 5.

For the ANSI sync situation, since the 3T interval is a violation of the Manchester code, and since some form of count is required to detect the 3T interval, provision is made within the system for maintaining the last T value during the time period of the 3T transition, this event corresponding to the "Hold T" designation in Figure 4. In short, the last valid T count is held for comparison purposes to predict the duration of the interval to the next transition and no attempt is made to use a 3T count derived from the 3T portion of the ANSI sync.

The Block Diagram of Figure 1

Referring again to Figure 1, the system 10, includes the first input or sample clock line 12, the second input or bi-phase encoded data line 14, the transition detector/synchronizer 16, the T/2 counter 18, the T interval counter 20, the multiplexer 22, the T-register 24, the first and second comparators 26, 28, and the bi-phase decoder main state controller or state machine 30.

The output signal of the transition detector/synchronizer 16 appears on lead 42, which signifies detection of a transition identified as an "EDGE" signal, and is coupled as an input to the state machine 30, as a first input to an OR gate 46 via lead 44, the other input of which is received over lead 52 from the T comparator 26. The Edge signal on lead 42 also provides a first input via lead 47 to a two input AND gate 48, the other input of which is received over lead 49 from the load (LOAD) output of the state machine 30. The sample clock 12 of this invention is a fixed rate clock and its input is transferred over lead 12 to provide a clock signal to the state machine 30, a clock input to the counters 18 and 20, the T- register 24 and a synchronous clock input to the transition detector 16. The counter 18 is a

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SUBSTITUTE SHEET nine bit counter, as signified by the numeral "9" on the output lead 50 (the output being the "t" value as designated), which provides a first input, designated B, to the comparator 26, and a first input designated B ' to the second comparator 28. The output of comparator 26 appearing on lead 52 provides a second input to the two input OR gate 46, the output of which is coupled to the synchronous clear (CLR) input of counter 18.

The interval counter 20 is a ten bit counter, as signified by the "10" on the output lead 54 thereof , with the output, representing the t' value (as designated in the drawing), providing a first A input to the multiplexer 22, the second input B of which is received from lead 54 through a "divide by two" operation 56. The terminal count (TC) output of counter 20 is coupled to the inverted synchronous enable (EN) input thereof over lead 58 and is used to inhibit counting when a transition interval is out of range of the decoder T interval counter size. This prevents limit cycling and decoder failures. The nine bit output of multiplexer 22, appearing on lead 58 (either t' or t'/2 as designated thereon) is input to the T-register 24 under control of the output from AND gate 48 over lead 51 to the synchronous register enable (RE) input, the nine bit ouφut "T" of register 24 being fed, via lead 60, to the A input of comparator 26 as well as to a divide by two operation in block 62, the divide by two being a logical shift right of the binary data. The output of the block 62 provides the A' input to the comparator 28, the B' input of which is provided from counter 18 over lead 50. The output of comparator 28 (A'=B') (or T 2 compare) provides a second input to the state machine 30 via lead 64, the first input to which is Edge via lead 42.

The state machine 30 has a five bit state ouφut, designated ST0, ST1, ST2, ST3, and ST4, as well as the load (LOAD) ouφut on lead 49 and the select (SEL) ouφut on lead 66. The outputs of the state machine 30 are state bits which have associated states assigned to them that derive the NRZ CLK (clock) ouφut, the NRZ DATA ouφut, the ANSI SYNC ouφut, the load (LOAD) signal ouφut via lead 49 and the select (SEL) ouφut, the last of which provides an input, via lead 66, to the select (S) input of multiplexer 22, all of which, along with the counters, are synchronous to the sample clock 12.

Operationally, lead 14 to the transition detector 16 is designated Bi-0, or bi-phase, this designating a Manchester I code, which is referred to as bi-phase mark, or split mark. The input is clocked into the transition detector /synchronizer 16 by the sample clock signal input on lead 12. The transition detector 16 looks for a level change denoting a transition from either a high level to a low level, or from a low level to a high level. In either event, upon detection of a transition, the detector 16 outputs a time-delayed one sample clock wide pulse signal over lead 42. This signal on lead 42 is designated "EDGE" which, as will be seen in the state diagram of Figures 8A-8C is a triggering condition, the presence or absence

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SUBSTITUTE SHEET of which, along with the other triggering condition of A'=B\ determines the path between states of state machine 30.

The transition detector/synchronizer 16 is basically a modified shift register of four flip-flops, the contents of which are clocked by the sample clock 12. In the detector/synchronizer 16, the modification includes an exclusive OR of the two final stages so that the only time there will be an ouφut is when the values at the outputs of the flip-flops of the two final stages differ. The sample clock 12 frequency is at a higher rate than the data stream input transitions via lead 14. The Edge signal on lead 42 is provided as a first input to the state machine 30. The signal on lead 42 is also provided as an input, over lead 44, to the synchronous clear (CLR) input of the T counter 20 and as one input to the two input OR gate 46, the ouφut of which is connected to the synchronous clear (CLR) input of the T/2 counter 18. The input on lead 42 to state machine 30 signals to the state machine that a new transition bit interval is starting and the last one is complete. The input to OR gate 46 signals the nine bit T/2 counter 18 to begin calculating the next T 2 bit interval, and it signals the ten bit T interval counter 20 to begin calculating the next T bit interval. The "counts" to the T 2 counter 18 and the interval counter 20 are sample clock counts provided by clock signals over lead 12 to the clock inputs of the counters, that is, both counters increment on the occurrence of each clock cycle, except at prescribed "clear counter" points where the counters are reset to zero, and when the T interval counter exceeds its range.

With the Edge ouφut on lead 42 high and then low synchronous with the clock 12, there will be a high input provided to each of the state machine 30 (via lead 42), one input of AND gate 48 (via lead 47) and one input to OR gate 46 (via lead 44). In effect, starting at a given point after acquisition, this Edge signal is then an initiating transition for determination of the applicable logical rules set forth as Step 4 in the above Theory of Operation portion, with the process running in steps 3 through 5 thereafter. The T/2 counter 18, receiving the sample clock 12, will provide an increment in the "t" count at each clock to commence counting to measure the time to the next T/2 transition for the next decode state change via state machine 30. The "t" ouφut of counter 18 will be input, via lines 50, to the B input of comparator 26 and the B' input of comparator 28. The clock input over lead 12 and the high ouφut from transition detector 16 will also be provided, via lead 44, to the counter 20, these two signals being input to the clock and clear inputs of counter 20, respectively. Counter 20 is counting along with counter 18 to measure the time to the next transition (Step 2). The ouφut of counter 20 (designated t') will be provided, via lead 54, as a first A input to the multiplexer 22, and, via a divide by 2 operation (t'/2) in block 56 to the B input of the multiplexer 22.

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SUBSTITUTE SHEET The nine bit T 2 counter 18 and the ten bit T interval counter 20, both of which run in parallel, have slight operational differences. Counter 18 is a nine bit counter, rather than ten bits since it only counts one 1 2 bit cell interval, that is a T interval, whereas the ten bit counter 20 has to count clock pulses representative of the transition duration for a logical zero value which requires analysis over two 1 2 bit cell intervals, that is, a 2T interval. The counter 20 counts the number of sample clocks which occur between transitions.

The ten bit interval counter 20 has a multiplexer 22 accepting its ouφut as a whole value or half value and selects either the t' value or the t' 2 value of the presently processed bit interval. In effect, in accordance with the determination of Steps 3(a)-3(c), the time between transitions will affect the ouφut in accordance with Step 4 of the Theory of

Operation. The selection is controlled by the state outputs of the state machine 30 via the select (SEL) ouφut on lead 66 to determine which value will be selected via multiplexer 22, that is t' or t'/2.

For the selection process, if the state machine 30 is doing the "one" decode (a period between transitions commencing at vertical axis 39 and ending between T 2 and 3T/2 on the time line 40) it would pass the interval count or t' value of the ten bit counter 20, via multiplexer 22, directly to the latch or T-register 24. If the state machine 30 is processing for a "zero" decode (a period between transitions commencing at vertical axis 39 and ending between 3T 2 and 5T 2 on the time line 40), it would select the B input of the t' or t' 2 multiplexer 22, via the divide by 2 operation 56, which would pass the processed interval count to the latch or T-register 24. Since the "Zero" state operation decode requires analysis over two half bit cell intervals, the accumulated count in the counter 20 for a "Zero" decode would be "2T", and with the divide by 2 operation 56, and the state machine 30 selection process, via select (SEL) lead 66, would transfer the two half bit cell interval value, divided by 2, to the T-register 24. The divide by two operation enables counting for a full bit cell time duration equal to decode of a logical "0", that is, a 2T interval, with the division providing a T value for comparative or reference purposes for subsequent transition interval analysis.

The selected ouφut of the multiplexer 22 then is loaded, via lead 58, on the next bit cell boundary (Edge) into the T-register 24 assuming the state machine 30 Load signal 49 is true, and is used as the next T for processing the following bit decoded value. The "load" signal ouφut of the state machine 30, via lead 49 to the AND gate 48 of the T-register 24, in conjunction with an 'Εdge" on lead 47, signals storage or loading, via lead 51, at the "RE" input of the register 24 of one of the t' value or t' 2 value from multiplexer 22 into the T- register 24, and the determination of which value is based on the time interval determined

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SUBSTITUTE SHEET for the transition interval of the data bit cell as shown in the time line 40 diagram of Figure 4, where it shows t'->T or t'/2->T (Step 4).

There are two comparators, the T 2 comparator 28 which is used to derive state transitions in the state machine 30, and the T comparator 26 which rolls the T 2 counter 18 back to 0 at full T increments, that is, it resets the counter 18 after the Υjl counter 18 has counted two quarter bit intervals, this being required to pass through the count value of T/2 for state transitions of the Figure 4 time domain. The basic concept runs on quarter bit cell duration intervals T/2, with the "T" above the line in Figure 4 being the binary count for the previously derived one-half bit cell interval. So the state machine 30 will have transitions in the state diagram at each T 2 interval or quarter bit cell interval. The top counter 18 is cleared in one of two cases, either at a detected transition signal on lead 42, or when the count within counter 18 has reached the whole "T" interval count, that is two T 2 intervals. The reason for this is that the counter 18 provides one T/2 interval count for the T 2 comparator 28 per T count cycle. When T counts are repeated, the T/2 count occurs at T 2, 3T/2, 5T 2, 7T/ 2, etc. The counter 18 is thus counting T 2 (quarter bit cell) intervals with the counter reset at each half bit cell interval T. The T/2 comparator 28 is making comparisons every half bit interval, as a result of which the states of the state machine 30 are changing every quarter bit cell interval (T/2).

The outputs of comparators 26 and 28 are labeled A=B and A'=B\ respectively. The upper comparator 26 has an ouφut, that is, A=B, when the contents of T-register 24 equals the T 2 counter which 18 has counted a half bit cell or T interval. The function of comparator 26 is only to reset the counter 18 at each half bit cell interval. The T 2 comparator 28 has an ouφut, that is A'=B\ on the boundaries of the periods shown in the time line diagram of Figure 4, that is at T/2, but not "T" intervals, e.g., at T/2, 3T 2, 5T/2 and 7T/2.

The State Diagrams

The operation of the block diagram of Figure 1 can be better understood with reference to the ouφut diagram of Figure 7 correlated to the state diagram of Figures 8A-8C. In the state diagram, the circles correspond to one of the four state operations set forth on the lower row of Figure 4, that is SLIP, ONE, ZERO, and SYNC, which arc respectively designated within the circles as "SUP", "1", "0", and "S", with a second "SLIP" operation for a transition occurring in a period at or beyond 7T/2. In addition, within the circles, there are sequentially numbered designations from 0 to 30, which are the states of the state machine 30 and will be used for ease of reference during the description thereof, and as keys between the state diagram of Figures 8 A-8C and the diagram of Figure 7.

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SUBSTITUTE SHEET With respect to the syntax used in the diagram, there are several basic elements found in the state diagram for communicating information, the first being the state number - an arbitrary assignment of the state space of which the state machine will transition. The transitions between states are triggered by two events, an Edge signal and A'*=B' , either the one or the other occurring or both occurring simultaneously. Also in each circle there is a description of the decoder state as to what state operation is being performed, i.e., Slip, a One decode, a Zero decode, or a Sync decode. So the state machine 30 has assigned to it four basic operations, each of which may occur in different states.

For each circle representative of a state, there are arrows that leave the circle and go to the next, or another, state. Within the state diagram, of the two triggering events, the "Edge" signal indicates the occurrence of a transition, and the A'=B' event indicates an ouφut of the T 2 comparator 28. From a given state, alternate paths exist to other states (as shown by the arrows), with the alternate path taken being determined by the triggering event For example, in Figure 8A, from State 0, there is a first path to State 1 with the notation adjacent the path showing A'=B\ this being the triggering event for transition from State 0 to State 1; the second path shows a transition from State 0 to State 0, with the notation Edge + A' ≠ B', this being the triggering event or idle case for transition along this path. In those events in which both triggering events occur simultaneously, the state transition path with Edge takes precedence insofar as transfer to the next state.

On each state circle there is a small arrow that leaves the circle and returns to the circle, which is to indicate the condition at which the state machine 30 is holding within a given state in the absence of one or the other or both of the triggering events. What that means, for example, is that once in state 1, with neither an Edge, nor an A'=B' (a T/2 compare is not occurring), the state machine stays in that state.

Also shown on the state diagram alongside the circle is t' -> T, or t'/2 -> T. With that statement, i.e. t' -> T, it is implied that the multiplexer 22 looks for t' directly to be loaded into the T-register 24. Note, that in order for that to occur, the state machine 30 must have the LOAD line 49 held high with the SEL line 66 held low (SEL=L, A input selected), as well as an Edge pulse signal on lead 47, whereby the AND gate 48 enables loading the register via line 51. When LOAD is low, the process is in a holding mode. Viewing the block diagram of Figure 1, the LOAD signal would appear on line 49 which is an enable input to AND gate 48, and, with a low input on an AND gate, the ouφut will be zero, which means the register 24 is not enabled.

At the top left of Figure 8A, adjacent the upper left circle designated SLLP in State "0", the ouφut function and arguments of the state machine are designated in the form

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SUBSTITUTE SHEET f [ST, Edge, A'=B']->[ST, LD, SEL, CLK, DATA, SYNC].

The left hand side of the equation sets forth the function (f) of the arguments (ST, Edge and A' = B') with the right hand side being the corresponding outputs of the function (f), that is, the outputs of the state machine 30. The argument ST on the left side equates to the "present state" (set out in Tables 1A-1H below as "Present ST') while the ouφut "ST" on the right side of the equation corresponds to the "next state" (set out as Next ST in Tables 1 A-1H). The argument 'Εdge" corresponds to transition detection on lead 42 and the argument A'=B' corresponds to the ouφut of comparator 28 on lead 64, these being the two inputs to the state machine 30. The ouφut functions on the right are ST, or state; LD, or the "load" signal from state machine 30 appearing on lead 49; SEL, which is the select ouφut from state machine 30 appearing on lead 66; CLK which is the NRZ CLK ouφut of state machine 30; DATA, which is the NRZ DATA ouφut of state machine 30; and SYNC, which is the ANSI SYNC ouφut of state machine 30. The outputs of the state machine 30 are used for controlling the associated components in the decoder 10 and for signaling the subsequent circuits in the system. Following each state circle in the state diagram, there is a bracketed logic statement, such as [1,0,0,1,0], each position of the bracketed statement being the binary logic level of the last five of the six ouφut variables in the above equation, that is, the true or not true level of LD, SEL, CLK, DATA and SYNC, respectively. The state variable ST is omitted since the state is expressed by the small numeral within the circle. In the state diagram of Figures 8A-8C, there are 31 states shown, that is, states 0-30, this resulting from the five-bit ouφut (ST0-ST4) of the state machine 30 which allows 2⁵ states, or 32 states, of which one is not assigned.

Viewing the bracketed binary arguments or statements in Figures 8 A-8C, those show the present control state output Looking at State "1", showing t' -> T, the SEL (select bit in the second bit location) = 0, which implies that the A path through the multiplexer 22 is used in loading the T-register 24 under the load conditions. That means that the t' count value is loaded into the register 24. The reason is that the bit interval being processed for that state is a T interval. Now in the case of State 2, showing t' 2 ->T, the t'/2 value is loaded into the T-register 24, since the bit interval being processed for that state is the decoding of a logical zero, two T intervals are being processed. The bracketed argument for state 2 shows "1" in the SEL (select bit in the second bit location), and, with SEL high, this would select the B input of multiplexer 22 for loading into the T-register 24, that B input being t'/2. In Manchester code, for decoding a zero, there are 2 T's.

Therefore, since the t' count is representative of 2 T's, a divide by 2 operation 56 enables providing a T value to be used for the next bit processing interval. Consequently, whenever SEL is true, the "divide by two" operation 56 is selected for input through the B input of the

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SUBSTITUTE SHEET multiplexer 22. This is because the decoder 10 is in a Zero decode operation, and, for decode of a logical "zero", there are 2 T's measured.

Tables 1 A through 1H, set forth below, list, in tabular form, much of that which is set forth on the state diagram of Figures 8 A-8C. The column headings are designated Present ST (state) , Present A' = B\ Present Edge, these being the function arguments, with the ouφut function columns labeled Next ST (state), Next LD, Next SEL, Next NRZCK and Next NRZDT and Next SYNC, these column heading corresponding to the outputs depicted on the state diagram. The bracketed logic notations in the state diagram correspond to the last five columns of the Tables for a given state transition from one state to another, with the first column of the arguments listing the "next state" transition alternative from a given state. The State diagrams of Figures 8a-8c contain an additional item of information, that being the transition interval value information being loaded into the T-register 24.

The outputs to the right of the arrow in the above equation are state variables or control flags. LD directs loading of the T-register 24 when LD is true. The SEL ouφut signals the multiplexer 22 as to which value to transfer to the T-register, that is, the t' value associated with decoding a logical "1" or the t'/2 value associated with decoding a logical "0". Thus when the state machine 30 asserts a true LD signal and a transition or edge occurs, that is the necessary combination to store a new value "T" in the T-register 24. The outputs NRZ CLK, NRZ DATA and ANSI SYNC are derived from the state information and basically take the state information and provide a useful ouφut from the decoder 10. The outputs are set forth for each of the states in the tables below and depicted in Figure 7 with respect to the decoding operation in accordance with the relevant state sequences to be described.

The state diagram is divided by horizontal divided lines into two main state modes, these being "ACQUIRE" mode (Figure 8A) and "LOCKED" mode (Figures 8B and 8C), these two designations appearing at the left in a rectangle just above the horizontal broken lines. The LOCKED mode includes a further substate mode, below the broken line of Figure 2B, this mode being designated as ANSI SYNC, positioned within a rectangle at about the lower middle part of the page. ANSI SYNC is a "locked" condition, that is, in synchronization. The Sync detected ouφut is used by other subsequent circuitry (not shown) to frame the serial data to produce framed parallel data words used by the system. The state diagram of Figure 8 A is also divided vertically into three segments, the leftmost segment being designated "START'; the center segment being designated "LOOK FOR ONE"; and the rightmost segment being designated "LOOK FOR ZERO".

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SUBSTΓΓUTE SHEET As will be described, the decoder 10 first looks for a logical sequence consistent with the Manchester I code, that is a valid or legal bit combination of 1-0 or 0-1, after which the decoder is "locked", that is the ouφut of the decoder is synchronized to the input For locking the decoder ouφut to the requirements of circuitry thereafter, ANSI sync is utilized. It is to be understood that the invention is not limited to the ANSI sync and any sync may be used, preferably a sync with a bit time interval combination which is violative of the Manchester I code rules.

For purposes of explanation of the state diagram of Figures 8 A-8C, and how the decoder 10 would process the Figure 7 encoded Manchester data, an assumption is made that at state 0, the T value is currendy a correct value or approximately a correct value. If the T value is not correct the state machine 30 would follow States 0, 1, 2, 3, 4 in some order to acquire a T value from a previous bit that was approximately correct

At State 0, with a T value which is approximately correct, initiated by the last Edge signal or transition, which would place the sequence at the far left of the waveform of Figure 7. The process is at State 0 there, and then the T/2 counter 18 begins to count. Knowing that the counter 18 counts T intervals and one-half way up to the T interval, a T/2 compare occurs, which is indicated by A'=B' (adjacent the path line from State 0 to 1), a state transition occurs from State 0 to State 1 at the T 2 count The T 2 counter 18 would then continue to count up to T and reset to zero; however, in this case, an Edge signal occurs. When Edge happens, State 1 is exited and, as indicated on the waveform of Figure 7 and in the diagram of Figure 8 A, the process goes to State 9 after exiting the "ones" state in Acquire to the "Look for Zero". At State 9, both counters are cleared because of the OR function on 18 and the direct clear on counter 20.

The process is now at State 9, with both counters 18 and 20 reset and then both counters begin counting again, Counter 18 would again cross through T 2 indicated by A'=B' (the second occurrence on the waveform of Fig.7), and State 9 now transitions to State 10. Then another Edge occurs, and following Figure 8A, when Edge occurs the path returns back to State 9, because the decoder 10 is now looking for a logical zero. The assumption is that a present T value has been loaded and decoder 10 has just processed a segment of a One, and now it needs to find a logical zero to confirm the T value selected. So, the decoder 10 is in State 9 and the T/2 and T counters are reset at the Edge signal and now start counting again. The process then crosses the T 2 value (following time line of Figure 4), which takes the process to State 10, and at State 10 and before the occurrence of Edge signal on lead 42, the counter 18 would count up to T and reset So then another T interval is counted at which a T/2 point is crossed, at which time the process then jumps to

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SUBSTΠΓUTE SHEET State 11 (crosses the 3T/2 of Figure 4). Notice the absence of a transition in the signal; the Edge signal has not occurred indicating no transition and that a zero or sync bit is still being processed.

In State 11, on occurrence of an Edge signal, that Edge would causes a transition from State 11 to State 16 which is to the "locked" state. In this example it has taken two bits, a one data bit and a zero data bit to force acquisition. In general, in accordance with the embodiment herein described, it is necessary to have a decoded one and zero combination, or a decoded zero and one combination for acquisition to occur.

Starting at the second "1" in the upper waveform of Figure 7, which is the third bit, the decoder is now at state 16, and in "locked" condition, that is, the data is locked to the state sequence for decoding Manchester data. For processing and decoding of the incoming data stream, State 16 may be viewed as the ground state of the decoder 10, that is, the beginning of each decode value(vertical axis 39 of Figure 4). At state 16, referring to Figure 8B, a "SLIP" is being decoded. Referring also to Figure 4, where Slip is shown as the state operation, the process remains in Slip until a transition is detected at T/2. For a One operation, it is not on the first occurrence of that interval, it's on the second occurrence of that interval that satisfies the requirement an NRZ data "1". Accordingly, the state machine has two "one" intervals that it processes, and on the first one, it does not ouφut a clock, that is, Figure 4 shows the time domain which requires two occurrences of the "one" operation before outputting a clock.

Starting at state 16, which is the ground (or Slip) state for decoding a value, NRZ DATA goes arbitrarily high, an NRZ CLOCK pulse and ANSI SYNC remain low, and counter 18 starts to count, and crosses T/2 which is A'=B'; this transitions to State 17. From State 17, the counter 18 continues to count The Edge signal occurs. Before the occurrence in Figure 4 of a 3T 2, again the counter gets an Edge, so it doesn't exceed the range T/2 to 3T 2, and it resets to zero. Now the decode process is back to the vertical axis 39 of Figure 4. But, due to the Edge, the process exits to State 13, at which point there has been processed one of the two T intervals of the logic "1". At state 13, the counter 18 counts, T 2 is crossed, which puts the decoder into the "One" operation state and also into State 14 on Figure 8B. For a "one" decode, the count does not exceed the range of T 2 to 3T 2, then an Edge occurs, and at that point in time, a "CLK" signal is ouφut, as denoted by the third bit of the bracketed statement In the diagram of Figure 8B, the third field bit is shown as a "(0/1)", which indicates a transition from false to true of the bit on the occurrence of edge while in State 14. Consequently, there is ouφut a clock with the data "1". At the ouφut of the state machine 30 an NRZ DATA "1" clocked out.

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SUBSTITUTE SHEET The process then returns to ground state, State 16, the beginning of a new bit. As shown in Figure 7, after decode of the 1-0-1, the system will, by way of example, process the ANSI sync code. From State 16, the first 3T of the sync follows. After a T/2 compare occurs, the process jumps to State 17. Between States 17 and 18, counter 18 will rollover, that is, it will reset midpoint between states 17 and 18 (Figure 7), and another T interval count is started at which point at T 2 again, which now in time is 3T 2, there is another state transition to state 18. Between states 18 and 19 another interval of T is counted, counter 18 clears and starts another interval, and, on crossing T 2 again, State 19 is entered. However, at this point the legal Manchester threshold of 2T maximum (with jitter, it's 5T 2) has been crossed. At this point, there is a code violation while processing a 3T interval. This is the reason for the dotted line between "LOCKED" and "ANSI SYNC" in Figure 8B.

In processing what is believed to be a Sync, and in order to determine it is a SYNC, a prescribed sequence must be followed. It cannot be decoded as a Sync until the 3T - T-T- 3T combination exists. From State 19 an Edge occurs as shown at the transition to State 21 on Figure 7. That Edge signal results in following the path for decoding a Sync, which goes to State 21, which indicates the transition terminating a 3T interval, after which the decoder is looking for a "1". From Figure 7, there is a logical "l"(aT-T interval) in the middle of 2 3T intervals. At State 21, the decoder is beginning to process that T-T portion in the state diagram.

At state 21, the counters are reset and start counting again. From State 21, counter 18 counts through T/2 causing a transition to State 22. An Edge occurs and transitions the process to State 24 to begin processing the next transition interval, which should be another "One" operation (a IT interval representing the second portion of the NRZ "1"). The counter continues and at T/2, there is a transition to State 25 and, with an Edge, to State 26. From there another 3T interval is processed in the manner previously described, through States 27, 28 and 29, and at State 29 the system is in the correct time window for an ANSI SYNC. On the state diagram of Figure 8C, in the fifth bit location corresponding to the Sync argument in the bracketed statement, it shows "(0/1)", at which point on occurrence of an Edge, die Sync goes true during State 29 to denote an ANSI SYNC.

Now, since the state machine is synchronous to the sample clock, and the ANSI

SYNC pulse is synchronous to the sample clock, the subsequent stages of circuitry (not shown) that use the decoded data are synchronized to the sample clock. For example, the Sync is used to initialize the following circuitry, such as a serial to parallel converter, by

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SUBSTITUTE SHEET resetting a divide by eight counter of a serial to parallel converter, whereby the counter would count 8, and would shift data into the shift register 8 times, then parallel load into an ouφut register and start the next shift operation. An NRZ data clock is also ouφut and has to be used as a clock enable in the shift register and serial-to-parallel divide by eight counter because the NRZ data is a static value - high or low. The NRZ clock could be used, for example, as a clock enable on a serial-to-parallel divide by eight counter and serial-to-parallel register, with the sample clock used as a synchronous clock.

After processing a SYNC, that is, after processing the second 3T , Edge returns the process to ground State 16 in the locked condition, where the following data Zero of Figure 7 can be processed. In processing the data zero, as previously discussed, at T 2 there is a jump to State 17. In die absence of an Edge knowing that counter 18 resets at "T\ and then counts up through another T 2 interval to 3T 2 which is shown at State 18, there is a transition from State 17 to State 18. From state 18 at the occurrence of Edge, an NRZ clock is ouφut(shown as (0/1) at the third bit location of the bracketed statement) with the data being zero (fourth bit location in the bracketed statement). Thereafter the machine returns to ground state, State 16.

So whether the decoder is processing a data "one" or a data "zero", the clock is ouφut only during the second T interval. For a data "one" decode operation, which has two paths in the state diagram, on d e first path (from State 17 to State 13), the Edge does not produce a clock. During the second path of State 14 back to State 16, the state transition with an edge does produce a clock (NRZ CLK). Thus there is an NRZ clock for every second occurrence of the T interval .

For processing a data zero, the state path goes from state 16 to 17, and in the absence of Edge, to State 18 at the next T 2 interval. At State 18 when an Edge occurs, an NRZ clock is produced witii die data being held low, and then returns again to ground state, State 16.

For bit processing, with the decoder 10 locked, ground State 16 can be thought of as the beginning of a bit interval, be a sync bit interval or a data bit interval. That process then continues thereafter or until a condition exists which causes the decoder into a state transition for a SLIP case, in which event it would fall out of "locked" and go back to "Acquire".

Recapping with reference to the Figure 4 time line 40, the decoder 10 falls through the "One" operation two times, and on the second occurrence produces a clock; for a "Zero"

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SUBSTΪTUTE SHEET operation, the decoder 10 falls through the "Zero" one time and puts out a clock; and for die "Sync" operation, it falls through the Slip, the One, the Zero, into the Sync interval. At the first portion of decoding die Sync, it goes through (a) a Slip, a One, a Zero and a Sync; (b) a Slip, a One; (c) a Slip, a One; and (d) a Slip, a One, a Zero, and a Sync, and outputs a Sync pulse; and during the second 3T portion, die same process as the first 3T portion, after which die SYNC pulse is ouφut

The following trutii tables show in tabular form that which is depicted in graphical form in the state diagram of Figures 8A-8C. The first column is equivalent to the encircled present States in the state diagram, with the second column of A'=B' corresponding to the first triggering event (i.e., the ouφut of comparator 28 appearing on lead 64 in Figure 1). The third column corresponds to the second triggering event, that, is the "Edge" signal appearing on lead 42 at the ouφut of d e transition detector 14 in Figure 1, these two signals along with die sample clock signal on lead 12 providing the inputs to d e state machine 30. These are equivalent to the left hand side of d e equation set forth in Figure 8A, that is, d e function (f) of the arguments ST, Edge and A'=B\ On die right of die => sign in the following tables there are the corresponding outputs of the function (f), that is, the outputs of the state machine 30, tiiese being listed as "Next ST', "Next LD", Next SEL", Next NRZCK", Next NRZDT', and "Next SYNC", tiiese corresponding to the ouφut designations in Figure 8 A. In effect, the following is a tabular representation of die graphical depiction of Figures 8 A tiirough 8C.

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SUBSTITUTE SHEET

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SUBSTΓΓUTE SHEET Table IB

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SUBSTITUTE SHEET Table 1C

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SUBSTITUTE SHEET Table ID

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SUBSTITUTE SHEET

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SUBSTΓΓUTE SHEET Table IF

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SUBSTITUTE SHEET

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SUBSTΠΓUTE SHEET

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SUBSTITUTE SHEET In accordance widi the instant invention, the duration between transitions is constandy monitored by the counters 18 and 20, which are incremented according to the sample clock 12, operating at a fixed rate. As the tape speed increases or decreases, die time duration between transitions, as represented by tiiese counts, varies. Yet, wid the instant invention, counters of limited depti may be reasonably employed since one counter is counting to IT, by useful means of T 2 increments, and tiien being reset, while the other is counting sample clock count pulses to a maximum duration of 2T. With the speed range of tape movement known, and sample clock frequency known, counters of proper minimum size may be conveniendy employed. Each successive bit interval is processed according to the count determined for T in the preceding interval on the time domain scale thus maintaining the T count per bit interval proximate to the most recent tape speed at all times. While there has been shown and described a preferred embodiment, it is to be understood d at various other modifications and adaptations may be made widiout departing from d e spirit and scope of the invention.

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SUBSTITUTE SHEET

Claims

What is claimed is:

1. A mediod for decoding digital data comprising:

providing a data stream on magnetic tape encoded at a predetermined bit density;

providing a sample clock operating at a predetermined frequency;

providing a state machine for outputting state operations in response to triggering events;

during playback of the magnetic tape at a speed within a range of speeds, generating, as a first triggering event, a signal for each transition in said data stream;

providing logic means including comparing means and responsive to said sample clock, said state machine and said transition signal for

(a) measuring, via said clock pulses, an interval T between adjacent transitions;

(b) measuring, via said clock pulses, an interval t' between die last of the adjacent transitions and a next succeeding transition;

(c) storing die value of the interval T;

(d) comparing, the relationship between interval T and interval t' to determine if the relationship is one of:

(i) t' < l/2 T (ϋ) l 2T ≤ t' < 3 2 T

(iii) 3 2 T < t' < 5 2 T

(iv) t' ≥ 5 2 T

in the case of step (d)(ii), inputting the results of the comparing into d e state machine and clocking out of said state machine a logical one on the second occurrence of interval T of such determination and, for each occurrence of interval T, replacing the stored value T widi a value oft';

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SUBSTITUTE SHEET in the case of step (d)(ϋi), inputting the results of die comparing into the state machine and clocking out of said state machine a logical zero during die second interval T and replacing the stored value T widi a value of t'/2; and

in die case of step (d)(i) or (d)(iv) clocking out of said state machine a state operation for reinitiating step (d).

2. The method of claim 1 wherein die step of measuring, via said clock pulses, includes first and second counters.

3. The method of claim 2 wherein one of said counters has the capability of counting to a value generally more than twice that of die otiier of said counters.

4. The mediod according to claim 3 wherein the step of storing the interval T includes means for selecting die value of said one counter or one half the value of said one counter for storing depending on die determination of die relationship in step (d).

5. The method according to claim 1 wherein said encoded data stream is Manchester I encoded data and wherein said data stream further includes a data segment including transitions which exceed transitions in accordance widi die Manchester I format, and wherein said method includes holding a stored value T derived from a valid Manchester I bit interval for a time duration required to compare interval T and interval t' to determine if 5/2 T < t' < 7/2 T.

6. The method according to claim 5 wherein said data segment is a portion of an

ANSI sync pattern.

7. The method according to claim 1 wherein said encoded data stream is Manchester I encoded data and wherein said data stream further includes a data segment including transitions which exceed transitions in accordance widi die Manchester I format, and wherein said step (d) of comparing includes determining if said relation ship is also one of

(v) 5/2 T ≤ t' < 7/ T; and

(vi) t' ≥ 7/2 T

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SUBSTΓΓUTE SHEET and, in die case of step (d)(v) holding a stored value T for a time duration necessary to determine if a transition occurs within die time span, and, if die transition occurs in a time interval determined in accordance with step (d)(vi), clocking out of said state machine a state operation for reinitiating steps (a) through (d).

8. A method for decoding a data stream recorded on a magnetic tape at a given density, widi die tape, during decode, operating at any speed widiin a range of speeds, said mediod comprising:

(a) providing a sample clock operating at a predetermined frequency;

(b) providing a signal at each transition in said data stream;

(c) counting die number of sample clock pulses between successive occurrences of said signals;

(d) storing a reference value proportional to die number of clock pulses thus counted;

(e) counting d e number of sample clock pulses between the last of said successive occurrences of said signals to the next successive occurrence of said signals;

(f) comparing the number of pulses thus counted against said reference value;

(g) providing a state machine responsive to said sample clock, each said signal and said comparing for decoding at least die next successive bit interval of said data stream.

9. A mediod for decoding successive segments of a Manchester I encoded data stream recorded on a magnetic tape at a given density, the decoding occurring widi d e tape operating at any speed widiin a range of speeds, said mediod comprising:

providing a sample clock;

providing an edge signal synchronized to said sample clock at each transition in said data stream;

providing a state machine synchronized to said sample clock and receiving, as a first input each said edge signal;

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SUBSTITUTE SHEET providing a first counter synchronized to said sample clock for counting to a first maximum count value;

providing a second counter synchronized to said sample clock and having a second maximum count value of at least twice said first maximum count value;

providing a register synchronized to said sample clock;

initiating d e counting of sample clock pulses in said first and second counters in response to a first one of said edge signals;

providing an ouφut from said first counter in response to one of a next edge signal and a first maximum count value;

generating a load signal from said state machine in response to a processed ouφut from said first counter;

providing an ouφut from said second counter in response to one of a next edge signal and a condition of reaching die ττ^*ιa^*χ^*iττ ^*m count value;

coupling the ouφut of said second counter to a multiplexer having as a first input the ouφut of said second counter and, as a second input, a value equal to one-half the ouφut of said second counter;

generating from said state machine a select signal determined by die relative ouφuts of said first and second counters;

in response to said select signal, coupling the selected one of die inputs of said multiplexer to said register,

loading the ouφut of said multiplexer into said register on concurrence of an edge signal and said load signal;

comparing the value of said register with d e ouφut of said first counter and, on a compare, resetting said first counter,

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SUBSTITUTE SHEET comparing one half the value of said register with the ouφut of said first counter and, on a compare, providing a comparison input to said state machine;

providing means responsive to said edge signal and said comparison input for determining die decoded attribute for die data stream segment.

10. The mediod of claim 9 wherein said first maximum count value corresponds to the expected number of clock pulses for adjacent transitions for a logical one in Manchester encoded data widi the tape running at its slowest speed.

11. The method of claim 9 wherein said second maximum count value corresponds to the expected number of clock pulses for adjacent transitions for a logical zero in Manchester encoded data widi die tape running at its slowest speed.

12. Apparatus for decoding a Manchester I encoded data stream from a magnetic tape operating during read at any speed widiin a range of speeds, said decoder comprising:

means for detecting each transition within said data stream;

means for measuring a first interval between a transition and the next successive transition;

means for measuring a second interval between said next transition and a following transition;

means for determining die relation between the measurements of said second interval relative to said first interval;

means for decoding each segment of said data stream based on said relation determining means and said transition detection means for selectively providing a clocked decoded data ouφut

13. The apparatus of claim 12 herein said means for measuring said first and second intervals includes counter means.

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14. The apparatus according to claim 13 wherein said counter means includes first and second counters, said first counter having a first maximum count value and said second counter having a second maximum count value at least twice said first maximum count value whereby the relationship between the timing and values of said first and second counters provides means for distinguishing between logical ones and logical zeroes in said data stream.

15. The apparatus according to claim 14 wherein said apparatus further includes sample clock means and said first and second counters count pulses from said sample clock means for measuring said first and second intervals.

16. The apparatus according to claim 15 wherein said first maximum count is the number of pulses related to a measured interval between transitions for a logical one widi the tape running at its slowest speed.

17. The apparatus according to claim 16 wherein said second maximum count is die number of pulses related to a measured interval between transitions for a logical zero widi die tape running at its slowest speed.

18. The apparatus according to claim 12 further including register means for storing a preselected measured interval.

19. The apparatus according to claim 17 wherein said means for decoding includes state machine means changing states in response to at least said first counter.

20. Apparatus for decoding an encoded data stream from a magnetic tape operating at any speed widiin a range of speeds wherein the encoded data is encoded on the tape at a given number of bits per unit lengtii of tape in a format in which transitions indicative of one logic value occur during one half bit cell intervals and transitions indicative of anodier logic value occur during full bit cell intervals, said apparatus comprising:

sample clock means operating at a predetermined frequency;

means synchronized to said sample clock means for detecting each transition;

first counter means synchronized to said sample clock means and responsive to detection of a transition for commencing counting sample clock pulses until one of die detection of a next transition or a reset signal;

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SUBSTITUTE SHEET second counter means synchronized to said sample clock means and responsive to detection of a transition for commencing counting sample clock pulses until one of die detection of a next transition or counter overflow, said second counter means counting to a value at least twice the maximum of said first counter means;

logic means responsive to said first and second counter means for providing said reset signal to said first counter and for determining the duration and sequence of transitions in said encoded data stream and for providing an ouφut indicative thereof ; and

state machine means synchronized widi said sample clock means and being responsive to said transition detection means and die ouφut of said logic means for providing a clocked decoded ouφut

21. A mediod for decoding a Manchester I encoded data stream recorded on a magnetic tape at a given speed, the decoding occurring widi the tape operating at any speed widiin a range of speeds, said mediod comprising:

providing a sample clock having a predetermined frequency;

providing an edge signal at each transition in said data stream;

from a given edge signal, counting, in a first counter, die number of sample clock pulses between said given signal and die next successive one of said signals;

from said given edge signal, counting in a second counter, die number of sample clock pulses between said given signal and die next successive one of said signals;

providing a state machine having first, second and tiiird inputs, said first input being said sample clock, said second input being said edge signal, said state machine having as a first ouφut a register load signal and, as a second ouφut, a multiplexer select signal;

providing to a multiplexer first and second values, said first value being die count of said second counter and said second value being one half the first value;

providing a register for storing one of said first and second values on concurrence of an edge signal and said register load signal, the value so selected being responsive to said

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SUBSTITUTE SHEET select signal enabling transfer of one of said first and second values through said multiplexer,

first compare means for comparing die ouφut of said register widi die value of die count in said first counter and, on compare, resetting said first counter,

second compare means for comparing one half the value of die ouφut of said register widi the value of die count in said first counter, and, on compare, providing the compare ouφut as said third input to said state machine; and

outputting from said state machine a clocked decoded data stream.

22. Apparatus for decoding an encoded data stream from a magnetic tape operating at any speed widiin a range of speeds wherein the encoded data is encoded on d e tape at a given number of bits per unit length of tape in a format in which transitions indicative of one logic value occur during one half bit cell intervals T and transitions indicative of anodier logic value occur during a full bit cell interval 2T, said apparatus comprising:

sample clock means operating at a predetermined frequency;

means synchronized to said sample clock means for detecting each transition and for providing an edge signal;

state machine means synchronized to said sample clock means and receiving said edge signal for outputting logic conffol signals, clocked decoded data and a plurality of state operations including a state operation for a decode of a logical one and a state operation for a decode of a logical zero,

logic means having ouφuts coupled to said state machine and responsive to said edge signals and to ouφuts of said control signals, said logic means including means for repetitively determining die number of clock pulses occurring between successive edge signals and for distinguishing between half bit cell intervals T and full bit cell intervals 2T; and

means for storing a value of T for a time duration longer tiian 2T for enabling decode, by said state machine, of data sync segments having portions thereof exceeding full bit cell intervals 2T.

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23. The apparatus of claim 22 wherein said logic means includes means for selectively storing one of a value generally equal to the number of clock pulses between transitions of said encoded data stream and a value equal to half the number of clock pulses, and means for comparing and distinguishing between half bit cell intervals and full bit cell intervals and outputting a logical one on die second of two sequential occurrences of half bit cell intervals and outputting a logical zero on one occurrence of a full bit cell interval, said apparatus further including means for reinitiating the sequential count and comparison for any other result of said comparing and distinguishing means.

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