WO1994001845A1 - Arrangement for tuning out interference signals on signals lines - Google Patents

Arrangement for tuning out interference signals on signals lines Download PDF

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Publication number
WO1994001845A1
WO1994001845A1 PCT/DE1993/000547 DE9300547W WO9401845A1 WO 1994001845 A1 WO1994001845 A1 WO 1994001845A1 DE 9300547 W DE9300547 W DE 9300547W WO 9401845 A1 WO9401845 A1 WO 9401845A1
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WO
WIPO (PCT)
Prior art keywords
signal
gate
arrangement
lines
signals
Prior art date
Application number
PCT/DE1993/000547
Other languages
German (de)
French (fr)
Inventor
Stefan Simon
Holger Krebs
Original Assignee
Robert Bosch Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Publication of WO1994001845A1 publication Critical patent/WO1994001845A1/en

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Classifications

    • G—PHYSICS
    • G08—SIGNALLING
    • G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
    • G08C25/00—Arrangements for preventing or correcting errors; Monitoring arrangements

Definitions

  • the invention is based on an arrangement for masking out interference signals on signal lines. It is already known to shield signal lines, for example the signal line from a sensor to the evaluation unit, in order to protect them from interference and thus falsification of the signal. Shielding a sensor cable is relatively expensive, but it does not guarantee that the signal is not falsified.
  • the arrangement according to the invention with the characterizing features of the main claim has the advantage over the fact that a useful signal which is completely free from interference is present in the evaluation unit. There is no need for expensive shielding of the sensor cable. Another advantage is that only one additional wire in the sensor cable is required for signal transmission.
  • FIG. 1 shows a basic circuit diagram for digital signal transmission
  • FIG. 2 shows the signal profiles as they occur at different points in the basic circuit diagram
  • FIG. 3 shows a basic circuit diagram for analog signal transmission.
  • FIG. 1 shows the basic structure of the invention.
  • the circuit diagram shows a sensor unit 1, the sensor itself not being shown.
  • the signal supplied by the sensor is given in the sensor unit 1 to a first signal line 2, which thus transmits the original signal A.
  • this original signal is passed to an inverter 3, so that the inverted signal A is present on a second signal line 4 at the output of the inverter.
  • These two signal lines 2 and 4 can lie, for example, with a ground line 5 in the sensor cable 6, which is only shown schematically. A simple three-core cable without shielding would be necessary.
  • the sensor cable 6 is connected to the signal lines 2 and 4 and the ground line 5 to an evaluation unit 7.
  • the signal lines are each connected to ground on the anode side via a Zener diode 8 and 9, in order to derive overvoltages and to protect the evaluation unit from destruction.
  • the signal line 2 and the signal line 4 are first routed to a first digitizing stage 10 and a second digitizing stage 11 in order to obtain clear levels for further evaluation.
  • the original signal AI is present at the output of the first digitizing stage 10.
  • the digitized inverted signal AI is present after the transmission.
  • This inverted signal AI is now passed to a further inverter 12, where it is inverted one more time, so that the double-inverted signal AI is now present.
  • the transmitted original signal AI and the double-inverted transmitted signal AI are each routed to an input of an AND gate 13, so that the interference-free useful signal A2 is available at the output 14 for evaluation.
  • FIG. 2 shows the individual signal profiles at different points in the basic structure from FIG. 1.
  • the mode of action will now be explained in more detail with reference to FIG. 2.
  • the original signal A and the inverted signal A as is available at the output of the sensor unit 1, are represented by the signal course I.
  • the signal lines 2 and 4 for the transmission of these two signals are influenced approximately equally in the environment to which they are exposed, that is to say, occurring faults S as symbolically shown in FIG. 1 have an effect on the signal profiles on both signal lines 2, 4 approximately the same effect.
  • the disturbances are shown in FIG. 2 in the signal profiles II.
  • These signal profiles are available at both inputs of the evaluation unit 7.
  • these signals are first digitized in the digitizing stages 10 and 11, so that the signal curves III are available at the output of the digitizing stages.
  • the inverted signal is now inverted again in the inverter 12, so that the signal profiles as shown in the signal profile IV are available in front of the AND gate 13. Now the two signal profiles are linked by the AND gate 13 and faults are thus recognized and extinguished.
  • the original signal on the other hand, is confirmed and is thus available for evaluation as interference-free signal A2, as shown in signal curve V.
  • FIG. 3 shows such an arrangement for canceling out interference signals for the transmission and evaluation of analog signals, the same reference numerals being used for the same parts from FIG.
  • the original signal A supplied by a sensor unit is first given for transmission to a signal line 2.
  • the original signal A is passed parallel to the signal line 2 to a differentiator 15, so that a differentiated signal dA is given to the signal line 4 at the output of the differentiator 15.
  • the signal transmission also takes place here in a three-wire sensor cable, so that interference S influences the original signal A and the differentiated signal dA equally.
  • the original signal A is given in the evaluation unit 7 to the first input of an analog AND link 17 and the differentiated signal dA via an integrator 16 to the second input of the analog AND link 17, so that interference signals at the AND Link 17 can be hidden. After the AND link 17, the original signal A is available without interference.

Abstract

The proposal is for an arrangement for tuning out interference signals on signal lines which ensures that an interference-free original signal is available for exploitation. The arrangement comprises the transmission of an original signal (A) in a first signal line (2) and of an inverted or differentiated original signal (A or dA) in a second signal line (4). Here, the previously inverted or differentiated signal is to be inverted or integrated again and then both signals are to be concatenated in an AND gate (13) so that the interference-free original signal A is available at the output of the AND gate.

Description

Anordnung zum Ausblenden von Störsignalen auf SignalleitungenArrangement for masking out interference signals on signal lines
Stand der TechnikState of the art
Die Erfindung geht aus von einer Anordnung zum Ausblenden von Stör¬ signalen auf Signalleitungen. Es ist bereits bekannt, Signalleitun¬ gen beispielsweise die Signalleitung von einem Sensor zur Auswerte¬ einheit zu schirmen, um sie so vor Störungen und damit Verfälschung des Signals zu schützen. Die Schirmung eines Sensor-Kabels ist rela¬ tiv kostenaufwendig, aber keine Garantie dafür, daß das Signal nicht verfälscht wird.The invention is based on an arrangement for masking out interference signals on signal lines. It is already known to shield signal lines, for example the signal line from a sensor to the evaluation unit, in order to protect them from interference and thus falsification of the signal. Shielding a sensor cable is relatively expensive, but it does not guarantee that the signal is not falsified.
Vorteile der ErfindungAdvantages of the invention
Die erfindungsgemäße Anordnung mit den kennzeichnenden Merkmalen des Hauptanspruchs hat demgegenüber den Vorteil, daß ein völlig von Stö¬ rungen befreites Nutzsignal in der Auswerteeinheit vorliegt. Eine teure Schirmung des Sensor-Kabels kann vollständig entfallen. Als weiterer Vorteil ist anzusehen, daß lediglich eine weitere Ader in dem Sensor-Kabel zur Signalübertragung erforderlich ist. The arrangement according to the invention with the characterizing features of the main claim has the advantage over the fact that a useful signal which is completely free from interference is present in the evaluation unit. There is no need for expensive shielding of the sensor cable. Another advantage is that only one additional wire in the sensor cable is required for signal transmission.
Durch die in den Unteransprüchen aufgeführten Maßnahmen sind vor¬ teilhafte Weiterbildungen und Verbesserungen der in den nebengeord¬ neten Ansprüchen angegebenen Anordnung möglich. Besonders vorteil¬ haft ist, daß am Ausgang des UND-Gatters Störungen vollkommen aus¬ gelöscht sind, und das Nutzsignal bestätigt als störungsfreies Signal zur Auswertung zur Verfügung steht. Letztendlich sei erwähnt, daß die Verwendung von Z-Dioden in beiden Signalleitungen gegen Mas¬ se die Auswerteeinheit vor Überspannungen und damit vor Zerstörung schützt.The measures listed in the subclaims allow advantageous developments and improvements of the arrangement specified in the secondary claims. It is particularly advantageous that interference is completely canceled at the output of the AND gate, and the useful signal confirmed is available as an interference-free signal for evaluation. Finally, it should be mentioned that the use of Z diodes in both signal lines against ground protects the evaluation unit against overvoltages and thus against destruction.
Zeichnungdrawing
Ausführungsbeispiele der Erfindung sind in der Zeichnung dargestellt und in der nachfolgenden Beschreibung näher erläutert. Es zeigen Figur 1 ein Prinzipschaltbild für digitale Signalübertragung, Figur 2 die Signalverläufe, wie sie im Prinzipschaltbild an verschiedenen Punkten auftreten und Figur 3 ein Prinzipschaltbild für analoge Signalübertragung.Embodiments of the invention are shown in the drawing and explained in more detail in the following description. FIG. 1 shows a basic circuit diagram for digital signal transmission, FIG. 2 shows the signal profiles as they occur at different points in the basic circuit diagram, and FIG. 3 shows a basic circuit diagram for analog signal transmission.
Beschreibung der AusführungsbeispieleDescription of the embodiments
Figur 1 zeigt den Prinzipaufbau der Erfindung. Die Schaltskizze zeigt eine Sensoreinheit 1, wobei der Sensor an sich nicht dargestellt ist. Das vom Sensor gelieferte Signal wird in der Sen¬ soreinheit 1 auf eine erste Signalleitung 2, die somit das Original¬ signal A überträgt, gegeben. Gleichzeitig wird dieses Originalsignal auf einen Invertierer 3 gegeben, so daß am Ausgang des Invertierers das invertierte Signal A an einer zweiten Signalleitung 4 anliegt. Diese beiden Signalleitungen 2 und 4 können beispielsweise mit einer Masseleitung 5 in dem nur schematisch dargestellten Sensor-Kabel 6 liegen. Es wäre somit ein einfaches dreiadriges Kabel ohne Schirmung notwendig. Das Sensorkabel 6 ist mit den Signalleitungen 2 und 4 sowie der Masseleitung 5 an eine Auswerteeinheit 7 geführt. In der Auswerteeinheit 7 sind die Signalleitungen jeweils über eine Zener- diode 8 und 9 anodenseitig gegen Masse geschaltet, um so Überspan¬ nungen abzuleiten und die Auswerteeinheit vor Zerstörung zu schüt¬ zen. Die Signalleitung 2 und die Signalleitung 4 sind nun zunächst auf eine erste Digitalisierstufe 10 bzw. eine zweite Digitalisier¬ stufe 11 geführt, um für die weitere Auswertung eindeutige Pegel zu erhalten. Am Ausgang der ersten Digitalisierstufe 10 liegt das Ori¬ ginalsignal AI vor. Und am Ausgang der zweiten Digitalisierstufe 11 liegt nach der Übertragung das digitalisierte invertierte Signal AI vor. Dieses invertierte Signal AI wird nun auf einen weiteren Inver¬ tierer 12 geführt, wo es ein weiteres Mal invertiert wird, so daß nun das doppelt invertierte Signal AI vorliegt. Das übertragene Originalsignal AI und das doppelt invertierte übertragene Signal AI wird nun jeweils auf einen Eingang eines UND-Gatters 13 geführt, so daß am Ausgang 14 das störungsfreie Nutzsignal A2 für die Auswertung zur Verfügung steht.Figure 1 shows the basic structure of the invention. The circuit diagram shows a sensor unit 1, the sensor itself not being shown. The signal supplied by the sensor is given in the sensor unit 1 to a first signal line 2, which thus transmits the original signal A. At the same time, this original signal is passed to an inverter 3, so that the inverted signal A is present on a second signal line 4 at the output of the inverter. These two signal lines 2 and 4 can lie, for example, with a ground line 5 in the sensor cable 6, which is only shown schematically. A simple three-core cable without shielding would be necessary. The sensor cable 6 is connected to the signal lines 2 and 4 and the ground line 5 to an evaluation unit 7. In the evaluation unit 7, the signal lines are each connected to ground on the anode side via a Zener diode 8 and 9, in order to derive overvoltages and to protect the evaluation unit from destruction. The signal line 2 and the signal line 4 are first routed to a first digitizing stage 10 and a second digitizing stage 11 in order to obtain clear levels for further evaluation. The original signal AI is present at the output of the first digitizing stage 10. And at the output of the second digitizing stage 11, the digitized inverted signal AI is present after the transmission. This inverted signal AI is now passed to a further inverter 12, where it is inverted one more time, so that the double-inverted signal AI is now present. The transmitted original signal AI and the double-inverted transmitted signal AI are each routed to an input of an AND gate 13, so that the interference-free useful signal A2 is available at the output 14 for evaluation.
In Figur 2 sind die einzelnen Signalverläufe an verschiedenen Punk¬ ten des Prinzipaufbaus aus Figur 1 dargestellt. Die Wirkungsweise soll nun anhand der Figur 2 näher erläutert werden. In Figur 2 ist durch Signalverlauf I das Originalsignal A und das invertierte Signal A, wie es am Ausgang der Sensoreinheit 1 zur Verfügung steht, dargestellt. Die Signalleitungen 2 und 4 zur Übertragung dieser bei¬ den Signale werden in dem Umfeld, dem sie ausgesetzt sind, annähernd gleich beeinflußt, das heißt, auftretende Störungen S wie sie in Figur 1 symbolisch dargestellt sind, haben auf die Signalverläufe auf beiden Signalleitungen 2, 4 annähernd gleiche Wirkung. Die Stö¬ rungen sind in Figur 2 in den Signalverläufen II dargestellt. Diese Signalverläufe stehen an beiden Eingängen der Auswerteeinheit 7 zur Verfügung. In der Auswerteeinheit werden diese Signale zunächst in den Digitalisierstufen 10 und 11 digitalisiert, so daß am Ausgang der Digitalisierstufen die Signalverläufe III zur Verfügung stehen. Das invertierte Signal wird nun in dem Invertierer 12 nochmals in¬ vertiert, so daß vor dem UND-Gatter 13 die Signalverläufe, wie sie im Signalverlauf IV dargestellt sind, zur Verfügung stehen. Nun wer¬ den beide Signalverläufe durch das UND-Gatter 13 verknüpft und so Störungen erkannt und ausgelöscht. Das Originalsignal hingegen wird bestätigt und steht somit als störungsfreies Signal A2 zur Auswer¬ tung bereit, wie in Signalverlauf V dargestellt.FIG. 2 shows the individual signal profiles at different points in the basic structure from FIG. 1. The mode of action will now be explained in more detail with reference to FIG. 2. In FIG. 2, the original signal A and the inverted signal A, as is available at the output of the sensor unit 1, are represented by the signal course I. The signal lines 2 and 4 for the transmission of these two signals are influenced approximately equally in the environment to which they are exposed, that is to say, occurring faults S as symbolically shown in FIG. 1 have an effect on the signal profiles on both signal lines 2, 4 approximately the same effect. The disturbances are shown in FIG. 2 in the signal profiles II. These signal profiles are available at both inputs of the evaluation unit 7. In the evaluation unit, these signals are first digitized in the digitizing stages 10 and 11, so that the signal curves III are available at the output of the digitizing stages. The inverted signal is now inverted again in the inverter 12, so that the signal profiles as shown in the signal profile IV are available in front of the AND gate 13. Now the two signal profiles are linked by the AND gate 13 and faults are thus recognized and extinguished. The original signal, on the other hand, is confirmed and is thus available for evaluation as interference-free signal A2, as shown in signal curve V.
Somit ist auf einfache Art und Weise gesichert, daß das vom Sensor erfaßte Signal der Auswerteeinheit störungsfrei zur Weiterverarbei¬ tung zur Verfügung steht.This ensures in a simple manner that the signal detected by the sensor is available to the evaluation unit for further processing without interference.
Figur 3 zeigt eine solche Anordnung zum Auslöschen von Störsignalen für die Übertragung und Auswertung analoger Signale, wobei für glei¬ che Teile aus Figur 1 gleiche Bezugszeichen verwendet werden. Hierzu wird das von einer Sensoreinheit gelieferte Originalsignal A zu¬ nächst zur Übertragung auf eine Signalleitung 2 gegeben.FIG. 3 shows such an arrangement for canceling out interference signals for the transmission and evaluation of analog signals, the same reference numerals being used for the same parts from FIG. For this purpose, the original signal A supplied by a sensor unit is first given for transmission to a signal line 2.
Gleichzeitig wird das Originalsignal A parallel zur Signalleitung 2 auf einen Differenzierer 15 gegeben, so daß am Ausgang des Differen¬ zierers 15 ein differenziertes Signal dA auf die Signalleitung 4 gegeben wird. Analog zu Figur 1 erfolgt die Signalübertragung auch hier in einem dreiadrigem Sensorkabel, so daß Störungen S das Ori¬ ginalsignal A und das differenziert' Signal dA gleichermaßen beein¬ flussen. Nach der Übertragung wird in der Auswerteeinheit 7 das Ori¬ ginalsignal A auf den ersten Eingang einer analogen UND-Verknüpfung 17 gegeben und das differenzierte Signal dA über einen Integrierer 16 auf den zweiten Eingang der analogen UND-Verknüpfung 17, so daß Störsignale an der UND-Verknüpfung 17 ausgeblendet werden. Nach der Und-Verknüpfung 17 steht das Originalsignal A ohne Störungen zur Verfügung. At the same time, the original signal A is passed parallel to the signal line 2 to a differentiator 15, so that a differentiated signal dA is given to the signal line 4 at the output of the differentiator 15. Analogously to FIG. 1, the signal transmission also takes place here in a three-wire sensor cable, so that interference S influences the original signal A and the differentiated signal dA equally. After the transmission, the original signal A is given in the evaluation unit 7 to the first input of an analog AND link 17 and the differentiated signal dA via an integrator 16 to the second input of the analog AND link 17, so that interference signals at the AND Link 17 can be hidden. After the AND link 17, the original signal A is available without interference.

Claims

Ansprüche Expectations
1. Anordnung zum Ausblenden von Störsignalen auf Signalleitungen, dadurch gekennzeichnet, daß eine erste Signalleitung (2) ein digita¬ les Originalsignal (A) und eine zweite Signalleitung (4) ein dazu invertiertes Signal (A) überträgt und daß die beiden Signalleitungen (2, 4) an ihrem Ende an einem ersten und einem zweiten Eingang eines UND-Gatters (13) anliegen, wobei das invertierte Signal (A) über einen dem UND-Gattereingang vorgeschalteten Invertierer (12) am Ein¬ gang des UND-Gatters (13) anliegt und daß am Ausgang des UND-Gatters (13) das störungsfreie Originalsignal (A) abgreifbar ist.1. Arrangement for masking out interference signals on signal lines, characterized in that a first signal line (2) transmits a digital original signal (A) and a second signal line (4) transmits an inverted signal (A) and that the two signal lines (2 , 4) are applied at their end to a first and a second input of an AND gate (13), the inverted signal (A) being connected via an inverter (12) upstream of the AND gate input at the input of the AND gate (13 ) is present and that the interference-free original signal (A) can be tapped at the output of the AND gate (13).
2. Anordnung zum Ausblenden von Störsignalen auf Signalleitungen, dadurch gekennzeichnet, daß eine erste Signalleitung (2) ein analo¬ ges Originalsignal (A) und eine zweite Signalleitung (4) ein dazu differenziertes Signal (dA) überträgt und daß am Ende der Signal¬ leitungen das Originalsignal an einem Eingang eine analoge UND-Ver¬ knüpfung (17) und daß das differenzierte Signal (dA) über ein Inte¬ grierglied (16) am anderen Eingang der analogen UND-Verknüpfung (17) anliegt.2. Arrangement for masking out interference signals on signal lines, characterized in that a first signal line (2) transmits an analog original signal (A) and a second signal line (4) transmits a differentiated signal (dA) and that at the end of the signal lines the original signal at one input an analog AND link (17) and that the differentiated signal (dA) is present via an integrating element (16) at the other input of the analog AND link (17).
3. Anordnung nach Anspruch 1 und 2, dadurch gekennzeichnet, daß das von einem Signalgeber gelieferte Originalsignal (A) an einer ersten Signalleitung (2) und über einen Invertierer (3) bzw. Differenzierer (15) an einer zweiten Signalleitung (4) anliegt. 3. Arrangement according to claim 1 and 2, characterized in that the original signal supplied by a signal generator (A) on a first signal line (2) and via an inverter (3) or differentiator (15) on a second signal line (4) .
4. Anordnung nach Anspruch 1, dadurch gekennzeichnet, daß den beiden Eingängen des UND-Gatters (13) Digitalisierstufen (10, 11) vorge¬ schaltet sind.4. Arrangement according to claim 1, characterized in that the two inputs of the AND gate (13) digitizing stages (10, 11) are precontrolled.
5. Anordnung nach Anspruch 1 bis 4, dadurch gekennzeichnet, daß bei¬ de Signalleitungen (2, 4) in einem Sensorkabel (6) zwischen einer Sensoreinheit (1) und einer Auswerteeinheit (7) angeordnet sind.5. Arrangement according to claim 1 to 4, characterized in that both signal lines (2, 4) in a sensor cable (6) are arranged between a sensor unit (1) and an evaluation unit (7).
6. Anordnung nach Anspruch 1 bis 5, dadurch gekennzeichnet, daß neben den beiden Signalleitungen (2, 4) im Sensorkabel (6) noch eine dritte Leitung (5) gegen Masse geschaltet ist.6. Arrangement according to claim 1 to 5, characterized in that in addition to the two signal lines (2, 4) in the sensor cable (6), a third line (5) is connected to ground.
7. Anordnung nach Anspruch 1 bis 6, dadurch gekennzeichnet, daß die beiden Signalleitungen (2, 4) in der Auswerteeinheit (7) über je eine Zenerdiode (8, 9) gegen Masse geschaltet sind. 7. Arrangement according to claim 1 to 6, characterized in that the two signal lines (2, 4) in the evaluation unit (7) are each connected to ground via a Zener diode (8, 9).
PCT/DE1993/000547 1992-07-09 1993-06-24 Arrangement for tuning out interference signals on signals lines WO1994001845A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19924222475 DE4222475A1 (en) 1992-07-09 1992-07-09 Arrangement for masking out interference signals on signal lines
DEP4222475.6 1992-07-09

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Cited By (1)

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WO2014166690A1 (en) * 2013-04-11 2014-10-16 Robert Bosch Gmbh Method for operating a common rail system of a motor vehicle having a redundant rail pressure sensor

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Publication number Priority date Publication date Assignee Title
DE4435783A1 (en) * 1994-10-06 1996-04-11 Siemens Ag Interface circuit for voltage-isolated signal transfer within electrical equipment
DE19508303A1 (en) * 1995-03-09 1996-09-12 Bayerische Motoren Werke Ag Signal transmitter e.g. for car control and/or diagnostics appts.
DE19611503C1 (en) * 1996-03-23 1997-05-07 Bosch Gmbh Robert Device for transferring signals generated by passive sensors
DE19654329A1 (en) * 1996-12-24 1998-06-25 Bosch Gmbh Robert Circuit arrangement for the interference-free evaluation of signals
DE19962233B4 (en) * 1999-12-22 2006-02-02 Siemens Ag Telecommunication device with non-inverted and inverted signal distribution

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US3906384A (en) * 1973-02-12 1975-09-16 Cambridge Res & Dev Group System for nullifying signal processor distortions

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FR2010482A1 (en) * 1968-05-25 1970-02-20 Philips Nv
US3748497A (en) * 1971-09-03 1973-07-24 Westinghouse Electric Corp Transfer gate
US3906384A (en) * 1973-02-12 1975-09-16 Cambridge Res & Dev Group System for nullifying signal processor distortions

Cited By (2)

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Publication number Priority date Publication date Assignee Title
WO2014166690A1 (en) * 2013-04-11 2014-10-16 Robert Bosch Gmbh Method for operating a common rail system of a motor vehicle having a redundant rail pressure sensor
US9863358B2 (en) 2013-04-11 2018-01-09 Robert Bosch Gmbh Method for operating a common-rail system of a motor vehicle having a redundant common-rail-pressure sensor

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