WO1993020678A1

WO1993020678A1 - Spacer tray

Info

Publication number: WO1993020678A1
Application number: PCT/US1993/002663
Authority: WO
Inventors: Karla Y. Carichner; John V. Bugarin
Original assignee: Vlsi Technology, Inc.
Priority date: 1992-03-31
Filing date: 1993-03-16
Publication date: 1993-10-14
Also published as: KR950701187A

Abstract

A spacer tray is disclosed. This spacer tray finds use in handling or shipping semiconductor packages having surface projections which extend the height of the semiconductor package beyond normal semiconductor height parameters. The spacer tray is generally used in conjunction with a standard carrier tray which holds the semiconductor base (i.e., the semiconductor body and leads). The spacer tray comprises a tray body having at least one bore, the bore being sized to house the semiconductor surface projection(s) while excluding the semiconductor base. Methods of use are also given.

Description

SPACER TRAY Technical Field

This invention relates to shipping devices for handling and shipping packaged semiconductor chip devices.

Background of the Invention

Semiconductor chips are produced and packaged in a variety of ways. A variety of chip carrier devices, for handling or shipping a number of packaged semiconductor chips, are commercially available.

In one chip carrier device, shown in Figure la, a molded stackable tray 10 provides a patterned group of wells 12 for semiconductor devices 14. As shown in cross-section in Figure lb, each well 12 includes a tray wall 16 portion and a tray base 18 portion. A semiconductor device 14 is placed within a well 12 for transport. When no semiconductor devices 14 are present, the trays 10 nest into one another for storage (not shown). When standard, low-profile, semiconductor device 14 are present, the trays 10 provide tongue-and-groove integration to maintain a stack of trays 10 as a carryable unit (as shown in Figure lb). If desired, an empty tray 10 can be used as a lid to enclose the semiconductor devices 14, as shown in Figure lb. Carrier trays such as that shown are generally vacuum molded, and have limited mechanical strength.

An alternate chip carrier device is shown in Figure 2. In this device, a semiconductor device (not shown) is inserted into a closable protector case 20. The case 20 is designed to enclose one or more semiconductor devices. However, the semiconductor device must be within specified height parameters to fit within a closed protector case 20.

In yet another chip carrier device, as shown in Figure 3a, a tubular carrier 22 is used to transport a multiplicity of semiconductor devices. One or both ends of the carrier 22 can be sealed using a cap 24. In one embodiment, one end of the carrier 22 is closed, and the opposite end of the carrier can be sealed using a removable cap 24. The cross-sectional shape of the tubular carrier 22 can be adapted to conform to a specific semiconductor device cross-section. Figures 3b and 3c show cross- sectional views of semiconductor devices held within a tubular carrier such as that shown in Figure 3a. As shown in Figure 3b, a tubular carrier is adapted to store a multiplicity of semiconductor devices 14 including a multiplicity of leads 24. A window means 25 can be present to permit inspection of the enclosed semiconductor packages. Figure 3c shows the cross-section of a tubular carrier 22 which stores semiconductor devices 14 including a multiplicity of leads 24 and including a heat sink 26. A window means 25 is preferably present. Tubular carriers such as these can subject the semiconductor devices to chipping or other damage if the semiconductor devices laterally impact each other during shipping or transport.

Each of the above shipping methods and devices is limited in regards to the dimensions of the semiconductor packages it can handle. More specifically, each carrier can handle only packaged semiconductors having dimensions which conform specifically to the tray dimensions. Semiconductor devices having additional structures (such as one or more heat sink, capacitor, or the like) which is mounted above the semiconductor package body and increases the height of the semiconductor package beyond normal package parameters are not amenable to transport using standard semiconductor carriers.

A standard semiconductor chip package 100 is shown in Figure 4a and 4b. A multiplicity of electrical leads 101 extend outward and then downward from a generally flat, square or rectangular rigid body portion 103. The body portion 103 is a housing which encloses a semiconductor die and appropriate electrical connections (not shown). Other electrical or electronic units, insulators, conductors, capacitors, resistors, and the like (not shown) can also be present within the body portion 103. While the pictured package is generally representative of such semiconductor packages, a wide diversity of similar packages are known to the art.

Semiconductor packages 100 such as those shown in Figure 4 have been in use for many years. However, as semiconductor dies have been reduced in size and increased in complexity, it has been beneficial to include additional structures such as heat sinks to dissipate the heat generated by the function of a semiconductor device in its ultimate environment of use. The package 100 shown in Figures 5a and 5b includes a heat sink 105 and four capacitors 107 extending from the upper surface of the body portion 103.

Standardized carrier trays 110 for semiconductor packages 100 are available from a variety of sources. Such carrier trays often meet JEDEC (Joint Electronic Device Engineering Counsel) standards or registered outHnes of the Electronic Industries Association (EIA) regarding internal and/or external size and shape parameters. One example is a pin grid array (PGA) tray 110, shown in top view in Figure 6. Ten wells 109 are each dimensioned to enclose one semiconductor package. Such trays are available commercially from a variety of sources, including R.H. Murphy Co., Inc. (Amherst, NH).

Figures 7a through 7c show cross-sectional views through one well 109 of a chip carrier tray 110, such as that taken through line 7-7 of Figure 6.

Figure 7a shows a single well 109 having side walls 111 and 113 and abase 115. The outer side wall 111 includes a notch 117 on its upper edge and a boss 119 on its lower edge. The notch 117 and boss 119 integrate when trays are stacked to provide a stable structure. One or more squared notch (not shown) can be present on the bottom edge of the tray to provide a grip for a strapping tape. If desired, a curved groove can be present to allow the use of a pin to mechanically bias the tray orientation. The presence and size of such notches and grooves are well known to the art, and are preferably present in conformity with JEDEC standards.

Figure 7b, shows an alternate embodiment of a standard well 109 in a PGA chip carrier tray. The base includes raised areas 121 extending from the base 115 of the well 109, which act to engage the outermost edges of the electrical leads 101, and thus hold the semiconductor package 100 free from lateral movement within the well. The body 103 of a semiconductor package, having a standard height, is held within the interior of a standard well 109.

Figure 7c shows a semiconductor package which includes surface attachments 123 (such as the heat sink 105 and capacitors 107 of Figure 5) which project upwards from the semiconductor body 103. While the body 103 and leads of the semiconductor package are held within, and protected by, a standard tray well 109, the attachments 123 protruding from the surface of the package body extend above the protecting walls of the well 109. The attachments 123 are not protected by the well 109, and may be damaged during transport.

Summary nf the Invention

A spacer tray is disclosed. This spacer tray finds use in handling or shipping semiconductor packages having surface structures, such as one or more heat sink, capacitor, or the like, which project from the normal surface of the semiconductor package. These surface structures extend the height of the semiconductor package beyond normal semiconductor height parameters.

The spacer tray of this invention is generally used in conjunction with a standard tray which holds the semiconductor base (i.e., the body and leads). The spacer tray comprises a tray body having at least one bore. The bore is sized to contain the semiconductor surface projection(s), while excluding the semiconductor base. A unit for holding semiconductors includes a holder tray and one or more spacer trays. A holder tray generally has at least one well into which the base of a semiconductor package can be inserted. A corresponding spacer tray has at least one bore corresponding in placement to the well of the holder tray. The bore is sized to contain extensions projecting fro the base of the semiconductor package, while excluding the semiconductor body and leads.

Because it is generally advantageous to produce semiconductor packages having a relatively low profile, one spacer tray which conforms to standardized height parameters for semiconductor tray holding devices will enclose most semiconductor packages. However, should a semiconductor package include surface extensions which exceed one standard tray height, a plurality of stacked spacer trays can be used to provide protection for the semiconductor package.

A method for protecting a semiconductor device using the spacer tray herein is shown. Such a method comprises positioning the base (body and leads) of a semiconductor package having at least one surface projection into a well of a lower holding tray; and positioning over the semiconductor package an upper protecting tray. The upper protecting tray includes a bore sized to house the projection while excluding the semiconductor base.

Brief Description of the Drawings

Figure 1 shows a molded stackable carrier tray of the prior art. Figure la is a top view, and Figure lb is a cross-sectional view. Figure 2 shows a prior art closable carrier for semiconductor devices.

Figure 3a shows a tubular carrier of the prior art. Figure 3b and

3c show cross-sectional views of alternate tubular carrier devices, adapted for use with semiconductor devices having different cross-sectional profiles.

Figure 4 shows a standard packaged semiconductor chip: Figure 4a is a side view, and Figure 4b is a top view.

Figure 5 shows a packaged semiconductor chip which includes several protruding structures which extend from the surface of the semiconductor package body. Figure 5a is a side view, and Figure 5b is a top view.

Figure 6 shows a top view of a standard semiconductor chip carrier tray.

Figure 7a shows a cross-sectional view of a well of a semiconductor chip carrier tray taken through line 7-7 of Figure 6. Figure 7b shows an alternate embodiment of a well of a semiconductor chip carrier tray which includes an enclosed alternate standard packaged semiconductor device. Figure 7c shows a well of a semiconductor chip carrier tray with a packaged semiconductor device which includes surface attachments.

Figure 8a shows a top view of a spacer tray of this invention. Figure 8b shows a cross-sectional view of a spacer tray of this invention, taken through line 8b-8b of Figure 8a. Figure 8c shows a carrier tray well with a packaged semiconductor device which includes surface attachments (such as that shown in Figure 7c) wherein the semiconductor device is protected by a carrier tray of this invention.

Figure 9a shows a top view of an alternate spacer tray of this invention. Figure 9b shows a cross-sectional view of an alternate spacer tray of this invention.

Figure 10b shows a top view of an alternate spacer tray of this invention. Figure 10b shows a cross-sectional view of an alternate spacer tray of this invention.

Disclosure of the Invention Including Best Mode

A spacer tray of this invention is used for storage of one or more semiconductor device including a semiconductor base and at least one projection extending above the base. The spacer tray comprises a tray body having at least one bore therethrough. Generally, multiple bores are present. The bore or bores are sized to house the portion of the semiconductor package which protrudes above the semiconductor base, while excluding the semiconductor base.

The spacer tray herein is generally used in conjunction with a standard carrier tray. A carrier tray includes at least one well, and generally includes a multiplicity of wells. A spacer tray which is used with a carrier tray conforms closely to the layout of the carrier tray. Each well of a carrier tray includes a corresponding cell of the spacer tray. The well of the carrier tray is dimensioned to enclose a semiconductor device body and leads. The cell of the spacer tray is dimensioned to enclose projections which extend above the semiconductor device body, while excluding the semiconductor device body and leads.

By excluding the semiconductor body and leads, the spacer tray cell acts to hold the semiconductor device body in place within the carrier tray well. The integration of a carrier tray and one or more spacer trays provides a unit which can be conveniently transported or shipped. Shipping sleeves, strapping, or other such devices well known to the art can be used to ensure that the trays remain integrated during handling or shipping.

The Figures are drawn for clarity and are not drawn to scale. Similar numbers refer to similar structures throughout the Figures.

Figure 8a shows a top view of a preferred spacer tray 125 of this invention. The tray 125 includes a multiplicity of cells 127. A cell 127 is a bore which is adapted to enclose projections which extend above a semiconductor device body, while excluding the semiconductor device body and leads. A cell 127 corresponds in placement and dimension to a well of a carrier tray (not shown). The number of cells is not critical.

In the spacer tray of Figure 8a, each cell 127 includes a four tongue members 129 which extend from the four walls of the cell 127. Preferably, each tongue member 129 is supported by a brace 131 to provide strength to the tongue member 129 during the stresses of shipping or handling. If desired, a corner brace 133 can be present to provide structural rigidity and/or to provide a "pin one" orientation marker to confirm the orientation of the enclosed semiconductor device (not shown) within the cell 127.

In a preferred embodiment, one or more ridge 135 is present at an outer surface of the tray 125 to provide enhanced impact resistance for the spacer tray 125 and to provide enhanced protection for enclosed semiconductor devices during handling or shipping.

The spacer tray 125 is made of any appropriate material having sufficient mechanical strength to withstand normal shipping and handling, while providing protection to the enclosed semiconductor devices. The spacer tray is preferably made of an injection molded plastic, and more preferably meets or exceeds JEDEC standards. An anti-static coating can be present if desired.

Figure 8b shows a cross-sectional view of a preferred spacer tray 125 of this invention, taken through line 8b-8b of Figure 8a. Two cells 127 are shown. Tongue members 129 and their supporting braces 131 are visible in side and end views.

figure 8c shows a cross-sectional view of a spacer tray cell 127 of this invention, in place above a semiconductor carrier well 109. A semiconductor device including a multiplicity of attachments 123 protruding from the surface of the package extend above the protecting walls of the well 109, and are surrounded by the protecting walls of the spacer tray cell 127. The semiconductor device attachments 123 are protected by the combination of the carrier tray well 109 and the spacer tray cell 127. -1-H Figure 9a shows a top view of an alternate embodiment of a spacer tray 125 of this invention. The tray 125 includes two cells 127. Each cell 127 includes a single tongue member 129 which extends from one of the walls of the cell 127. A semiconductor device 100 is shown enclosed within one of the cells.

Figure 9b shows a cross-sectional view of the spacer tray 125 of Figure 9a, taken through line 9b-9b of Figure 9a. A supporting carrier 110 is also shown in the cross-sectional view. A semiconductor device 100 is shown enclosed within one of the wells of the carrier tray and one of the corresponding cells of the spacer tray.

The pictured spacer tray 125 includes a two cells 127. Each cell 127 includes a single tongue member 129 which extends from one of the walls of the cell 127 to partially obscure the mouth of the cell. This tongue acts to exclude the body and leads of the semiconductor device 100, and to hold the semiconductor device in position within the integrated structure of the carrier tray and spacer tray.

Figure 10a shows a top view of an alternate embodiment of a spacer tray 125 of this invention. The tray 125 includes two cells 127. Each cell 127 is round, and is sized to enclose a surface heat sink while excluding the semiconductor device body and leads. A semiconductor device 100 is shown enclosed within one of the cells.

Figure 10b shows a cross-sectional view of the spacer tray 125 of Figure 10a, taken through line lOb-lOb. The tray 125 includes two cells 127. Each cell 127 is dimensioned to exclude the body and leads of the semiconductor device, and to hold the semiconductor device 100 in position within the integrated structure of the carrier tray and spacer tray.

The apparatus shown above can be used in a method for protecting a semiconductor device. Such a method comprises: (a) positioning the base of a semiconductor device into a well of a carrier tray; and (b) positioning over the semiconductor device a spacer tray, said spacer tray. As discussed above, the spacer tray includes a cell or bore sized to house the projection while excluding the semiconductor base.

While the invention has been described in connection with several exemplary embodiments, it will be understood that many modifications will be apparent to those of ordinary skill in the art in light of the above disclosure. Such modifications may include using substitute materials, smaller or greater dimensions, varying the number and placement of spacer tray cells, protecting different types of encapsulated integrated circuit devices, using a variety of different shapes for conductors, insulators and so forth, to achieve substantially the same results in substantially the same way. Reference to the following claims should be made to determine the scope of the claimed invention.

Claims

Clfti gWe Claim:

1. A spacer tray for use with a semiconductor device, said semiconductor device including a semiconductor base, and at least one projection extending above the base; said spacer tray comprising a tray body having at least one bore therethrough, said bore being sized to house the semiconductor projection while excluding the semiconductor base.

2. A spacer tray of Claim 1 wherein the spacer tray body further comprises a multiplicity of bores therethrough.

3. A spacer tray of Claim 1 wherein the tray body is made of a plastic material.

4. A spacer tray of Claim 1 wherein the tray body is made by injection molding.

5. A spacer tray of Glaim 4 wherein the tray includes an outer configuration, and the outer configuration conforms to JEDEC standards.

6. A spacer tray of Claim 5 wherein the spacer tray further comprises an anti-static coating.

7. A spacer tray of Claim 1 wherein the spacer tray further comprises a shelf member which extends from the tray body to partially obscure the bore, said shelf acting to exclude the semiconductor base.

8. A spacer tray of Claim 7 wherein the spacer tray further comprises a shelf brace member extending between the tray body and the shelf member.

9. A multiple tray apparatus for holding a semiconductor package, said apparatus comprising:

(a) a carrier tray including at least one well into which a semiconductor base can be inserted; and

(b) a spacer tray comprising at least one bore corresponding in placement to the well of the carrier tray, said bore being sized to contain an extension projecting from the semiconductor base while excluding the semiconductor base; wherein the carrier tray and spacer tray integrate to form a unit to substantially enclose the semiconductor package.

10. A multiple tray apparatus of Claim 9 wherein the carrier tray further comprises a multiplicity of wells; and the spacer tray further comprises a multiplicity of bores therethrough, wherein each well of the carrier tray corresponds to a bore of the spacer tray, and where in the units integrate to form a carrier for a multiplicity of semiconductor devices.

11. A multiple tray apparatus of Claim 9 wherein the spacer tray body is comprised of a plastic material.

12. A multiple tray apparatus of Claim 9 wherein the spacer tray further comprises a shelf member which extends from the tray body to partially obscure the bore, said shelf acting to exclude the semiconductor base.

13. A multiple tray apparatus of Claim 12 wherein the spacer tray further comprises a shelf brace member extending between the tray body and the shelf member.

14. A method for protecting a semiconductor device, said semiconductor device including a semiconductor base and at least one projection extending upward from the semiconductor base; said method comprising:

(a) positioning the base of a semiconductor device into a well of a carrier tray; and

(b) positioning over the semiconductor device a spacer tray, said spacer tray including a bore sized to house the projection while excluding the semiconductor base.

15. A method of Claim 14 wherein the spacer tray- urther comprises a multiplicity of bores therethrough.

16. A method of Claim 14 wherein the spacer tray body is comprised of a plastic material.

17. A method of Claim 14 wherein the spacer tray further comprises a shelf member which extends from the tray body to partially obscure the bore, said shelf acting to exclude the semiconductor base.

18. A method of Claim 14 wherein the spacer tray further comprises a shelf brace member extending between the tray body and the shelf member.