WO1993020519A1

WO1993020519A1 - Future bus bus termination network

Info

Publication number: WO1993020519A1
Application number: PCT/GB1993/000486
Authority: WO
Inventors: William Ramsay
Original assignee: Cts Corporation Uk Ltd.
Priority date: 1992-03-31
Filing date: 1993-03-09
Publication date: 1993-10-14
Also published as: GB9206949D0

Abstract

A bus termination network as described for terminating transmission lines used with high speed digital backplanes and which meets futurebus+ specifications. The network consists of a plurality of resistors (R) each of which is connected between a hole (15), which receives a connector, and a common junction (22) which is connected to a 2.1 voltage supply at connector (26). The junction (22) is connected to ground (24) via a capacitor (20). The resistor network is provided in a surface mount chip (18) provided with gull-wing connectors. Each transmission line is connected through a single resistor R in network package (18) so that the signal on the transmission line is decoupled from a 2.1 voltage supply and capacitor (20) decouples the resistors (R) from ground (24).

Description

FUTURE BUS BUS TERMINATION NETWORK

The present invention relates to high speed digital back planes which are used for computing and digital signal routing. In particular, the invention relates to apparatus for terminating transmission lines used with said high speed digital backplanes.

The demands on the performance of modern backplanes has moved from what was once a straightforward device into the high-tech, high performance arena. Although many of the proprietary mainframe computer buses already require high performance, digital backplanes represented by VME and Multibus do not, although in order to gain optimum performance from these backplanes, good design and controlled manufacturing techniques are required.

The demands for a controlled transmission and termination impedance, tight crosstalk control and balanced signal skew demanded by both in-house designs and open standards, such as Futurebus+, requires an order of magnitude increase in design and production standards. The specified level of performance operated by this new bus standard far outweighs the increased costs required to meet the performance levels.

A large number of existing buses use driver devices which are derived from logic families, such as TTL to drive the backplane. Futurebus+ uses incident wave switching. This means that backplane speeds are limited by the basic physics of wave propogation only, so that the signal is therefore damped to the correct level at any one point. Consequently, there are no reflections or reflections are minimised below a certain threshold level so means that the backplane exhibits very good lined transmission properties. In particular, the VME and similar backplanes have requirements or recommendations for the intrinsic impedance of the backplane traces usually shown as implemented in microstrip. The Futurebus+ IEEE 896.2 specification has a mandatory requirement for the backplane impedance as modified by the through hole vias and the connectors. The value is 57 ohms with a tolerance of about 8%.

From this the backplane designer has to work backwards to determine the intrinsic backplane impedance and, consequently, a suitable backplane construction. The full relationships are complex and in order to meet the Futurebus+ requirements, a balanced tri-plane (strip line) implementation is required. The high signal density of the 2mm four-row connectors result in up to four strip line layers and the resulting boards are considerably thicker than those produced for VME. Of course, other numbers of strip line layers could be used.

The management of trace and connector loading effects as well as the requirement for a high pin count has resulted in a connector with finer geometries which adds further demands to the backplane manufacturer. The requirements for 2mm (0.079 ins) two-part connectors for printed wiring boards and backplanes are specified in EI (Electronic Industries Association) Standard EIA-IS64.

With incident wave switching it is very important t terminate correctly the backplane transmission line for all module loading conditions. In order to meet bus demands, microwave components and decoupling techniques are required. . The value of the termination is inevitably a compromise between an empty and a fully loaded backplane. The Futurebus+ specification require a 1%, 33 omhs resistor between the signal and a well decoupled 2%, 2.1 v. supply.

In addition, Futurebus+ uses very sharp edge rates, nanoseconds, which, with incident wave switching, place constraints on the amount of allowable crosstalk. The specification requires a worst case effect of 3% crossta under all conditions.

In order to meet this level of performance more is required than running screening traces between the signa lines. All of the lines on the backplane including ground connections exhibit inductive and capacative reactance effects in addition to resistance; these compl impedances need to be taken into account when designing screen traces.

Although the specification of Futurebus+ results in very high performance bus, there have been several associated technical problems which have arisen because of the specified high performance. One such problems are that the use of a 33 omhs resistor may not satisfy all loading conditions because the resistance is a fixed value and a bus has a problem that its behaviour is dependent on electrical loading. A further problem is that when dealing with very fast edge rates, for example, the 2nsecs. specified in the Futurebus+ standard, a small piece of wire, for example a quarter inch or half inch, has a significant effect on reflection and matching because of intrinsic inductance and capacitance at this frequency.

A further problem, although not specified in the Futurebus+ and TeleCombus specifications, has been an understanding that discrete chip resistors should be used typically of the 1205 or 0805 size. It will be appreciated that the pick and placement of these devices adds to the cost of the backplane and the individual nature of the devices has a small but significant reduction on the system MTBF (Mean Time Between Failure) . A further problem is that the existing specification does not address how the specified level of crosstalk is to be achieved under all conditions and particularly the very fast edge rates involved.

It is an object of the present invention to provide a bus termination system which obviates or mitigates at least one of the aforementioned disadvantages.

It is a further object of the invention to provide a resistor network chip set for a connection module to allo uni-directional connectors (buses) to be interfaced to appropriate resistor/capacitor networks to satisfy the Futurebus+ specification and to provide a high level of signal integrity.

This is achieved by providing a resistor and capacitor network physically next to the end of each transmission line with a capacitor being coupled to each of a group of resistors so as to satisfy the electrical requirements of the future bus specification.

According to one aspect of the present invention, there is provided a bus termination system for use with backplane transmission media, said bus termination system comprising termination means for terminating a transmission line of said transmission media, each termination means having a plurality of resistor means, capacitor means coupled to said plurality of resistors means, whereby the bus termination system acts to decoupl a signal on said backplane transmission line and a predetermined voltage supply.

Conveniently, a single resistor is coupled between each transmission line and a single capacitor, and the single capacitor is coupled between each resistor and a reference level. Preferably, the predetermined voltage supply is 2.1 volts. The voltage supply is coupled to the junction between the resistors and the capacitor.

Conveniently, the resistors are provided in a surface mounted resistor network printed on a ceramic substrate. Advantageously, the surface mount resistor network is a CTS Corporation Surface Mount type 766 encapsulated in and provided with gull-wing connectors in a narrow body gull-wing surface mount package. It is available in both a "network" form, where several resistors share a common pin, and a "ladder" form where each resistor has separate connections. Preferably the ladder form is used as this is closest to discrete resistor preference. It also minimises common mode crosstalk. The CTS Corporation Surface Mount 766 resistor network contains 8 resistive elements in a single package.

In a preferred arrangement, the surface mount chips are disposed on one side of a p.c. board. The chips could be located on both sides, i.e. on the top and the bottom or on the bottom only, depending on physical preference. The resistor network chips may contain different number of resistors, for example, 16 or 24, depending on preference. An advantage of using chip networks such as the CTS Corporation Surface Mount 766 is that the resistor specification can be chosen depending on requirements and standard circuits can be used so that crosstalk is minimised. Another advantage of using network chips is that the level of crosstalk produced by the packaging of the resistor elements in close proximity on a high dialectric constant substrate is minimised.

According to another aspect of the present invention, there is provided a method of terminating a backplane transmission line comprising, coupling a single resistor to each transmission line, coupling a group of resistors to a common reference level via a common capacitor, providing a predetermined voltage supply between said group of resistors and said common capacitor whereby said voltage supply is decoupled from a signal on said back plane transmission line.

Conveniently, the method includes coupling a single capacitor to 4 transmission lines via single resistors.

Conveniently, said single resistors are provided in a surface mount resistor network. Advantageously, the network is a 16 pin chip which is coupled to 8 tranmission lines and 4 of the resistors on the chip are coupled via a decoupling capacitor to ground, the other side of the decoupling capacitor being connected to a 2.1 voltage signal to comply with the future bus specification.

According to another aspect of the present invention, there is provided an impedance controlled high-speed printed circuit board comprising, a printed circuit board, at least one backplane connector coupled to said printed circuit board for receiving another printed circuit board, said backplane connector having a plurality of transmission line terminals coupled thereto, each transmission line terminal being coupled to a single resistor, and groups of said resistors being coupled together at selected locations, said location having a predetermined voltage level, said groups of resistors and predetermined voltage level being decoupled by a common capacitor from a reference level, said groups of resistors being implemented in a surface mount resistor network physically located in proximity to said backplane connector.

According to a further aspect of the present invention, there is provided a bus termination system comprising a chip having a plurality of resistor means for coupling to a transmission line, the resistor means being further coupled to a single capacitor, the chip and the capacitor being located in close proximity to the termination of the transmission line.

According to a still further aspect of the present invention, there is provided a bus termination arrangement comprising a circuit board carrying a plurality of chips each having a plurality of resistor means for coupling to a transmission line through individual connecting means and the resistor means of each chip being further coupled to a single capacitor, wherein the connecting means are regularly spaced at a standard pitch and extend in rows along the circuit board, the chips are of a standard length and mounted along at least one side of the rows of connecting means adjacent the corresponding connecting means and the relative sizing of the pitch of the connecting means and the length of the chips permits location of a capacitor between the ends of adjacent chips

These and other aspects of the present invention will be described with reference to the accompanying drawings in which:-

Fig. 1 is a plan view of a printed circuit board having a plurality of backplane connectors which are terminated in accordance with the present invention;

Fig. 2 is an enlarged view of part of the circuit board of Fig. 1 with the backplane connector removed to show the tracking connections between the circuit board and the bus termination resistor and capacitor networks;

Fig. 2a is a circuit diagram of the electrical circuit connected between 4 terminals of separate transmission lines and a ground implemented by one of the chips shown in Fig. 2, and

Fig. 3 depicts a cross-sectional view on lines 3-3 of Fig. 2 depicting the physical layout and positioning of the network chips and capacitors with a backplane connector also shown coupled to the circuit board.

Reference is first made to Fig. 1 of the drawings which depicts a printed circuit board generally indicated by reference numeral 10 which has a plurality of backplane connectors 12 shown mounted therein. Each connector 12 is a 2mm two-part connector such that there are 4 rows of connectors 14 which are separated by 2mm. In addition, each column of connectors is separated by 2mm from an adjacent column complying with the EIA - IS 64 Standard (Electronic Industries Association) .

Reference is now made to Fig. 2 of the drawing which depicts part of the circuit board 10 shown in Fig. 1 with the back plane connector 12 omitted in the interest of clarity. It will be seen that there are 4 columns of via holes 15 in the printed circuit board 10 such that each row has 4 holes. Each hole 15 is adapted to be coupled to one of the pins 14 of the connectors shown in Fig. 3. From an inspection of Fig. 2 it will be seen that there are 2 holes in each row indicated by reference numeral 16 and shown as a double circle which are ground terminals. The grounds are necessary to provide the double ground screening in each line to meet the Futurebus+ specification requirements. The general outline of the connector 12 is shown and it will be seen that there are a plurality of surface mounted chips generally indicated by reference numeral 18 located adjacent the connector 12. Each surface mounted chip 18 is identical and only one will be described in the interest of clarity, although it will be appreciated that the description is applicable to all of the chips 18.

The chip 18 is a CTS Corporation surface mount 766 resistor network chip which is printed on a ceramic substrate and is encapsulated and provided with 16 gull-wing connectors in a narrow body gull-wing surface mount package. In the resistors chip 18 is arranged in a ladder form as can be seen in Fig. 2a.

It will be seen that each chip 18 is connectable to 8 transmission lines via connecting holes 15. The resistor chip 18 provides in combination with capacitors 20, the bus or transmission line termination means for each transmission line in the high speed digital backplane.

In the embodiment shown, each resistor chip 18 receives input from the 8 transmission lines; each resistor chip 18 has 8 resistors and 4 of the resistors are electrically connected together as seen in Fig. 2a to provide a termination means which complies with the future bus requirements. This is best understood with reference to Fig. 2a which depicts the top 4 transmission lines ofthe top right chip 18 being connected together. Each transmission line (or line hole 15) is connected to a single resistor R in the network chip 18. The other ends of each of the 4 resistors are connected together at a common terminal 22. A capacitor 20 is connected between the terminal 22 and ground 24. The connection between the capacitor 20 and resistors at junction 22 is also connected to a 2.1v voltage at connector 26 as shown in accordance with the Futurebus+ specification.

It will be appreciated that each transmission line is connected through a single resistor R in a resistor network package 18 so that the signal on the transmission line is decoupled from a 2.1 voltage supply and capacitor 20 decouples the resistors from the reference ground level. The resistors are 33 ohms 1% resistors and the 2.1 volts is a 2% voltage supply as required by the Futurebus+ specification.

It will be appreciated that the provision of resistors in a printed ceramic substrate facilitates the termination of the transmission lines in the backplane with the resistors and capacitors being located physically very close to the physical termination of the transmission line.

An advantage of this arrangement is the very close proximity of the network packages in relation to the physical termination of the transmission line conductors facilitate close packing of the arrangements shown and also minimise the level of crosstalk such that it complies with the Futurebus+ requirements. A further advantage of incorporating resistor networks in the chip as shown is it permits flexibility of the choice of resistor specification as the resistors can either be coupled in the ladder arrangement as shown or in other arrangements as specified for the CTS Corporation surface mount 766/767 resistor networks.

Various modifications may be made to the embodiment hereinbefore described without departing from the scope of the invention. For example, the resistor network chips could be located on the same side as the connector 12 as shown in Fig. 3 or they could be located on the opposite side of the circuit board. Furthermore, some could located on one side of the board and some on the other side, depending on the particular requirements. In addition, the size of the resistor packages may be varied, for example, to have a 32 or 24 pins depending on requirements. In addition, a capacitor may be coupled between a number of resistors other than 4, for example, 3, 5 or 6 resistors could be grouped depending on particular requirements, although 4 is particularly the more convenient grouping for 2mm 4 row back plane connector.

Advantages of the present invention are that the reduced track length to terminators facilitates accurate matching and reduces crosstalk from surface tracking and also reduces the inductive and capacative effects. The provision of the resistor network and surface mount resistors allows flexibility in the choice of resistor packages and also in the choice-of resistor specification without the drawback of discreet components in picking and placing. In addition, they are surface mount packages, they can be readily installed using convention pick and place technology, thus minimising assembly cost. The use of resistor network packages provides higher MTBF requirements and the invention results in a high-speed digital back plane transmission line termination system which satisfies the Futurebus+ specification.

Claims

1. A bus termination system for use with backplane transmission media, said bus termination system comprising termination means for terminating a transmission line of said transmission media, each termination means having a plurality of resistor means, capacitor means coupled to said plurality of resistors means, whereby the bus termination system acts to decouple a signal on said backplane transmission line and a predetermined voltage supply.

2. A system as claimed in claim 1 wherein a single resistor is coupled between each transmission line and a single capacitor, and the single capacitor is coupled between each resistor and a reference level.

3. A system as claimed in claim 1 or claim 2 wherein the predetermined voltage supply is 2.1 volts.

4. A system as claimed in any preceding claim wherein the voltage supply is coupled to the junction between the resistors and the capacitor.

5. A system as claimed in any preceding claim wherein the resistors are provided in a surface mounted resistor network printed on a ceramic substrate.

6. A system as claimed in claim 5 wherein the surface mount resistor network is and provided with gull-wing connectors in a narrow body gull-wing surface mount package.

7. A system as claimed in claim 5 or claim 6 wherein said surface mount resistor network is arranged in a network format where several resistors share a common pin.

8. A system as claimed in claim 5 or claim 6 wherein said surface mount resistor network is arranged in a ladder format where each resistor has separate connections

9. A system as claimed in any one of claims 5 to 8 wherein the surface mounted resistor network is disposed on one side of a p.c. board.

10. A system as claimed in any one of claims 5 to 8 wherein the surface mounted resistor network is disposed on both sides of a p.c. board.

11. According to another aspect of the present invention, there is provided a method of terminating a backplane transmission line comprising, coupling a single resistor to each transmission line, coupling a group of resistors to a common reference level via a common capacitor, providing a predetermined voltage supply between said group of resistors and said common capacitor whereby said voltage supply is decoupled from a signal on said back plane transmission line.

12. A method as claimed in claim 11 wherein the method includes coupling a single capacitor to four transmission lines via single resistors.

13. A. method as claimed in claim 11 or claim 12 wherein the network is a 16 pin chip which is coupled to eight tranmission lines and two of the resistors on the chip are coupled via a decoupling capacitor to ground, the other side of the decoupling capacitor being connected to a 2.1 voltage signal to comply with the future bus specification.

14. An impedance controlled high-speed printed circuit board comprising, a printed circuit board, at least one backplane connector coupled to said printed circuit board for receiving another printed circuit board, said backplane connector having a plurality of transmission line terminals coupled thereto, each transmission line terminal being coupled to a single resistor, and groups of said resistors being coupled together at selected locations, said location having a predetermined voltage level, said groups of resistors and predetermined voltage level being decoupled by a common capacitor from a reference level, said groups of resistors being implemented in a surface mount resistor network physically located in proximity to said backplane connector.

15. A bus termination system comprising a chip having a plurality of resistor means for coupling to a transmission line, the resistor means being further coupled to a single capacitor, the chip and the capacitor being located in close proximity to the termination of the transmission line.

16. A bus termination arrangement comprising a circuit board carrying a plurality of chips each having a plurality of resistor means for coupling to a transmission line through individual connecting means and the resistor means of each chip being further coupled to a single capacitor, wherein the connecting means are regularly spaced at a standard pitch and extend in rows along the circuit board, the chips are of a standard length and mounted along at least one side of the rows of connecting means adjacent the corresponding connecting means and the relative sizing of the pitch of the connecting means and the length of the chips permits location of a capacitor between the ends of adjacent chips.