WO1993018580A1

WO1993018580A1 - Digital phase locked loop for token ring networks

Info

Publication number: WO1993018580A1
Application number: PCT/US1993/002122
Authority: WO
Inventors: Ivan A. Reede
Original assignee: Cabletron Systems, Inc.
Priority date: 1992-03-09
Filing date: 1993-03-08
Publication date: 1993-09-16

Abstract

A digital phase locked loop includes a digital phase error estimator (100) for providing a phase error signal representative of a phase error between an input signal and an output signal at discrete time intervals, a phase error integrator (102) for providing a phase correction command when the phase error signal represents the same polarity phase error for a selected number of successive discrete time intervals, a synthesizer (108) for generating a synthesized signal having a digitally controllable frequency or phase, and a controller (106) for digitally controlling the phase or frequency of the synthesized signal to provide the output signal such that the phase error is maintained within prescribed limits.

Description

DIGITAL PHASE LOCKED LOOP FOR TOKEN

RING NETWORKS

Field of the Invention

This invention relates to digital phase locked loops and, more particularly, to a digital phase locked loop which contains a digital phase error integrator and which has a constant phase slope. The digital phase locked loop of the invention is preferably utilized for clock recovery in a token ring network, but is not limited to such use.

Background of the Invention

A token ring computer network includes a

plurality of stations connected to a data

transmission path, or trunk, in the form of a closed loop. A block diagram of a conventional token ring network is shown in FIG. 1. Trunk coupling units (TCU's) 10, 12, 14, 16, 18, etc. are connected in series on a ring 20. Stations 22, 24, 26, 28, and 30 receive and transmit signals through TCU's 10, 12, 14, 16 and 18, respectively. A token ring network can include up to 250 stations. The ring 20 can comprise shielded twisted pair, unshielded twisted pair, optical fiber, or any other suitable media (for example, microwave).

The token ring network uses a synchronous data transmission technique wherein a clock and data are combined in the transmitted signal. As used herein, the term "signal" refers to the combined data and clock utilized in token ring networks. The data and clock remain combined except within the station. A clock transition occurs at the center of each data bit position. A transition or lack a thereof at the beginning of each bit position indicates a one or a zero in the binary data. In the insert mode, the transmitted signal is received by a TCU from its upstream neighbor and is forwarded to the station. The station receives the signal and recovers the clock and data it contains. The station then combines the two to form a new signal and

retransmits the signal to its TCU. Its TCU in turn forwards the signal to its downstream neighbor. In bypass mode, as contrasted with insert mode, the TCU forwards the signal it receives from its upstream neighbor directly to its downstream neighbor. This process is repeated until the signal reaches the active monitor. When the active monitor receives the signal, it sinks the recovered clock and stores the recovered data in a FIFO buffer. The active monitor then builds a new signal with the data and its own internal clock. The new signal then goes through the same repeating process as it did before the active monitor until it reaches the station which initially transmitted the data. Along its path, the signal data content may also have been altered if the signal passed its destination, where it will have been marked as received, or if a station detected an error in the data content of the signal, where it will have been marked as

erroneous. The operation and signalling in token ring networks is governed by IEEE 802.5/1989 Stand for Token Ring Systems.

The clock that circulates through a token ring network is generated by a station designated as the active monitor. All other stations, designated as standby monitors, recover the clock from the

transmitted signal using clock recovery circuit, which is typically a phase locked loop. Although the clock recovery circuit is typically a phase locked loop, LC type tank circuits have been

proposed. A block diagram of a station in a

conventional token ring network is shown in FIG. 2. Incoming signal passes through an equalizer 40 to a phase locked loop 42 or other clock recovery circuit and a demodulator 44. The phase locked loop

recovers the clock from the incoming signal and controls the demodulator 44. The recovered signal is input to a FIFO buffer 46 if the station is the active monitor. The recovered data and clock are supplied to a MAC layer and SMT within the station after buffering for the active monitor. The output data from the station is supplied by the MAC to a modulator 48 which combines the data and clock to form a signal which it inputs to a transmit filter 50. The modulator 48 is controlled by the recovered clock from the phase locked loop 42 when the station is a standby monitor. The modulator 48 is

controlled by a local clock 52 (active monitor clock) when the station is the active monitor.

An improved token ring network architecture is disclosed in copending application Serial No.

(Attorney's Docket No. C0441/7012), filed

concurrently herewith and entitled "Accelerated Token Ring Network". In the disclosed token ring network architecture, stations are decoupled into separate clock domains such that clock jitter does not propagate through the network. A local clock at ah accelerated clock rate is generated at each trunk coupling unit or concentrator. The station

connected to the trunk coupling unit or concentrator is operated at the accelerated clock rate when the station is a standby monitor, is operated at the active monitor clock rate when the station is the active monitor and is operated at the station's own clock rate when the station is in loopback mode. Signal is received from the trunk and is transmitted to the trunk at the active monitor clock rate. The station thereby operates at the accelerated clock rate of the local clock except when the station is the active monitor or is in loopback mode. The concentrator, the trunk coupling units and the stations in the accelerated token ring utilize clock recovery circuits.

The conventional clock recovery circuits used in token ring networks are analog phase locked loops or LC tank type circuits. The circuitry is physically large and relatively expensive and can only

partially be fabricated in integrated circuits. In addition, analog phase locked loops often require adjustment to compensate for or control the effects of spurious poles and component tolerances.

It is a general object of the present invention to provide digital phase locked loops.

It is another object of the present invention to provide digital phase locked loops having a digital phase error integrator to reduce phase noise.

It is another object of the present invention to provide digital phase locked loops having a constant phase slope.

It is a further object of the present invention to provide digital phase locked loops having a digitally controlled phase error integrator and a digitally controlled phase slope.

It is a further object of the present invention to provide digital phase locked loops suitable for clock recovery in token ring networks.

It is still another object of the present invention to provide digital phase locked loops which are simple in construction and low in cost.

Summary of the Invention

According to the present invention, these and other objects and advantages are achieved in a digital phase locked loop comprising a digital phase error estimator responsive to an input signal and an output signal for providing a phase error signal representative of a phase error between the input signal and the output signal at discrete time intervals, phase error integrator means for

providing a phase correction command when the phase error signal represents the same polarity phase error for a preselected number of successive

discrete time intervals, a synthesizer for

generating a synthesized signal having a digitally controllable frequency or phase, and control means responsive to the phase correction command for digitally controlling the phase or frequency of the synthesized signal to provide the output signal such that the phase error is maintained within prescribed limits.

The phase error signal is preferably a binary signal having first and second states, one of which represents phase lag between the input signal and output signal and the other of which represents phase lead.

The phase error integrator preferably includes a first counter, means for advancing a count in the first counter when the phase error signal represents constant polarity phase error on successive time intervals, means for resetting the count in the first counter when the phase error signal represents a reversal in phase error polarity, and means for generating a phase correction command and for resetting the first counter when the count in the first counter reaches a predetermined number.

The synthesizer preferably comprises a phase signal generator for generating a plurality of phase signals of the same frequency and different phases, and the control means preferably comprises selector means for selecting one of the phase signals as the output signal. A phase signal that is closest in phase to the input signal is selected by the

selector means as the output signal.

In a first embodiment, the selector means includes a second counter and a data selector that selects one of the phase signals as the output signal in response to a count contained in the second counter. The count in the second counter is incremented or decremented in response to the phase correction command.

In a second embodiment, the selector means includes a shift register and a data selector that selects one of the phase signals as the output signal in response to a bit contained in the shift register. The position of the bit in the shift register is shifted in response to the phase

correction command.

When the digital phase locked loop is used in a token ring network, the input signal typically comprises synchronously clocked data having an embedded clock, and the output signal comprises a recovered clock. In a preferred embodiment, the phase error estimator comprises a D type flip-flop having a clock input and a D input. The data is applied to the clock input and the recovered clock is applied to the D input. This configuration evaluates phase on every data transition and

provides constant bandwidth.

According to another aspect of the invention, there is provided a method for phase locking an output signal to an input signal. The method comprises the steps of detecting a phase error between the input signal and the output signal and providing a phase error signal representative of the phase error at discrete time intervals, providing a phase correction command when the phase error signal represents the same polarity phase error for a preselected number of successive discrete time intervals, generating a synthesized signal having a digitally controllable frequency or phase, and digitally controlling the phase or frequency of the synthesized signal to provide the output signal in response to the phase correction command such that the phase error is maintained within prescribed limits.

Brief Description of the Drawings

For a better understanding of the present invention, together with other and further objects, advantages and capabilities thereof, reference is made to the accompanying drawings which are

incorporated herein by reference and in which: FIG. 1 is a block diagram of a conventional token ring network;

FIG. 2 is a block diagram of a station in a conventional token ring network;

FIG. 3 is a block diagram of a digital phase locked loop in accordance with the present invention;

FIG. 4 is a schematic diagram of a circuit suitable for demonstration of digital phase locked loop principles in accordance with the present invention;

FIG. 5 is a phase diagram that illustrates the relative phases of the phase signals generated by the phase signal generator for the case of 16 phase signals;

FIG. 6 is a timing diagram that illustrates the relative phases of the phase signals generated by the phase signal generator;

FIG. 7 is a state diagram that illustrates the operation of the phase error integrator;

FIG. 8 is a schematic diagram of a digital phase locked loop in accordance with a second embodiment of the present invention; and

FIG. 9 is a schematic diagram of a

digitally-controlled analog phase synthesizer in accordance with another embodiment of the invention.

Detailed Description of the Invention

A block diagram of a digital phase locked loop (DPLL) in accordance with the present invention is shown in FIG. 3. An input signal, designated as DATA, is applied to an input of a phase error estimator 100. A second input to the phase error estimator 100 is the output signal of the DPLL, designated as R CLK. The phase error estimator 100 determines a phase error between the input signal and the output signal at discrete time intervals and provides a phase error signal to a phase error integrator 102. The phase error signal is

preferably a binary signal having a first state that represents a phase lag between the input and output signals and a second state that represents a phase lead between input and output signals.

Alternatively, the phase error signal can be a digital signal that quantifies the amount of lead or lag between the input and output signals. A phase error signal is generated on each transition of the input signal.

The phase error integrator 102 requires that a phase error signal of one polarity be present for a selected number of successive time intervals before a phase correction is made. An integration rate controller 104 controls the parameters of the phase error integration. When the phase error signal quantifies the amount of lead or lag, this signal can influence the rate at which the phase error integrator accumulates phase error. The phase error integrator 102 provides a phase correction command to a phase selector, or phase controller, 106. A phase generator, or synthesizer, 108 generates a synthesized signal having a digitally controllable frequency or phase. In response to the phase correction command, the phase selector 106 controls the phase or frequency of the synthesized signal to provide the output signal of the DPLL. The phase or frequency of the synthesized signal is controlled so as to maintain the phase error between the input and output signals within prescribed limits.

A block diagram of a circuit suitable for demonstrating the operating principles of the digital phase locked loop of the present invention is shown in FIG. 4. The implementation of a digital phase locked loop for use in a token ring network requires the use of higher speed circuits than those shown in FIG. 4, but which are equivalent in

function to those shown. It will be understood that the circuit of FIG. 4 is only one example of a DPLL circuit in accordance with the present invention.

A D-type flip-flop 120 functions as the phase error estimator, or phase detector. The input signal DATA is applied to the clock input of

flip-flop 120, and the output signal R CLK

(recovered clock) is applied to the D input of flip-flop 120. As discussed below, this connection of DATA and R CLK signals to flip-flop 120 provides advantageous operation in a token ring network.

The Q output of flip-flop 120 is input to an exclusive OR gate 122 and to the D input of a flip-flop 124. The input signal DATA is applied through an inverter 126 to the clock input of flip-flop 124. The Q' output of flip-flop 124 is input to exclusive OR gate 122. The Q output of flip-flop 120 represents either a phase lead or a phase lag between the input signals to the phase detector and constitutes the phase error signal. The Q' output of flip-flop 124 represents the polarity of the phase error signal.

The output of exclusive OR gate 122, which represents a reversal of phase error polarity, is applied through a gate 128 to the clear input of a phase error integrator counter 130. The output signal R CLK is applied to the clock input of counter 130. The application of the output signal R CLK to the clock input of counter 130 locks the maximum phase slope of the DPLL to the recovered clock. Alternatively, any other clock could be used to control the phase slope or capture and tracking range of the DPLL. First and second stage outputs of counter 130 are input to an AND gate 132. The counter 130 functions as a phase error integrator as described below. The output of AND gate 150 is applied to the clock input of a phase selection counter 136 and to a second input of gate 128. The Q' output of flip-flop 124 is applied to the UP/DOWN control input of phase selection counter 136.

The outputs of phase selection counter 136 are applied to the select inputs of a data selector 138. The data inputs to selector 138 on lines 140 comprise phase signals generated by a counter 142 and shift registers 144 and 146. The phase signals are square waves which have the same frequency and are shifted in phase relative to each other. In the example of FIG. 4, 16 phase signals are utilized. The phases of the phase signals are uniformly distributed between 0° and 360°. It will be

understood that a variety of different circuits can be utilized for generating phase signals. The data selector 138 selects one of the phase signals in response to the state of the phase selection counter 136 as the output signal R CLK of the DPLL. The phase signal is selected so as to maintain the phase error between the input signal DATA and the output signal R CLK of the DPLL within prescribed limits.

The configuration of the phase detector shown in FIG. 4 is particularly advantageous when the DPLL is used for clock recovery in a token ring network. The token ring network uses a signaling technique wherein the clock and data are combined in a

synchronously clocked signal, designated as DATA in FIG. 4. In this signalling technique, transitions on the DATA input do not occur for every recovered clock transition. Thus, if the recovered clock signal were applied to the clock input of flip-flop 120, corresponding data transitions would not occur on some clock cycles and the phase detector would produce erroneous results. By applying the input signal DATA to the clock input of flip-flop 120 and the recovered clock R CLK to the D input, phase evaluations are made only when data transitions occur. Thus, the phase detector evaluates whether the recovered clock R CLK occurs before or after a data transition. When data transitions do not occur, evaluations of phase error are not made by the phase detector. This configuration results in the digital phase locked loop having constant gain.

In order to prevent continuous output phase correction, which would lead to excessive phase noise, the phase error integrator is designed with a zone, similar to hysteresis, in which phase

corrections are not made. A phase correction command is sent to the phase selector only when the phase error exceeds a selected upper or lower limit for a determined time. This prevents the DPLL loop from continuous hunting for a zero error phase on each and every cycle, which may cause transmit asymmetry and undesired recovered clock sidebands. The phase correction command generated by the phase error integrator has three output states: excess phase lead, excess phase lag, and within lead/lag limits (no correction required).

The operation of the phase error integrator can be understood with reference to FIG. 4. The phase correction commands described above are provided to phase selection counter 136 on lines 150 and 152. The sign of the phase correction command, lead or lag, is provided by the O' output of flip-flop 124 on line 152. This signal controls whether phase selection counter 136 is incremented or

decremented. A clock input is provided to counter 136 on line 150 only when phase error integrator counter 130 reaches a count of four. Counter 130 reaches a count of four only when the phase error signal represents the same polarity phase error (lead or lag) on four successive cycles of the clock R CLK applied to counter 130. Each time the phase error changes polarity, the counter 130 is reset to zero. The output of exclusive OR gate 122

represents a change in polarity of the phase error signal and causes counter 130 to be cleared. Thus, for example, when the phase error signal represents phase lead on three successive cycles followed by phase lag, the change in polarity between the third and fourth cycles causes counter 130 to be reset, and no phase correction command is given. Now consider the case where the phase error signal represents phase lead on four successive cycles. The counter 130 reaches a count of four, and a phase correction command is given on line 150. The counter 136 is incremented or decremented, depending on the state of the UP/DOWN input on line 152.

Thus, the phase selection counter 136 is incremented or decremented only when the phase error signal represents phase error of the same polarity on four successive cycles.

It will be understood that the number of

successive cycles of the same polarity phase error required before phase correction can be varied to meet the requirements of a particular system. The phase error integrator can be controlled by changing the count in counter 130 required to trigger phase correction command. The required count can easily be placed under computer control. Furthermore, the counter 130 is not necessarily reset upon a reversal of phase error polarity. In an alternative

embodiment, the counter 130 is advanced in the opposite direction by a fixed or variable number when a reversal in phase error polarity occurs.

This approach may be particularly advantageous when the phase error is quantified as discussed above. The general approach is to have a nonlinear process take place wherein the error integration counter, which operates in clear logic, is transformed to a state machine that operates as a fuzzy logic device wherein the decision process to apply a phase correction slows down when that decision process is not clear cut, as in the presence of noise and jitter on the DATA input. Such speed reduction dynamically changes the bandwidth and dynamically reduces the tracking range in the presence of noise and jitter and is an attempt to avoid making a decision to correct the output phase and then having to reverse that correction.

The phase generator 108 in the DPLL of the present invention replaces the voltage controlled oscillator in a conventional analog phase locked loop with a pulse dithering, controlled phase generator. The phase generator synthesizes a signal of the exact output frequency and phase as the input signal. The pulse dithering, controlled phase generator uses a technique whereby, rather than attempting to control the rate of change of an oscillator phase as a function of time, the input signal directly controls the output phase.

The control is digital in nature and takes the form of two possible commands. The first phase correction command is to move the phase of the output signal by a portion of a cycle in a forward direction. The second phase correction command is to move the phase of the output signal backwards by a portion of a cycle. These commands are

implemented in the circuit of FIG. 4 by incrementing or decrementing phase selection counter 136. In the absence of a phase correction command, the phase of the output signal is maintained constant. This corresponds to a fixed count in counter 136.

The phases of the different phase signals are illustrated in the phasor diagram of FIG. 5. In the present example, 16 phase signals are uniformly distributed between 0° and 360°. Thus, adjacent phase signals are separated in phase by 22.5°. Each phasor shown in FIG. 5 represents one of the 16 phase signals and corresponds to one of the states of phase selection counter 136. The states of the counter 136 are indicated at the end of each

phasor. Corresponding phase signals are shown in FIG. 6. It will be understood that more or fewer than 16 phase signals can be utilized within the scope of the invention.

A state diagram illustrating the operation of the DPLL of FIG. 4 is shown in FIG. 7. Each circle represents a different state of the circuit. Different states in horizontal rows of states represent different states of phase error integrator counter 130. States in different vertical positions represent different states of phase selection counter 136. By way of example, horizontal row 200 shown in FIG. 7 represents state 6 of phase

selection counter 136 and the phasor labeled 6 in FIG. 5. For state 6 of counter 136, phase signal 6 is selected as the output signal of the DPLL.

State 202 at the center of row 200 represents the reset condition of phase error integrator counter 130. Successive phase error signals

representing one polarity phase error cause counter 130 to be incremented to states 204, 206 and 208. Successive phase error signals representing the opposite polarity phase error cause counter 130 to be incremented to states 210, 212 and 214. In the present example, the counter 130 is incremented in only one direction, and the polarity is indicated by the output of flip-flop 124 on line 152.

Importantly, a phase error signal representing a phase error reversal causes the counter 130 to be reset from any of states 204, 206, 208, 210, 212 and 214 to state 202. Successive phase error signals of the same polarity are required to advance counter 130. When the counter 130 is in state 208 and a phase error signal of the same polarity is received, a phase correction command is input to counter 136, thereby advancing counter 136 to state 220 and resetting counter 130. Similarly, when the counter 130 is in state 214, and a phase error signal of the same polarity is received, a phase correction command is input to counter 136, thereby causing counter 136 to be decremented to state 222 and counter 130 to be reset. In general, it can be seen that phase error signals representing the same polarity phase error are required on four successive cycles to generate a phase correction command. A change in the phase error signal polarity causes the counter 130 to be reset rather than incremented in the opposite direction. As described above, this configuration provides a zone where no phase

correction commands are given, thereby preventing continuous phase correction. The size of the zone in which phase corrections are not made can be varied by changing the number of successive phase error signals of the same polarity required to trigger a phase correction command.

The phase step size and stepping rate of the DPLL of the present invention is independent of the magnitude of the input phase error. When phase stepping occurs, it takes place at a predetermined rate and by predetermined increments. The frequency of the phase signals is matched to the nominal frequency of the input signal. The operating parameters of the DPLL, such as capture range and tracking range, are determined by the parameters of the phase error integrator counter 130 and the number of phase signals utilized.

As noted above, a preferred application of the digital phase locked loop of the present invention is in token ring networks for clock recovery. It is known that a critical issue in token ring station interoperability is filtered accumulated phase slope (FAPS). This condition results from multiple phase locked loops operating in series. When an input signal containing FAPS is received by the DPLL of the present invention, the recovered clock output steps in the direction of the FAPS as predicted. However, the DPLL of the present invention can be designed to insure that under no circumstances will it exceed the maximum acceptable FAPS. When the received FAPS is excessive and cannot be

accommodated within the available tracking range, the circuit provokes a ring failure at the receiving side. This causes the FAPS induced failure to occur as close as possible to the source of the failure. Moreover, attenuation is guaranteed to take place within the station in the form of a predetermined maximum tracking error. FAPS is therefore

attenuated as it propagates from one station to the next when the DPLL of the present invention is used.

A schematic diagram of a second embodiment of a digital phase locked loop in accordance with the invention is shown in FIG. 8. The circuit of FIG. 8 is capable of operation at 16 MHz as required in a token ring network. The phase detector and the phase error integrator have the same configuration shown in FIG. 4 and described above. The phase synthesizer uses a counter 240 and a shift register 242 to generate eight phase signals at twice the required frequency. Adjacent phase signals are separated in phase by 45°. One of the eight phase signals is selected by a set of eight gates 244, and the frequency of the selected phase signal is divided by two by a flip-flop 246. The output of flip-flop 246 is the output signal R CLK. In this embodiment, the selection of phase signal is

performed by a shift register 250. A single zero bit is loaded in shift register 250 and is shifted left or right in response to the phase correction command to select the required phase signal.

A schematic diagram of a digitally controllable analog phase synthesizer is shown in FIG. 9. An oscillator 260 supplies a sine wave output to a transformer 262 and supplies the sine wave output through a 90° phase shifter 264 to a transformer 266. Digital control inputs Phi A+, Phi A-, Phi B+, Phi B-, AMPL A and AMPL B permit selection of an output having the required phase on an output line 270. The digital control inputs are typically + or - 12 volts and permit selection of one of 16

phases.

The digital phase locked loops shown and

described above have been implemented in hardware. The DPLL of the present invention can also be implemented as a computer program, a state machine or firmware. Table I below shows an implementation of the DPLL in the Symphony spreadsheet program. The first letter in the "ID" column is the spreadsheet array. The n value is the row in the spreadsheet array, and [n-1] refers to the previous row in the spreadsheet array. Delayed signals simulate a propagation delay. In this state machine program, the input of inverter 126 is connected to R CLK instead of DATA. This is not a significant change as transitions on R CLK and DATA occur almost simultaneously. Starting with every variable at zero initially and inputting a signal to An, this program requires and maintains lock. It is therefore a software implementation of the DPLL. The results of the software implementation of the DPLL are shown in attached Appendix A.

While there have been shown and described what are at present considered the preferred embodiments of the present invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the scope of the invention as defined by the appended claims.

Claims

CLAIMS What is claimed is:

1. A digital phase locked loop comprising:

a digital phase error estimator responsive to an input signal and an output signal for providing a phase error signal representative of a phase error between the input signal and the output signal at discrete time intervals;

phase error integrator means for providing a phase correction command when said phase error signal represents the same polarity phase error for a selected number of successive discrete time intervals;

a synthesizer for generating a synthesized signal having a digitally controllable frequency or phase; and

control means responsive to the phase correction command for digitally controlling the phase or frequency of the synthesized signal to provide the output signal such that the phase error is

maintained within prescribed limits.

2. A digital phase locked loop as defined in claim 1 wherein said phase error signal is a binary signal having first and second states, one of which

represents phase lag of said input signal relative to said output signal and the other of which represents phase lead.

3. A digital phase locked loop as defined in claim 1 wherein said phase error integrator means

includes:

a first counter;

means for advancing a count in said first

counter when the phase error signal represents constant polarity phase error on successive time intervals;

means for resetting the count in said first counter when the phase error signal represents a reversal in phase error polarity; and

means for generating a phase correction command and for resetting said first counter when the count in said first counter reaches a predetermined number.

4. A digital phase locked loop as defined in claim

3 wherein said synthesizer comprises a phase signal generator for generating a plurality of phase

signals of the same frequency and different phases and said control means comprises selector means for selecting one of the phase signals as the output signal.

5. A digital phase locked loop as defined in claim

4 wherein said selector means includes a second counter and a data selector that selects one of the phase signals as the output signal in response to a count contained in said second counter, the count in said second counter being incremented or decremented in response to said phase correction command.

6. A digital phase locked loop as defined in claim 4 wherein said selector means includes a shift register and a data selector that selects one of the phase signals as the output signal in response to a bit contained in said shift register, the position of the bit in said shift register being shifted in response to said phase correction command.

7. A digital phase locked loop as defined in claim 4 wherein said phase signal generator generates phase signals that are equally distributed in phase between 0° and 360°.

8. A digital phase locked loop as defined in claim 1 wherein said input signal comprises synchronously clocked data having an embedded clock and wherein said output signal comprises a recovered clock.

9. A digital phase locked loop as defined in claim 8 wherein said phase error estimator comprises a D-type flip-flop having a clock input and a D input and wherein said data is applied to said clock input and said recovered clock is applied to said D input.

10. A method for phase locking an output signal to an input signal, comprising the steps of:

detecting a phase error between the input signal and the output signal and providing a phase error signal representative of the phase error at discrete time intervals;

providing a phase correction command when said phase error signal represents the same polarity phase error for a selected number of successive discrete time intervals;

generating a synthesized signal having a

digitally controllable frequency or phase; and

digitally controlling the phase or frequency of the synthesized signal to provide the output signal in response to the phase correction command such that the phase error is maintained within prescribed limits.

11. A method as defined in claim 10 wherein the step of detecting a phase error and providing a phase error signal comprises the steps of providing a binary phase error signal having first and second states, one of which represents phase lag of the input signal relative to the output signal and the other of which represents phase lead.

12. A method as defined in claim 10 wherein said input signal comprises synchronously clocked data having an embedded clock, wherein said output signal comprises a recovered clock and wherein the step of detecting a phase error and providing a phase error signal includes applying the synchronously clocked data to the clock input of a D-type flip-flop and applying the recovered clock to the D input of said flip-flop.

13. A method as defined in claim 10 wherein the step of providing a phase correction command includes: advancing the count in a first counter when the phase error signal represents constant polarity error on successive time intervals;

resetting the count in said first counter when the phase error signal represents a reversal in phase error polarity; and

generating a phase correction command and resetting said first counter when the count in said first counter reaches a predetermined number.

14. A method as defined in claim 13 wherein the step of generating a synthesized signal includes

generating a plurality of phase signals of the same frequency and different phases and wherein the step of digitally controlling phase or frequency

comprises selecting one of the phase signals as the output signal.

15. A method as defined in claim 14 wherein the step of selecting one of the phase signals includes selecting one of the phase signals in response to a count contained in a second counter and incrementing or decrementing count in the second counter in response to the phase correction command.

16. A method as defined in claim 14 wherein the step of selecting one of the phase signals includes selecting one of the phase signals in response to a bit contained in a shift register and shifting the position of the bit in said shift register in response to said phase correction command.

17. A method as defined in claim 14 wherein the step of generating a plurality of phase signals includes generating phase signals that are equally

distributed in phase between 0° and 360°.