WO1993015463A1

WO1993015463A1 - A method of providing a communication circuit for transferring data between a processor system and an external system

Info

Publication number: WO1993015463A1
Application number: PCT/DK1993/000022
Authority: WO
Inventors: Jan Kristoffersen
Original assignee: Jan Kristoffersen
Priority date: 1992-01-22
Filing date: 1993-01-22
Publication date: 1993-08-05
Also published as: DK8292A; AU3449593A; DK169224B1; DK8292D0

Abstract

A method of providing a communication circuit between a processor system and an external system (EB) by means of the signals normally used to a read-only storage, such as a ROM or EPROM. According to the invention the address bus (AB) of the processor system and the read control signal (RC) are used to generate the transmission data, the address bus (AB) utilizing selected addresses to form the transmission data in interaction with the CPU of the processor system, said addresses being transmitted from the processor system by the read control signal (RC) triggering a data port by means of an address control circuit (AMC). As a result, it is possible to perform a write operation by means of the existing signals for a read-only storage, such as a ROM or EPROM, thus utilizing that the mentioned ROM or EPROM is mounted on a socket, whereby it is possible to provide an extra communication circuit to an existing processor system.

Description

Title: A method of providing a communication circuit for transferring data between a processor system and an ex¬ ternal system

Technical Field

The invention relates to a method of providing a commu¬ nication circuit for transferring transmission data be¬ tween a processor system and an external system by means of the signals normally used to a read-only storage, such as a ROM or EPROM, wherein the data to be transfer— red are generated by means of the address bus of the processor system to the read—only storage in interaction with the CPU of the processor system and correspond to selected addresses on the address bus, said data in form of data on the address bus then being transmitted to the external system by a read control signal from the pro¬ cessor control circuit, preferably by means of an ad¬ dress control circuit connected to the data bus being made to trigger a data port connected to the external system.

Background Art

It is known to link a communication circuit to a ROM or EPROM. The reading of data from such a communication circuit usually is effected by a circuit substituting certain cells in the memory circuit with a read port for the communication circuit. When the processor addresses the address in question, the processor thus reads from the communication port instead of from the memory cir¬ cuit .

Writing data to the communication circuit is more trou- blesome, as the processor's ordinary write control sig¬ nal is not utilized in connection with a ROM or EPROM circuit. Writing is typically carried out by the proces¬ sor performing a normal read operation from selected ad¬ dresses in the EPROM or the ROM circuit. This operation implies that a special circuit transfers the address on the memory cell being read from, as write data to the communication circuit. Thus, by means of software the processor is made to read from an address corresponding to the value of the desired data to be written onto the communication circuit, confer US patent No. 4,691, 316 and US patent No. 5,047,926.

However, circuits made with said known methods are en¬ cumbered with a number of drawbacks. By the prosessor types in question sporadic addressing of read and write circuit to the communication system in the EPROM circuit may occur during the normal program flow. These sporadic addressings typically occur during the so—called idle time or dummy bus cycles, where the processor is engaged in carrying out internal calculations and does not uti¬ lize the external address and data busses. The processor can thus perform additional readings of the EPROM cir¬ cuit on the addresses which do not relate to the on¬ going program flow. These addressings may cause unwanted writings to communication ports, which again may cause faults in the communication to the external system.

These dummy bus cycles are usually undocumented from the processor manufacturer, which means that it in practice is extremely difficult to make programs providing a re¬ liable communication when an EPROM circuit is used to¬ gether with a communication circuit according to prior art.

Furthermore, most of the known communication circuits are constructed in such a manner that the read and write operations are irreversible. For instance when a data byte has been read from the communication circuit, the same data byte cannot be read again. Instead the next data byte is read. The problems of the prior art are thus further enlarged.

The object of the invention is to demonstrate how to combine prior art for reading and in particular writing of data to a communication circuit in a ROM or EPROM circuit having a circuit which functions as a key or trigger of a read or write operation, wherein a well- defined sequence of addressing operations is to be put through the processor, before a read or write operation may be carried out, and wherein a well—defined sequence of addressing operations may discontinue or stop an on¬ going addressing sequence.

The method according to the invention is characterised in that a write operation is carried out by a number of address bits being read onto the data port, the address bit pattern on address bus connected to the data port corresponding to the desired data value to be transfer- red, and that the part of the address area used for the write operations is controlled by means a trigger se¬ quence system which, prior to a write operation may have changed from a waite state to a ready state by the pro¬ cessor system reading from a specific address (a ready address) .

The trigger sequence system may thus prevent sporadic addressing sequences from performing undesired read or write operations on the communication circuit during the dummy cycles of the processors.

The trigger circuit may comprise a circuit implementing a sequence circuit by means of a state machine according to prior art combined with a circuit which by means of the address bus and the read control signal of the EPROM may define a number of operations or state transitions to be carried out by the state machine in a predeter¬ mined order, before a read or write operation may be triggered.

According to the invention, the addresses, which may trigger the individual state transitions In the state machine, may be selected so as to correspond to the me¬ mory addresses, wherein the processor instruction per— forming a read/write operation on the communication cir¬ cuit at a read operation in the address area of the EPROM is arranged.

A state machine having a number of states corresponding to the number of addresses required by the read instruc— tion and plus 1 plus the number of dummy cycles for the processor instruction used is enough to uniquely define that a read/write operation on the EPROM' s built-in com¬ munication circuit is valid and may be carried out.

Furthermore, the above method ensures that an on—going read/write operation is not stopped at an interrupt of the processor, as the processor always completes an on¬ going processor instruction before an interupt is ef¬ fected.

Moreover, the write circuit of prior art is encumbered with the drawback that the write area occupies such a large number of memory cells. To overcome this drawback, the address area in the read-only storage used for write operations may according to the invention be smaller than the address area which may be selected by the read control signal and the address mapping control, an ad¬ dress area being selected in the address area not used by the data port or the read control signal for write operations, said address area having a size correspond¬ ing to the size of the port. As a result, a better uti¬ lization of the address area is obtained.

At a 8—bit processor the write area thus typically occu— pies 2⁸ «= 256 memory cells, and at a 16-bit processor the writing of 8-bit data typically takes up 512 memory cells in the EPROM circuit. This is a definite drawback at the smaller processor types.

The above method is advantageous in that the memory cells in the write area may be utilized for normal pro¬ gram codes, as an addressing per se of these cells is not enough to trigger read/write operations on the com¬ munication circuit. In practice this means that the com¬ munication circuit typically only occupies two to four bytes in the EPROM circuit.

If it is assumed that a processor has an instruction for reading a memory, wherein the instruction consist of one byte and if it is assumed that the read operation is carried out in the two addressing cycles (instruction fetch and read/write operation) and that there are no dummy cycles, a sequence circuit with only two states will be enough to ensure a unique validation of a trig¬ gered read/write operation on the communication circuit.

At microprocessors with more complex instruction sequen- ces it may be necessary to select a more complex trigger sequence "key" to obtain a unique validation of a trig¬ gered state .

Even at use of a simple trigger sequence network with only two states a definite improvement of the communica— tion security is obtained compared to prior art cir¬ cuits . A method, whereby a circuit intended for write opera¬ tions is combined with a circuit intended for read ope¬ rations for the formation of a joint communication cir¬ cuit which can perform write as well as read operations, may be characterised in that a read control signal is used for selecting an address area for the joint circu¬ it, and the address mapping control divides said address area in such a manner that the circuits intended for write operations and the circuits intended for read ope— rations utilize different parts of the address area at the same time as the circuit intended for read operati¬ ons transfer data to the processor system via a data bus .

Brief Description of the Drawings

The invention is described in greater detail in the fol¬ lowing with reference to the accompanying drawings, in which

Fig. 1 shows typical line connections for a read—only storage in form of a ROM circuit,

Fig. 2 illustrates a communication circuit which can write onto an external data bus by means of addressing signals for the ROM circuit,

Fig. 3 illustrates a ROM circuit with a communication circuit for bidirectional communication with the exter— nal bus ,

Fig. 4 illustrates the bidirectional communication cir¬ cuit of Fig. 3 with a sequence circuit for obtaining a better utilization of the ROM circuit,

Fig. 5 is a state diagram for the sequence circuit, Fig. 6 is a detailed diagram of the write circuit of Fig. 2,

Fig. 7 is a detailed diagram of the circuit for bidirec¬ tional communication with the external bus of Fig. 3,

Fig. 8 is a detailed diagram of the communication cir¬ cuit with a sequence circuit, and

Fig. 9 illustrates the entire communication circuit be¬ tween a processor system and the external bus.

Best Mode for carrying out the invention

It is difficult to transfer data from a processor system to an external communication bus (EB) , as the signals from the CPU of the processor system used to control the writing of data are normally not accessible from a read¬ only storage in form of a ROM circuit in the processor system.

According to the invention, such a transfer of data is made possible, as an address bus (AB) of a socket for the ROM circuit - confer Fig. 2 - is used in interaction with the CPU of the processor system to form the data to be transferred onto the external communication bus (EB) . By means of an address mapping control (AMC) connected to the address bus (AB) of the processor system selected addresses on the address bus (AB) are able to trigger a write port (WO) , which then transmits the addresses in question onto the external communication bus (EB) con¬ nected therewith. If the write port (WP) comprises eight bits, 256 addresses are normally available. When writing data the CPU of the processor system carries out a read¬ ing of the address in the ROM circuit which after having been triggered via the address mapping control (AMC) is able to transmit the desired data onto the external bus (EB) via the write port (WP) . At the same time the CPU ignores any data on the data bus (DB) from the ROM cir¬ cuit.

As the ROM circuit is mounted on a socket, a bidirec¬ tional communication may furthermore be etablished be¬ tween the processor system and the external com¬ munication bus (EB).

A circuit enabling such a bidirectional communication is shown in Fig. 3. The circuit further comprises an ad¬ dress mapping control (AMC) connected with the address bus (AB) to the ROM circuit and receives the address signal from the ROM circuit. As also shown in Fig. 2 the address mapping control (AMC) is connected to a write port (WO) which is connected to the address bus (AB) and receives address signal therefrom. Moreover, a read port (RP) is able to receive data from the external bus (EB) and is connected to the data bus (DB) and may feed data to the latter. The read port (RP) is also controlled by the address mapping control (AMC) .

The address mapping control is a combination of the write circuit of Fig. 2 and a read circuit for transfer¬ ring data from the external bus (EB) onto the data bus (DB) , both circuits being activated via the address map— ping control (AMC) by addresses within the normal ad¬ dress area of the ROM circuit. Writing of data to the external data bus (EB) is performed as mentioned in con¬ nection with the write circuit in Fig. 2. Reading of data from the external bus (EB) is performed by means of a specific address on the address bus (AB) triggering the read port (RP) via the address mapping control (AMC) , said read port then transferring data from the external bus (EB) onto the data bus (DB). The address mapping control (AMC) disables the ROM circuit, concur¬ rently. The addresses in the ROM circuit which are not utilized for communication may be used as usual for sto¬ rage of software. The address area not used for writing of data to the external bus (EB) cannot be used in an¬ other way and may thus not be used to store software or data, whereby the ROM circuit is not utilized to an op¬ timum.

This problem may be rectified by constructing the commu— nication circuit in such a manner that the write port (WP) only may be triggered, if the CPU in advance has executed a program located on specific addresses.

Such a communication circuit is illustrated in Fig. 4 and corresponds to the one shown in Fig. 3 with the ad— dition of a trigger sequence system (TSS) connected to the address mapping control (AMC) and which has to be triggered via the address mapping control (AMC) by one or more addresses (ABA) on the address bus (AB) , before addresses in a selected address area (ABW) on the ad- dress bus (AB) may trigger the write port (WP),so that the addresses in question can be transmitted onto the external bus (EB) as data.

In its most simple form the trigger sequence system (TSS) has two states, namely a waite state (HV) and a ready state (AR) , as shown in the state diagram in Fig. 5. From the waite state (HV) a program address (ABA) is able to trigger a change of state to the ready state (AR) . An address in a selected area (ABW) is, however, only able to trigger a change of state to the waite state (HV) , whereby it is possible to carry out a write operation concurrently. As a result, the addresses in the selected address area (ABW) may be used not only to carry out a write operation but may also be used for software and data.

A change of state (ATO) , as shown with the dotted line in Fig. 5, exemplify that the sequence system (TSS) may be extended with a time—out function resetting the se— quence system (TSS) during start-up of the CPU or in case of errors, at which the read operation is discon¬ tinued.

The effect of the sequence system (TSS) may be optimised by deriving the trigger signal (ABA) on the bus (AB) from the address, from which the CPU receives a read instruction and by the signal (ABW) triggering a write operation deriving from one of the addresses being read during the execution of the read instruction, whereby the write operation cannot be divided by a CPU inter— rupt.

The sequence system (TSS) may be utilized in the same manner at reading from a read port (WP) .

The read port (RP) and the write port (WP) represent the interface to a universal communication circuit which may be extended with register ports, FIFO circuits, UART circuits or the like. The external bus (EB) represents any form of data transmission, either serial or parallel communication.

Figs. 6 to 9 illustrate the detailed structure of the mentioned circuits .

The write circuit

The write circuit shown in Fig. 6 discloses how a write operation is performed using the address and control signals for an EPROM. The circuit 74688 in the address mapping control (AMC) is an address comparator which is able to compare two binary addresses. It is used to se¬ lect an address area of 256 bytes (2⁸) to be used for write operations. The selection is made by the circuit comparing the most significant bits on the address bus (AB) . The lower eight bits are not included in the com¬ parison. At the reading of an address in the selected address area the lower eight bits of the bit are latched in the write port (WP) connected thereto. Writing of data to the port is then performed by reading the ad¬ dress, wherein the lower eight bits of the address bus (AB) (0-7) correspond to the desired data value to be transferred.

Both read control signals CS and OE are to be true in order to carry out a read operation. When CS is true, the comparator 74688 is enabled. A reading in the selec¬ ted address area ABW results in the output signal ABW from 74688 being true. The signals ABW and OE are fed to an OR gate 7432. When both input signals to the OR gate 7432 are true, the output signal WPC fed to the write port (WP) connected thereto is also true. The lower eight bits of the address bus (AB) are thus input to the write port (WP) under clock control. This data value may at a later stage be output to the external bus (EB) by supplying a read signal (ERD) to the write port (WP) .

Data from the processor system to the external system (EB) are thus transferred.

The bidirectional communication circuit

The possibility of transferring data from the external system (EB) to the processor system is also very benefi¬ cial. This is made possible by means of the circuit in Fig. 7 illustrating an EPROM with a circuit for bidirec- tional communication. The lowermost part of the circuit is a write circuit which is able to transfer data from the processor circuit to the external system (EB) . This circuit corresponds to the circuit described in connec— tion with Fig. 6. The uppermost part of the circuit is a read circuit able to transfer data from the external system (EB) to the processor system. The read circuit comprises a read port (RP) connected to an address map¬ ping control which is described in the following.

At the transfer of data from the external system (EB) to the processor system the read port (RP) is read in the same manner as a cell in the EPROM memory. The address mapping control then selects an address in the EPROM, implicating that the read port (RP) instead of the EPROM is activated by a read operation.

The address mapping control for the read port (RP) com¬ prises two comparators U3 and U4 of the type 74688. These comparators function jointly as one comparator with the exit signal ABR, said comparator selecting the address in the EPROM implicating that the read port (RP) is activated. The signal ABR from the comparator U3 and the read control signal OE are gated by means of an OR gate U1B of the type 7432. When both signals are true, the U1B signal RPC supplied from the OR gate is true. This signal is fed to the OC entry by the read port (RP) . The contents of the read port (RP) is thus read onto the data bus (DB) . In order to avoid conflicts be¬ tween the EPROM and the read port RP , the EPROM is dis¬ abled during the reading from the read port (RP) by means of an inverter U5A of the type 7404 and an OR gate U1C of the type 7432. The signal ABR is inverted by the inverter U5A so that the value false is fed to the entry of the OR gate U1C during an output from the read port (RP) . In order to indicate that it is ready for a read operation, the read control signal CS is thus prevented from activating the CE terminal for the EPROM, whereby the EPROM remains passive during reading of data from the read port (RP) .

The read circuit which in practice is a read port in the EPROM' s address area is prior art. The novel feature is that the read circuit is combined with a write circuit.

An extended address mapping control

The write circuits shown in Figs. 6 and 7 utilize a me- mory area in the EPROM on 256 bytes for write opera¬ tions. The 256 bytes cannot immediately be used for data, as an unintended write operation is performed, if it is attempted to read data in this memory area.

The memory area used for write operations may, however, also be used for data by means of the circuit shown in Fig. 8 by means of a trigger sequence system with a waite state (HV) and a ready state (AR) . The circuit is to be in the ready state, before reading of data in the write area results in a write operation. If the sequence system is in its waite state (HV) , it is, however, pos¬ sible to use and read the data bytes in the write area in a usual manner without effecting a write operation.

In its most simple form the sequence system of Fig. 8 comprises a D-flip-flop U3A of the type 7474 and NAND gates U2A and U2B of the type 7400. The waite state and the ready state are specified as 1 and 0 on the Q exit of the flip-flop U3A. The Q exit of the U3A is connected with an OR gate U1B , the exit of which is connected with an additional OR gate .1A.

A write operation is performed, when a write control signal WPC supplied from the OR gate U1A becomes true. Together the OR gates UlA and U1B form a 3 input OR gate effecting that the WPC signal is only true, if the sig¬ nal ABW and the signal OE are true and the sequence sy— stem U3A is in its ready state at the same time.

A couple of comparators U5 and U4 of the 74688 form one comparator which may select an address in EPROM. A read¬ ing of this address results in the sequence system U3A changing from a waite state to a ready state in that the the signal ABA from U4 becomes true at reading of the ready address, whereby the value "1" is supplied to the entry of the flip-flop U3A via the NAND gate U2A. The signal is read onto the flip—flop U3A by the read con¬ trol signal upon completion of the read operation. The flip—flop U3A then changes to a ready state. The flip- flop's Q exit is let back to the D entry of the flip- flop U3A via the AND gates U2B and U2A so that it re¬ mains in the ready state, until a subsequent write ope¬ ration is carried out.

At reading of the write area during the subsequent write operation, the signals ABW and OE become true. As the Q exit of the flip—flop U3A also is true, the requirements for carrying out a write operation are achieved and the write control signal WPC become true. At the same time the AWB signal effects that the value "0" Is shown on the entry to the flip—flop U3A. This value is clocked into the flip—flop U3A by the OE upon completion of the write operation, whereby the flip—flop U3A returns to the waite state.

The sequence system may, if necessary, be extended with a time—out circuit, which may be used in case that pro¬ cessor system Is reset in between the ready state and a write operation. The sequence system is then in an dis— advantageous state and may thus be reset by the time—out circuit (by means of a signal ATO) .

The last circuit (Fig. 9) shown how EPROM forms part of a ordinary circuit. A processor system is illustrated comprising a CPU, a EPROM and a RAM and an address de¬ coder generating the selection signals CS to EPROM and RAM, respectively.

The circuit is a simple processor system. To the right the CPU of the processor system is shown. Furthermore, the two memories, an EPROM and a RAM are shown. They are used for storing software and data, respectively, which for instance are used to control a manufacturing pro¬ cess. The CPU of the processor system carry out opera¬ tions effecting that the processor system obtains the desired functions. The EPROM is mounted on a socket and provided with an external circuit, from where the ad¬ dress bus AB and the two control wires CS and OE initi¬ ate. The dotted space to the left of the processor sys¬ tem represent a cable connection or distance to the mac- hine being communicated to, for instance a PC. The two blocks represent a standard method for providing an in¬ terface for a PC bus .

In order to make the circuit as simple as possible, a write port and a read port have been provided. The ports may as an alternative be an UART, whereby a serial com¬ munication may be carried out directly to the communica¬ tion port (COM port) on a PC.

The invention is described with reference to a preferred embodiment. Many modifications may, however, be per- formed without thereby deviating from the scope of the invention.

Claims

1. A method of providing a communication circuit for transferring transmission data between a processor sy¬ stem and an external system (EB) by means of the signals normally used to a read—only storage, such as a ROM or EPROM, wherein the data to be transferred are generated by means of the address bus (AB) of the processor system to the read-only storage in interaction with the CPU of the processor system and correspond to selected addres— ses on the address bus (AB) , said data in form of ad¬ dresses on the address bus (AB) then being transmitted to the external system (EB) by a read control signal (RC) from the processor system, preferably by means of an address control circuit (AMC) connected to the ad— dress bus (AB) being made to trigger a data port con¬ nected to the external system (EB) , c h a r a c t e r i— s e d in that a write operation is carried out by a number of address bits being read onto the data port, the address bit pattern on address bus (AB) connected to the data port corresponding to the desired data value to be transferred, and in that the part of the address area used for the write operations Is controlled by means a trigger sequence system (TSS) which prior to a write operation may have changed from a waite state (HV) to a ready state (AR) by having the processor system read from a specific address (a ready address) .

2. A method as claimed In claim 1, c h a r a c t e ¬ r i s e d in that the address area in the read—only storage used for write operations is smaller than the address area which may be selected by the read control signal (RC) and by the address control circuit (AMC), an address area being selected in the address area not used by the data port or the read control signal (RC) for write operations, said address area having a size cor—

3. A method as claimed in claim 2, whereby a circuit intended for write operations is combined with a circuit intended for read operations for the formation of a joint communication circuit which is able to perform write as well as read operations , c h a r a c t e r i ¬ s e d in that a read control signal (RC) is used for selecting an address area for the joint circuit, the ad¬ dress control circuit in form of an address mapping con¬ trol (AMC) dividing said address area in such a manner that the circuits intended for write operations and the circuits intended for read operations utilize different parts of the address area at the same time as the spe¬ cial circuit for read operations transfers data to the processor system via a data bus (DB) .

4. A method as claimed in claim 1, c h a r a c t e ¬ r i s e d in that the trigger sequence system (TSS) via the address mapping control (AMC) is triggered by one or more addresses on the address bus (AB) prior to the se¬ lected address (AB) triggers the write port (WP) so that said addresses may be transmitted via the write port (WP) onto the external bus (EB) as data.

5. A method as claimed in claim 4, c h a r a c t e ¬ r i s e d in that the trigger sequence system (TSS) used has two states , namely a ready state (AR) in which reading of data from a write area in the read-only sto¬ rage ensures that a write operation may be carried out, and a waite state (HV) in which reading of data from the write area ensures that a write operation cannot be per¬ formed.

6. A method as claimed in claim 4 or 5, c h a r a c ¬ t e r i s e d in that the trigger sequence system (TSS) comprises a D-flip-flop.