WO1993009491A1

WO1993009491A1 - An address generator

Info

Publication number: WO1993009491A1
Application number: PCT/AU1992/000556
Authority: WO
Inventors: David Sydney Fensom; Craig Charles Pullin
Original assignee: Commonwealth Of Australia
Priority date: 1991-11-08
Filing date: 1992-10-20
Publication date: 1993-05-13

Abstract

An address generator (2) comprising means (10, 12, 14) for generating operand signals, processing means (4, 6, 8) for forming an address signal on the basis of the operand signals, and means (16) for accessing data on the basis of one of the operand signals and supplying the accessed data to the processing means (4, 6, 8), in substitution for said one of the operand signals, to form an address signal.

Description

AN ADDRESS GENERATOR The present invention relates to an address generator. More specifically, but not exclusively, it relates to an address generator which is able to perform vector addressing of a three dimensional vector space.

Most address generators are simple devices which increment a current address and the result is normally passed to a memory device. Consecutive addresses are generated until an external device wishes to jump to a random location in memory. The address corresponding to the random location is provided by the external device, or another device, to access the location, and is also supplied to the address generator so consecutive addresses are then generated from the new current address. This form of linear addressing may be appropriate for a number of applications but it is relatively limited.

In a number of situations it is desirable to be able to access data on a more flexible basis to obtain information of interest. For example, impulse response data obtained by a synthetic aperture radar, and which relates to a particular target on the earth's surface, is stored in address locations which correspond to a Range Cell Migration Track, and it is advantageous to be able to generate addresses which follow the track and can efficiently access the target data. It is also advantageous to be able to generate addresses which can address a memory space by moving, as desired, a two dimensional address matrix or a vector address through the memory space.

In accordance with the present invention there is provided an address generator comprising means for generating operand signals, processing means for forming an address signal on the basis of said operand signals, and means for accessing data on the basis of one of said operand signals and supplying the accessed data to said processing means, in substitution for said one of said operand signals, to form an address signal. Preferabiy said address generator includes control means for controlling said generating, processing and accessing means and for selecting said one of said operand signals to be used as an index to said data by said accessing means. Preferably said generating means generates said operand signals simultaneously on a sequential basis in accordance with the following:

i = initial i

For 1 to size i

j = initial j

For 1 to size j

k = initial k

For 1 to size k

address = basejoffset + (i + j + k)

k = k + step k

j = j + step j

i = i + step i

where k is the value represented by a first operand signal, j is the value represented by a second operand signal, i is the value represented by a third operand signal, and base_offset, and the initial, step and size values are predetermined integers represented by data stored, in use, in said generator, and address is the value represented by the address signal formed by said processing means.

Preferably said processing means includes modulo means for performing a 2ⁿ or 2⁽ⁿ⁺¹⁾ + 2ⁿ, modulo operation on the sum, (k + j + i), of said operand signals, n being a positive integer.

Preferably said generating means is adapted to perform a bit reversal operation on said first operand signal such that said address signal is able to access data in a bit reversed order, said first operand signal comprising n bits of data and said bit reversal operation being bit k(m) becomes bit k ((n-1) - m) for m = 0 to (n-1).

Preferably said generating means includes means for generating in parallel sets of said operand signals and means for selectively outputting one of said sets.

Preferably said processing means includes pipeline processing stages for combining two of said operand signals to form an intermediate signal, for combining said intermediate signal and the remaining operand signal to form a sum signal and for performing said modulo operation on said sum signal and adding a base_offset signal representative of said base_offset.

A preferred embodiment of the present is hereinafter described, by way of example only, with reference to the accompanying drawings, wherein:

Figure 1 is a block diagram of a preferred embodiment of an address generator according to the present invention;

Figure 2 is a block diagram of a loop vector generator of the address generator; Figure 3 is a block diagram illustrating connection of the address generator to external memory;

Figure 4 is a timing diagram of signals used in writing data to a passive memory connected to the address generator;

Figure 5 is a timing diagram of signals used in reading data from an active memory connected to the address generator;

Figure 6 is a block diagram of a third pipeline processing stage of the address generator;

Figure 7 is a block diagram of a modulo circuit of the third pipeline stage; Figure 8 is a timing diagram of signals received and produced by the pipeline stages of the generator;

Figures 9 to 11 are snapshots of data processed over nine cycles of the address generator;

Figure 12 is a circuit diagram of the address generator, 12a being the upper left comer, 12b the upper right comer, 12c the bottom left comer and 12d the bottom right comer;

Figure 13 is a diagram illustrating operation of a synthetic aperture radar;

Figure 14 is a diagram illustrating the form of data received by the synthetic aperture radar; Figure 15 is a diagram of the arrangement of response data from the synthetic aperture radar in memory;

Figure 16 is a diagram of a rotating buffer holding the response data;

Figure 17 is a diagram illustrating the relationship between an RCM track and stored filter kernel vectors;

Figure 18 is a diagram illustrating movement of an address matrix through a memory space; and

Figure 19 is a diagram of Fast Fourier Transform processor. An address generator 2, as shown in Figure 1, includes three pipeline processing stages 4, 6 and 8, two loop vector generators 10 and 12, a multiplexer 14 a memory interface 16, and a pipeline controller 18. Control of the circuits 10 to 16 of the generator 2 is effected by the pipeline controller 18 using a control bus 20 which is connected to all of the circuits 10 to 16. The generator 2 is configured to generate a 20 bit address on an output terminal 22 at the end of each clock cycle, which is approximately 100 ns. The address is generated in accordance with the following algorithm:

i = initial i

For 1 to size i

j = initial j

For 1 to size j

k = initial k

For 1 to size k

address = base_offset + (i + j + k)

k = k + step k

j = j + step j

i = i + step i

In C language notation, with the size values in two complement's form, the algorithm for 20 bit vectors is as follows:

loop_i = init_i;

for( count_i = size_i; count_i <= Oxfffff; count_i++ ) {

loop_j = init_j;

for( count_j = size_j; count_j <= Oxfffff; count_j++ )

{

loop_k = init_k;

for( count_k = size_k; count_k <= Oxfffff; count_k++ )

{

address = base_offset + loop_i + loop_j + loop_k; loop_k = loop_k + step_k;

}

loop_j = loop_j + step_j;

}

loop_i = loop_i + step_i;

}

The loop values i, j and k are represented by 20 bit loop vectors which are generated sequentially by the loop vector generators 10 and 12. One loop vector generator 10 provides a set of loop vectors for one address stream and the other loop vector generator 12 provides a set of loop vectors for a second address stream. The state of a select stream input (SSTR) 24 of the pipeline controller 18 determines which address stream is to be processed and the controller 18 provides appropriate control signals to the corresponding loop vector generator 10 or 12 to issue a set of loop vectors, simultaneously. The outputs of the generators 10 and 12 are inputted to the multiplexer 14, and the controller 18 selects, in accordance with the chosen address stream, which set of outputs are to be passed from the multiplexer 14 to the first pipeline stage 4 and the interface 16.

A loop vector generator 10, 12, as shown in Figure 2, provides three loop vectors i, j and k, in accordance with the algorithm recited above, during each clock pulse, which is provided on a clock input 26 of the pipeline controller 18. The generator 10, 12 includes an i register circuit 28, a j register circuit 30, and a k register circuit 32. The register circuits 28, 30 and 32 are the same, and each include a pair of initial value registers 34, a pair of step registers 36 and a pair of size registers 38. One register of each pair 34, 36 and 38 is for an active address sequence of the stream and the other register of each pair is for a passive address sequence of the stream. The active address sequence of a stream is the sequence which is to be processed by the pipeline stages 4, 6 and 8 to produce an output address. Data selectors 40 are connected to the outputs of the register pairs 34, 36 and 38 to select, in response to signals from the controller 18, which register corresponds to the active address sequence. In the i register circuit 28, the initial value register pair 38 stores two 20 bit initial i vectors, one of which is selected as relating to the active sequence by the data selector 40 and is outputted to an accumulator register 42 via a second data selector 44. The contents of the accumulator register 42 provides an output on an i vector output bus 46, which is sent to the multiplexer 14 during each clock pulse with the output on j vector and k vector output buses 48 and 50. The step register pair 36 stores two 20 bit step i vectors and the one which corresponds to the active address sequence is passed by a data selector 40 to a multiplexer 52. The contents of the accumulator 42 is also received by the multiplexer 52. When the i loop is to be advanced, in accordance with the algorithm, the multiplexer 52 selects the inputs from the i register circuit 28 and passes them to an adder circuit 54, where the signals are summed. The result of the summation is passed by the adder as an output signal to the data selector 44 and then stored in the accumulator register 42. The updated contents of the accumulator register 42 is placed on the i bus 46 as the next i loop vector. The size value register pair 38 stores two size i vectors for both the passive and active address sequences, the contents of the register corresponding to the active sequence being selected by a data selector 40 and stored in a size value counter 56. The size value vectors are stored in two's complement form and the counter 56 is incremented whenever the contents of the accumulator 42 is changed by the output of the adder 54. When the counter is incremented beyond its full count (i.e. from FFFFF to 00000 hex), processing for the address stream of the active address sequence has been completed.

If desired, the step vector used may be set to zero so that the adder 54 passes the same loop vector to the accumulator 42. The counter 56 is still incremented and the initial loop vector is outputted from the accumulator 42 for each address in the sequence.

For the j and k register circuits 30 and 32, when the size value counter 56 goes beyond its full count, the counter is re-initialised by receiving the contents of the corresponding active address sequence size value register 38, and the accumulator register 42 and the size value counter 56 of the next outer loop vector, i or j, is advanced, in accordance with the algorithm. A carry output of each size value counter 56 of the register circuits 28, 30 and 32 is used to generate loop status data.

The contents of the accumulator register 42 and the active address sequence step register 36 of the j and k register circuits 30 and 32 is also passed to the multiplexer 52 of the generator 10, 12, as shown in Figure 2. In accordance with the algorithm, the multiplexer 52 passes the inputs from the k register circuit 32 to the adder each clock cycle, until the size value counter 56 of the k register circuit 32 passes its full count. Then k register circuit 32 is re-initialised and the multiplexer 52 passes the inputs from the j register circuit on the next clock cycle. Thereafter submission of the k register circuit inputs resumes. The inputs from the i register circuit 28 are only passed to the adder when the size value counter 56 of the j register circuit 30 exceeds its full count. The multiplexer 52 passes selected inputs to the adder 54 at the beginning of each clock cycle and a new loop vector set, i, j and k, is generated within 30 ns of the start of a clock cycle in which an address stream is advanced. The output of the k register circuit 32 is placed on the k vector bus 50 via a bit reverse circuit 58. When disabled, the bit reverse circuit 58 passes the contents of the k vector accumulator register 42 unaltered, but when enabled the circuit 58 reverses the bit order of the vector received from the accumulator register 42. For each 20 bit vector received the bit reverse circuit 58, when activated, outputs bit k(m) as bit k (19 - m) for m = 0 to 19, on the k vector bus 50. With the k register circuit 32, the bit reverse circuit 58 can be used to achieve bit reversal of a vector of n bits, where n is less than 20, by enabling the bit reverse circuit 58, setting the initial k value register to zero, setting the k size value counter to -2ⁿ, and setting the step k register 36 to 2^(20-n). All of the address vectors placed on the k vector bus 50, which can be used as the basis for a bit reversed output from the generator 2, are then reversed according to the following:

bit k(m) = bit k((n-1) - m), for m = 0 to (n-1).

The register pairs 34, 36 and 38 of the i, j and k register circuits 28, 30 and 32 are set, for both the active and passive address sequence of each stream, before sequential loop vectors are generated and the data selectors 40 and 44 and multiplexer 52 are controlled by the pipeline controller 18 to extract the correct sequence and the correct vectors according to the algorithm. By setting the initial, step and size values, as desired, for each of the three register circuits 28, 30 and 32, the bit width of the sequential loop vectors can be varied and the number of loop vectors employed in generating an address stream can also be varied.

The multiplexer 14 connected to the generators 10 and 12 selectively passes two loop vectors of an address stream to the first pipeline stage 4, as vectors A and B, and passes the third vector, as vector C, to the interface 16. In accordance with control signals from the controller 18, vector C may be the i, j or k loop vector of the stream selected by the multiplexer 14. Vector C may be passed directly by the interface 16 to the first pipeline stage 4 or alternatively the vector C can be used as an address, or index, to access an external memory, or look-up table (LUT), by placing the vector on an output address bus 60, as- shown in Figures 1 and 3. Data retrieved from the external memory is received by the interface 16 on a data bus 62 and passed to the first pipeline stage 4 as the third loop vector LUT(C) instead of the vector C. The ability to substitute one of the loop vectors for a predetermined vector stored in an external memory is particularly advantageous, as described hereinafter, because it enables the addresses generated by the address generator 2 to deviate from a sequential path and instead follow a path dictated by the data stored in the external memory.

The address generator 2 is configured to address two external memory circuits 64 and 66 on alternate half clock cycles, one being designated an active memory from which data is read, and the other being designated a passive memory to which data can be written. The interface 16 is therefore able to address one memory 64 or 66 whilst the other memory 66 or 64 is having data written to or read from it. Assuming memory 64 is currently designated the active memory and memory 66 the passive memory, the interface 16 latches the loop vector C placed on the address bus 60 in a first address register 68 in response to an address strobe output (ASTRB(0)) 70 from the interface 16. The interface 16 provides chip select enable (LUTCS(0)) and read/write enable (LUTWE(0)) signals 72 and 74 to the active memory 64 and the contents of the first address register 68 is used to address the active memory 64. Data is read from the active memory 64, in accordance with the state of the read/write enable signal 74, and placed on the data bus input 62 to the interface 16. To write data to the passive memory 66 an initial access address is written into a write address register in the interface 16. Access to all of the registers in the address generator 2 is achieved using a chip select input 80, a read/write enable input 82, an address bus 84, which selects the desired register, and a data bus 86 which is connected to all of the internal registers. After setting the write address register, the data to be written is sent on the data bus 86 to a data sink register 88. On receiving an address on the address bus 84 which corresponds to the data sink register 88, the address generator 2 issues a data strobe output (DSTRB) 90 to latch the data in the register 88. At the same time the address from the write address register is output on the address bus 60 and latched in a second address register 92 in accordance with a second address strobe output (ASTRB(1)) 94. The passive memory 66 is then write enabled by a second chip select output (LUTCS(l)) 96 and a second read/write enable output (LUTWE(1)) 98 and the data held in the sink register 88 is written into the passive memory at the location corresponding to the contents of the second address register 92. A timing diagram illustrating the timing of the control signals for a write access to the passive memory 66 is illustrated in Figure 4. The address of the write address register is IE and the address of the data sink register is IF. The write address register is incremented after each cycle data is written to the passive memory 66. A timing diagram of the control signals employed during a read access to the active memory 64 is illustrated in Figure 5 which specifically relates to substitution of the j loop vector with data held in the active memory 64. Selecting which of the two external memories 64 and 66 is the passive or active memory is achieved by providing the appropriate signals on the address strobe, chip select and read/write enable outputs 70, 74 and 94 to 98, in accordance with a flag held in a control register of the pipeline controller 18. To avoid bus contention the active memory must be disabled before performing an active to passive switch and vice versa.

The first pipeline stage 4 of the generator 2 receives vectors A and B, which are loop vectors k and j if an external memory access is not required using the interface 16, and are placed at the inputs of an adder in the stage 4 within 50 ns of the start of a clock cycle. A sum is generated by the adder within 40 ns and is placed in one of two output registers of the stage 4, depending on which address stream is being processed according to the select stream input 24. Two registers are also provided, one for each address stream, for storing data, LUT(C), read from the active external memory 64 and provided by the interface 16. If an external memory access is not required, loop vector i is sent to the first stage 4 and stored in one of the two registers. The sum and loop vector i or LUT(C) stored in the output registers are passed to the second pipeline stage 6 in accordance with the state of an advance address stream input (ADVB) 25 of the pipeline controller 18. The advance address stream signal instructs the pipeline controller 18 to place appropriate control signals on the control bus 20 to cause the selected loop generator 10 or 12 to output the next loop vectors to the multiplexer 14 and also causes the pipeline processing stages 4, 6 and 8 to process the signals present on their inputs to advance the address stream. The second pipeline processing stage 6 includes an adder which sums the loop vector i or LUT(C) and the sum outputted by the first pipeline stage 4 and places the result in one of two output registers, depending on which address stream is being processed. The contents of the output register of the second stage 6 is inputted to the third and final processing stage 8 which, if required, performs a modulo operation on the sum and then adds the contents of a base_offset register in accordance with the algorithm recited on page 5.

The third pipeline stage 8, as shown in Figure 6, includes a modulo circuit 100 which is able to perform a modulo operation, when enabled, on the sum vector received on the input 102 of the third stage 8. The modulo operation performed is dependent on the contents of a buffer-length register 102 which holds the representation of the buffer-length and may be 2ⁿ, for n = 0 to 20, or 2⁽ⁿ⁺¹⁾ + 2ⁿ, for n = 0 to 18, n being an integer. For a buffer-length of 2¹⁹, this would restrict the addresses generated to half the address space of a 2²⁰ memory space. Similarly, a 2¹⁹ + 2¹⁸ buffer-length would restrict the addresses generated to 75% of a 2²⁰ memory space. The modulo process is completed within 35 ns and the output is passed to an adder 106 where it is summed with the contents of a base_offset register 108. Addition of a base offset stored in the register 108 enables the address outputted by the modulo circuit 100 to be offset to a desired memory location. The output of the adder 106 is latched into one of two output registers 110, depending on which address stream is being processed. Addresses are sequentially output from the output registers 110 on the output bus 22 of the generator 2. Buffer-length and base_offset registers 104 and 108 are provided for each address stream and the final processing stage 8 also includes latches between the adder 106 and the output registers 110 which can be used to hold the first address of a passive address sequence while the final address of an active address sequence is held in an output register 110. The modulo circuit 100 performs a 2ⁿ modulo operation using a basic masking process where an AND operation is performed between the address vector on the input bus 102 and a mask vector having upper low bits corresponding to the bits to be discarded and high bits in the lower bit locations. For example, if the buffer length is 2¹⁵ the upper 5 bits of the 20 bit mask are low and the remaining bits are high. The 2⁽ⁿ⁺¹⁾ + 2' modulo operation although more complicated is still relatively simple to implement and is advantageous as it provides a greater degree of flexibility with respect to the memory space size which can be selected for restricted addressing by the generator 2. The following set of equations illustrate how the modulo operation can be broken down into two masking operations, a bit shift operation and a relatively simple modulo 3 operation. X mod (1.5 x 2^m)

The second sum expression in the final line of the equations represents a masking operation to obtain the upper m-1 to N-1 bits of the input vector on which the operation is performed. A simple modulo 3 operation is then performed on the upper bits and the multiplication term outside the brackets represents a bit shift, to an upper m-1 bit location, of the result of the modulo 3 operation. The first sum term represents a mask operation to obtain the low 0 to m-2 bits of the input vector and the expression is completed by placing the results of the modulo 3 operation as the most significant bits ahead of the low bits obtained by the second masking operation. To perform the 2ⁿ⁺¹ + 2ⁿ modulo operation the modulo circuit 100 includes, as shown in Figure 7, a first mask circuit 112 for extracting the lower n bits of the operand vector received on the input 102 of the circuit 100. A second mask circuit 114 simultaneously extracts the remaining upper bits of the operand vector. Both mask circuits perform an AND operation with low bits against the unwanted bits and high bits against the bits desired. The output of the first mask circuit 112 is provided to a bit combine circuit 116 and the output of the second mask circuit 114 is inputted to a standard modulo 3 circuit 118. The modulo 3 circuit is formed using combinatorial logic and the result of the operation is represented by 2 bits output to a bit shift circuit 120. The bit shift circuit 120 moves the received 2 bits to the n+1 and n+2 locations, with the remaining n bits being low and outputs the result to the bit combine circuit 116. The bit combine circuit 116 produces an output 122 which includes the n bits from the first mask circuit 112 and the 2 bits from the modulo 3 circuit 118 as the upper bits, n+1 and n+2.

To initialise the address generator 2, an external device defines an address sequence by writing loop parameters and control data to registers of the generator 2.

A complete parameter set for an address sequence defines the three loop vectors, modulo buffer-length and base_offset for both address streams, and control data held in the controller 18 defines the way in which the loop vectors are combined for each address stream to generate the address sequence. A reduced parameter set can be written if fewer than three loops are required to define an address stream, or if only one address stream is required. The control data indicates how many loop vectors and streams are defined so an end of sequence state can be determined correctly. An active address sequence can be repeated, if desired, or the passive address sequence run up behind the active address sequence, in accordance with control data held in the passive and active sequence control registers included in the controller 18. The bit map for each of the passive and active sequence control registers is as follows in

Tables 1 to 3.

Processing of the passive address sequence begins after it has been defined and a passive address sequence defined control signal is issued. The passive address sequence may run up directly behind the active address sequence so the first address of the passive address sequence is processed by the pipeline stages 4, 6 and 8 after each stage 4, 6 and 8 has completed its part in the processing of the last address of the active address sequence. In other words, as the processing resources of one of the stages 4, 6 and 8 is released, it is utilised for calculating the first address of the passive address sequence. This "hot start" of the passive address sequence enables the resources of the address generator 2 to be fully utilised. Alternatively, a "cold start" may occur where the resources of the pipeline processing stages 4, 6 and 8 are fully released prior to the beginning processing of the next address sequence or a "warm start" may occur where the resources of the stages 4, 6 and 8 are partially released before processing of the passive address sequence is begun. A "cold start" is forced if the passive address sequence wishes to use a different active memory 64 to the active sequence. Generation of the sequences is controlled by start of sequence, end of sequence, passive sequence defined, start next sequence, advance address stream, and select address stream signals issued by the controller 18 in accordance with external inputs, internal status signals and control data written into the control registers. The passive address sequence is run up in the pipeline processing stages 4, 6 and 8 after the passive sequence defined signal is issued and the start of sequence status signal is issued when the run up is complete. The start next sequence control signal may then be asserted to cause the passive address sequence to become active, and output of the new sequence to commence. The select address stream signal selects from which address stream an address is to be outputted and the advance address stream signal indicates whether that stream is to be advanced. The end of sequence signal is issued after an abort signal is received by the generator 2 or after the final address of the active sequence has been outputted by the generator 2. The generator 2 includes a status register which holds information concerning the state of the generators 10 and 12, and the pipeline stages 4, 6 and 8 in response to status signals received therefrom. Figure 8 is a timing diagram which illustrates how the loop vectors are processed through the pipeline stages when the i loop vector is used as an index to the active loop-up table (ALUT) 64 connected to the interface 16. Figures 9, 10 and 11 illustrate an example of data produced by the generators 10 and 12 and the pipeline stages 4, 6 and 8 during nine consecutive cycles as dictated by the state of the select stream and advance stream signals issued.

The address generator 2, as illustrated in Figure 12, has been designed using standard logic gate arrays so the design can be processed by VLSI standard cell design software to produce a VLSI layout, from which the generator 2 can be fabricated as a single semiconductor chip. The controller 18 is implemented by two functional blocks CTST 130 and CGEN 132. The address generator 2 can be implemented in a number of ways and the circuit illustrated in Figure 2 is only one such implementation. A skilled addressee would appreciate that the basic components of the address generator described with reference to Figures 1 to 11 are standard and could be configured as desired.

The address generator 2 is particularly useful for accessing data obtained by a synthetic aperture radar and forwarding the data to signal processing circuits, such as a finite impulse response (FIR) filter. The European Space Agency's ERS-1 synthetic aperture radar 150, as shown in Figure 13, is designed to transmit continuous chirp pulses which illuminate a patch 151 on the ground 152 to an extent of 3 dB relative to the original pulses. The patch, or 3 dB footprint is approximately 110 km in range and 4 km in azimuth. The radar 150 emits pulses of 37.1 μs in length and samples the echo for 299 μs corresponding to the swath of 100 km. This produces a range line of 5616 complex samples per transmitted pulse. For an isolated point target 154 on the ground 152, as shown in Figure 14, the echo from the target 154 for each pulse is distributed in time over 704 samples, along the range lines 156. As the antenna of the radar 150 moves along the path 158 the target 154 moves through the footprint 151 so as to enter and leave the real aperture 160 of the antenna. Therefore following the time axis 162, over which echo samples are obtained, the distance between the target and the boresight 164 decreases to a minimum and then increases as the target 154 leaves the aperture 160 so that the locus of the samples relevant to the target along the range lines 156 follows a curve 166 known as the Range Cell Migration (RCM) track. The echo samples obtained by the radar 150 are stored in memory 170 as they are received, as shown in Figure 15, where the crosspoints of the grid 172 represent the storage locations of the memory 170. The vertical lines 174 of the grid 172 correspond to the range lines 156, and samples obtained along a range line 156 are stored in memory locations having an address spacing therebetween of d, which corresponds to the spacing between the horizontal lines 176 of the grid 172. For example, the samples stored along the range axis 178 may be held in memory location zero 180, location d 182, location 2d 184 and location 3d 186, etc. Following the movement of the radar 150, samples of the next range line 156 are stored at memory location one 188, memory location d+1 190, memory location 2d+l 192 and memory location 3d+l 193, etc. This continues for movement of the radar 150 moves along the azimuth. Samples are received along a time axis 196. Figure 15 illustrates the stored range samples 198, in boxes, which relate to a target of interest 154 and the Range Cell Migration Track 166 for the target illustrates how the samples 198 follow the curve 166.

To obtain data representative of the target 154 along a synthetic antenna aperture, of the same length as the width of the footprint 151, each of the range samples 198 have to be accessed correctly, according to the RCM 166, from the memory 170 and compressed into a single sample. The samples 198 are weighted appropriately so that the single sample corresponds to one which would lie on the locus 166. The samples are compressed in this manner by accessing them according to the RCM, which is known, and applying them to an FIR filter with the appropriate filter kernel for each sample vector 198. The RCM 166 is determined from the known position of the target and the orbit of the radar 150.

By storing data corresponding to the trajectory of the RCM 166 in the active memory 64 connected to the address generator 2, as shown in Figure 3, the address generator 2 can be used to generate addresses to correctly access the relevant data vectors 198 for transmittal to an FIR filter. The initial k vector is set to zero, the step k vector is set to d, corresponding to the memory spacing between the samples of the vectors 198, and the size k vector is set to four corresponding to the number of samples in each vector 198. The j loop vector parameters are set to generate consecutive j vectors, which are used to access the active memory 64 to obtain the data corresponding to the RCM curve 166. The RCM data shifts the addresses generated to the first location 200 of each sample vector 198. With reference to the example illustrated in Figure 15, the RCM data obtained by the j vector would be 0, 1, 3, 4, 5, and then after the fifth vector 202 would jump to d+6, d+7 and d+8, and then after the eight vector 204 would jump to 2d+9, etc. to follow the RCM 166. The i loop vector parameters are set to allow the k and j loop vectors to access a data set corresponding to one RCM curve 166, and then a succeeding i vector is generated to jump to generation of addresses which are used to access another data set of vectors corresponding to another RCM curve 206, as shown in Figure 16. Therefore using the j loop vector as an index to the external memory 64 enables addresses to be generated to access vectors 198 along a series of curves 166, 206. The vector window 198 can be moved through a memory space 170 according, to any curves predefined by data stored in the active memory 64.

The modulo operation facility provided by the address generator 2 enables addresses to be generated for accessing a rotating buffer memory. For example, as shown in Figure 16, vector sets stored in upper address locations of the memory 170 and corresponding to curves 208 and 210 may have the vectors corresponding to the upper parts of the curves stored in lower address locations to fully utilise the memory space 170. The buffer-length register 104 is set corresponding to the size of the memory space 170 so that addresses generated to access the vectors corresponding to the upper ends 212 of the curves 210 and 208 are converted to the appropriate lower addresses to access the vectors at the bottom locations 214 of the memory space 170.

The filter kernels for each sample vector 198 comprise a kernel vector of four respective weights for the four samples. A set of kernel vectors are stored in memory and the address generator 2 is used to access the correct kernel vector for each sample 198 of an RCM curve 166 corresponding to the position of the samples of the vector 198 relative to the curve 166. The relative position is determined by interpolating the position of the RCM curve 166 with respect to the middle two samples 220 and 222 of a sample vector 198, as shown in Figures 15 and 17. Again, the j vector is used to access the active memory 64 to extract a value which represents the correct kernel vector to be accessed. With reference to the example illustrated in Figure 17 there are 15 kernel vectors assigned to 15 respective positions 224 between the middle two sample points 220 and 222, and the j vector is used to access data which would cause generation of an address to access the sixth kernel vector 226, as the RCM 166 passes through a position which is located approximately 40% of the entire distance between the points 222 and 220 from the bottom point 222. Storing the kernel vectors in address locations which increase in value from 0 to 15 corresponding to 0 to 100% of the distance from the second sample 222 would mean the addresses generated by the generator 2 would gradually increase in value from that corresponding to the first vector 201 illustrated in Figure 15 until the kernel corresponding to the fifth vector

202 is accessed and then data accessed by the j vector would ensure that the next address generated jumps down to a low address value for the kernel of the sixth vector

203 so as to follow the RCM curve 166. Therefore the correct kernel vector can be simply accessed for each of the samples 198 along an RCM curve 166 by storing appropriate data in the active memory 64 which corresponds to the curve 166. One address generator 2 may be used to generate addresses to access the kernel vectors while another generator 2 operating in parallel may be used to generate addresses to access the sample vectors to which the kernel vectors are applied. Alternatively the two address streams of one address generator 2 can be used to access the sample and kernel vectors, alternately. Using the i loop vector to access the active memory 64, the address generator 2 is able to generate addresses to access data according to a two dimensional address matrix 250, which is moved through a memory space 252 according to a curve 254, as shown in Figure 18. Data representative of the curve 254 is stored in the active memory 64 and if the matrix is P × N the j vector loop parameters are set with a step value of N, a length value of P, and the k loop vector parameters are set with a step value of 1 and a size value of N.

Using the k loop vector to access the active memory 64, the address generator 2 can be used to generate addresses to access arbitrary points in a three dimensional memory space, according to data stored in the active memory 64.

The bit reversal facility provided in the address generator 2 is particularly useful for accessing data in a bit reversed order so that it can be applied to a Fast Fourier Transform (FFT) processor 260, as shown in Figure 19, to produce an output 262 which is in the correct bit order. If eight time samples x(i) 264 are applied directly to the inputs of the FFT 260, the butterfly operations 266 performed by the FFT 260 would produce eight frequency domain outputs X(i) in a "bit reversed order", i.e. the order of the samples is altered in manner corresponding to bit reversing the binary representation of the sample number. In a number of applications, the frequency domain output is required in the correct order immediately after it is produced for further processing and delays incurred by having to correct a bit reversed output are undesirable. Therefore it is advantageous to be able to address the time domain samples 264 in a bit reversed order so they can be applied directly in a bit reversed form, as shown in Figure 19. This results in the butterfly operations 266 producing a frequency domain output 262 in the correct order.

Claims

CLAIMS:

1. An address generator (2) comprising means (10,12,14) for generating operand signals, processing means (4,6,8) for forming an address signal on the basis of said operand signals, and means (16) for accessing data on the basis of one of said operand signals and supplying the accessed data to said processing means (4,6,8), in substitution for said one of said operand signals, to form an address signal.

2. An address generator (2) as claimed in claim 1, including control means (18) for controlling said generating, processing and accessing means and for selecting said one of said operand signals to be used an index to said data by said accessing means.

3. An address generator (2) as claimed in claim 2, wherein said accessing means (16) includes a memory interface (16) for connection to a memory circuit (64,66) and for applying said index as a read address to said memory circuit (64,66) to obtain said data.

4. An address generator (2) as claimed in claim 3, wherein said memory interface (16) is adapted for connection to two memory circuits (64 and 66) so as to read data according to said read address and write data according to a write address on alternate cycles.

5. An address generator (2) as claimed in any one of claims 1 to 4, wherein said generating means (10,12,14) generates said operand signals simultaneously on a sequential basis in accordance with the following:

i = initial i

For 1 to size i

j = initial j

For 1 to size j

k = initial k

For 1 to size k

address = base_offset + (i + j + k) k = k + step k

j = j + step j

i = i + step i

where k is the value represented by a first operand signal, j is the value represented by a second operand signal, i is the value represented by a third operand signal, and base_offset, and the initial, step and size values are predetermined integers represented by data stored, in use, in said generator, and address is the value represented by the address signal formed on the basis of said operand signals by said processing means (4,6,8).

6. An address generator (2) as claimed in claim 5, wherein said data corresponds to the trajectory of a curve (166) and said second operand signal is used by said accessing means (16) to access said data, and the address signals formed are vector addresses (198) which move through a memory space (170) according to said trajectory.

7. An address generator (2) as claimed in claim 6, wherein said vector addresses (198) follow the trajectories of different curves (166,206,208,210) for different values of said third operand signal.

8. An address generator (2) as claimed in claim 5, wherein said data corresponds to the trajectory of a curve (254) and said third operand signal is used by said accessing means (16) to access said data, and the address signals formed correspond to a two dimensional address matrix (25) which moves through a memory space (252) according to said trajectory.

9. An address generator (2) as claimed in claim 5, wherein said first operand signal is used by said accessing means (16) to access said data, and the address signals formed correspond to points in a three dimensional memory space according to said data.

10. An address generator (2) as claimed in any one of claims 5 to 9, wherein pairs of said predetermined integers are stored, one set for an active address sequence and the other set for a passive address sequence, and said generator (2) is adapted to form address signals of said active sequence whilst executing processing steps for said passive sequence.

11. An address generator (2) as claimed in claim 10, wherein said generating means (10,12,14) includes, for each operand signal, accumulator means (42) for storing said operand signal, which is supplied with the corresponding step value data to selection means (52), which selectively applies said operand signal and said step value data to adding means (54), the output of said adding means (54) being stored in said accumulator means, as said operand signal.

12. An address generator (2) as claimed in claim 11, wherein said generating means (10,12,14) further includes counting means (56) for each operand signal which counts the adding steps for said operand signal up to the corresponding size value and then generates a carry signal, wherein the carry signals of said generating means (10,12,14) are used to control said selection means (52).

13. An address generator (2) as claimed in any one of claims 5 to 12, wherein said processing means (4,6,8) includes modulo means (100) for performing a 2" modulo operation on the sum, (k + j + i), of said operand signals, n being a positive integer.

14. An address generator (2) as claimed in any one of claims 5 to 12, wherein said processing means (4,6,8) includes modulo means (100) for performing a 2⁽ⁿ⁺¹⁾ + 2ⁿ, modulo operation on the sum, (k + j + i), of said operand signals, n being a positive integer.

15. An address generator (2) as claimed in claim 14, wherein said modulo means (100) comprises:

first masking means (112) to obtain the low n bits of input data of said modulo means (112);

second mask means (114) to obtain the remaining upper bits of said input data; modulo three means (118) for performing a modulus three operation on said upper bits;

shift means (120) for shifting the two bits output from said modulus three means to n+1 and n+2 bits; and

means (116) for outputting said low n bits and said n+1 and n+2 bits together.

16. An address generator (2) as claimed in any one of claims 13 to 15, wherein said processing means (4,6,8) includes pipeline processing stages for combining two of said operand signals to form an intermediate signal, for combining said intermediate signal and the remaining operand signal to form a sum signal and for performing said modulo operation on said sum signal and adding a base_offset signal representative of said base_offset.

17. An address generator (2) as claimed in any one of claims 1 to 16, wherein said generating means (10,12,14) includes means (10,12) for generating in parallel sets of said operand signals and means (14) for selectively outputting one of said sets.

18. An address generator (2) as claimed in any one of claims 5 to 17, wherein said generating means (10,12,14) includes bit reverse means (58) which enables said generating means (10,12,14) to perform a bit reversal operation on said first operand signal such that said address signal is able to access data in a bit reversed order; said first operand signal comprising n bits of data and said bit reversal operation being bit k(m) becomes bit k ((n-1) - m) for m = 0 to (n-1).