WO1993004558A1

WO1993004558A1 - Process and device for separating the synchronisation signal from an image signal

Info

Publication number: WO1993004558A1
Application number: PCT/EP1992/001808
Authority: WO
Inventors: Herbert Schütze; Friedhelm Holtz
Original assignee: Deutsche Thomson-Brandt Gmbh
Priority date: 1991-08-16
Filing date: 1992-08-07
Publication date: 1993-03-04
Also published as: DE4127120A1

Abstract

In digital processing, in particular, it is often necessary to extract a synchronisation signal from a composite image, e.g. an FBAS, studio standard or TTL signal, in order, for instance, to synchronise a PLL (Phase-Locked Loop) therewith. Prior art processes, however, operate inaccurately in the vertical blanking gap of the FBAS signal or generate errors in the case of high-level burst signals. Initially a first reference voltage is formed which is obtained from the blanking level of the image signal (103). From this first reference voltage is formed a second reference voltage (105) with its d.c. voltage level lying roughly at the centre between the blanking level and the synchro-base. From the synchronisation pulse are obtained scanning pulses (109) which are used to generate a third, more accurate reference voltage (115). Shortened scanning pulses (111) are formed from these pulses which start after the beginning of the scanning pulse and stop before its end. These shortened scanning pulses and a sample and hold function (112) are used to measure a value representing the voltage of the image signal synchro-base, to which a further set offset voltage is added. This provides the third, more accurate, reference voltage (115), the level of which lies about midway between the blanking level and the synchro-base. This third reference voltage now exactly follows the level of the synchro-base with changing synchronisation pulses, e.g. in the vertical blanking gap. From the third reference voltage (115) are then obtained accurate synchronisation signals (117) which exhibit very little jitter and are insensitive to over-raised burst signals and permit the generation of exactly timed beat pulses even inside the vertical blanking gap.

Description

Method and device for separating the synchronization signal from an image signal

The invention relates to a method and a device for separating the synchronization signal from an image signal.

State of the art

In image processing, especially in digital, it is often necessary to use a composite image signal, e.g. a CVBS signal, a studio standard or a TTL signal, a synchronization signal (hereinafter called synch signal), e.g. to extract the composite sync signal in order to synchronize a PL (phase locked loop), for example.

Known methods, however, work inaccurately in the vertical blanking gap of the CVBS signals or generate errors in the. Case of high level burst signals.

invention

The invention is based on the object of specifying an improved method for separating the synchronization signal from an image signal. This object is achieved by the inventive method specified in claim 1.

In principle, the method according to the invention consists in first forming a second reference voltage 105 from a first reference voltage corresponding to the voltage level of the synchronous base U of an image signal, the level of which is approximately in the middle between the voltage level of the synchronous base and the blanking level 11 of the image signal lies, and that with the help of the second reference voltage and the - in particular filtered color carrier suppressing - A signal corresponding to the synchronization pulse is obtained, which is converted into a time-shortened signal 111, and that subsequently with the aid of a sample and hold function controlled by this shortened pulse, to which the image signal is supplied, and an offset addition, a third reference voltage 115 is generated, the level of which lies approximately in the middle between the voltage level of the synchronous base and the blanking level of the image signal and from which a time signal is obtained by comparing it with the image signal, which is filtered in particular to suppress the color carrier exact synch signal 117 is formed.

Advantageous further developments of the method according to the invention result from the associated dependent claims.

The invention is based on the further object of specifying a device for the method according to the invention. This object is achieved by the device according to the invention specified in claim 4.

In principle, the device according to the invention is provided with a first reference voltage circuit 104, the input of which is supplied with an image signal 103 and which forms a second reference voltage 105 from a first reference voltage corresponding to the voltage level of the synchronous base U of the image signal, the level of which is approximately equal to the middle between the voltage level of the synchronous floor and the blanking level

U of the image signal lies with a filter 106, to which the image signal 103 is also supplied and in which at least the color carrier of the image signal is suppressed, with a first comparator circuit 108 connected downstream of the first reference voltage circuit and the filter, which compares the syn ¬ chronization pulse of the image signal 103 forms a corresponding touch signal 109, which is reduced in time in a subsequent pulse generator 110. Key signal 111 reshaped and the key input of a sample and hold circuit 112 is supplied, at the signal input of which the image signal 103 is applied and which generates a third reference voltage 115 from the sampled synchronous floor level of the image signal with the aid of a downstream offset adder 114, the level of which is approximately in the middle between the voltage level of the synchronous floor and the blanking level of the image signal and with a second comparator circuit 116 connected downstream, which is additionally supplied with the output signal 107 of the filter 106 and which forms a temporally accurate synch signal 117.

Advantageous further developments of the device according to the invention result from the dependent claims.

First, a first reference voltage is formed, which is obtained from the blanking level of the image signal, e.g. by appropriately charging a capacitor. From this first reference voltage - e.g. by subtracting a fixed voltage - a second reference voltage is formed, which lies approximately in the middle between the blanking level and the synchronous floor in its DC voltage level.

From the synchronous pulse, tactile pulses are obtained which are used to generate a third, more accurate reference voltage. Shortened key pulses are formed from these key pulses, which begin after the start of the key pulse and end before the end of the key pulse. With the aid of these shortened key pulses and a sample and hold function, a value representing the voltage of the synchronous base of the image signal is now measured, to which a fixed offset voltage is also added. This creates the third, more accurate reference voltage, which is approximately in the middle between the blanking level and the synchronous floor. This third reference voltage now also follows with changing sync pulses - e.g. in the vertical blanking gap - exactly the level of the synchronous floor.

Exact synch signals are then obtained from the third reference voltage, for example by means of a comparator are very low jitter and insensitive to excessive burst signals and also allow the generation of exact timing pulses within the vertical blanking interval.

drawings

Exemplary embodiments of the invention are described with the aid of the drawings. The drawings show in:

1 shows a block diagram of the device according to the invention; a first reference voltage circuit; a sample and hold circuit; Waveforms in synch separation; detailed circuitry for blocks 102, 104 and 108 of Figure 1; detailed circuitry for blocks 106, 112, 114 and 116 of Figure 1;

detailed circuitry for block 110 of FIG. 1.

embodiments

In Fig. 1, an input image signal 101 is pelungsschaltung in a decoupled ^N ygleichspannungsmäßig decoupled, buffered, and if necessary, amplified. The output signal 103 of this decoupling circuit is fed to a first reference voltage circuit 104, a filter 106 and a sample and hold circuit 112, which can contain, for example, an integrated circuit LF 398 from the manufacturer National Semiconductor.

The chrominance burst or other interfering signal parts are filtered out in the filter 106, for example with the aid of a notch filtering. The output signal 107 of this filter is sent to a first comparator circuit 108 and a second comparator circuit. tion 116 forwarded. The first reference voltage and the second reference voltage 105 are formed in the first reference voltage circuit. In the first comparator circuit, pulse pulses 109 arise from the output signal 107 of the filter and with the aid of the second reference voltage, which pulse pulses are supplied to a pulse generator 110 and are converted therein into shortened pulse pulses 111.

Under unfavorable circumstances, the pulse pulses 109 can be falsified by the fact that the second reference voltage 105 deviates from its target value, e.g. due to changed sync pulses in the vertical blanking interval. When storing digital image signals delayed by parts of a field, such changed synchro pulses can then lead to clock jitter in visible parts of the image. For this reason, the pulse pulses 109 are only used to generate a more accurate, third reference voltage.

In the sample and hold circuit 112, the voltage of the decoupled image signal on the synchronous base is measured with the aid of the shortened key pulses 111 and recorded until the next shortened key pulse. The subsequent offset adder 114 adds to the output signal 113 of the sample and hold circuit such an offset voltage that the resulting third reference voltage 115 lies midway between the blanking level and the synch level of the decoupled rapid signal. Such an offset adder can also be contained in the first reference voltage circuit 104. In the second comparator circuit 116 connected downstream, the decoupled image signal which has passed through the filter is compared with the third reference voltage 115 and an accurate synch signal 117 is generated.

The filter 106 can be implemented as a notch filter with an active input circuit which is tuned to the frequency of the chrominance burst.

The pulse generator 110 contains, for example, an analog differentiating circuit and an all-pass as a delay element. Alternatively, a digital module can be used that on the negative edge of the pulse pulse 109 after a short delay generates the shortened pulse pulse 111.

2, the first reference voltage circuit 104 is shown in principle. On the one hand, capacitor C1 is slowly charged via resistor R5 and, on the other hand, voltage is pulled to the level of the synchronous floor via diode D1. The capacitor voltage and thus the first reference voltage can be tapped off with high resistance via a buffer U1.

3, the sample and hold circuit 112 is shown in principle. The input signal is fed to a capacitor C9 via a buffer U3 and a V-MOS transistor TR1. The V-MOS transistor can be controlled directly by a TTL signal and is characterized by a very low channel resistance. The capacitor must be dimensioned so that the load from the rest of the circuit does not lead to a measurable change in voltage as long as the V-MOS transistor blocks.

4, various signals from the block diagram in FIG. 1 are reproduced over time: a) input image signal 101; b) output signal 103 from decoupling circuit 102 with blanking level U and synchronous floor level U; c) output signal 107 from filter 106 with the second reference voltage 105 obtained therefrom; d) key pulse 109; e) shortened key pulse 111; f) output signal 107 from filter 106 with the output signal of the sample and hold circuit 112 and the third reference voltage 115; g) the exact synch signal 117. 5 shows the decoupling circuit 102, the first reference voltage circuit 104 and the first comparator circuit 108 in detail. An operational amplifier with a gain of one can also be inserted in the decoupling circuit 102 for better decoupling after capacitor C27. The input line VIDEO IN is terminated with the characteristic impedance of the line, which is also represented by the input resistance Rl. The RC combination for capacitor C1 with the resistors R3, R4 and R5 must have a time constant τ which is large compared to the time difference between two sync pulses. The capacitor C1 is kept at the voltage U + U via the diode D1. By means of a subtractor implemented by the operational amplifier U1, such an offset voltage is subtracted from the voltage at the capacitor that the output voltage, ie the second reference voltage 105, lies in the middle between Ua and Us.

A comparator IC U2 of the type LM 360 is connected to the operational amplifier Ul.

6 shows the filter 106, the sample and hold circuit 112, the offset adder 114 and the second comparator circuit 116 in detail. Both the operational amplifier U3 connected as an impedance converter and the operational amplifier U4 connected as an impedance converter receive the decoupled image signal at the input. U4 is followed by a series resonant circuit consisting of capacitor C14 and inductor L1, which performs notch filtering. The output voltage is coupled out via an operational amplifier U5 connected as an impedance converter. A comparator IC U6 of the type LM 360 is connected to the operational amplifier U5. The signal CS is tapped at the non-inverting output 7.

A V-MOS transistor TR1 of the BS 17C type is connected to the operational amplifier U3, the gate of which is driven by the shortened keying pulse 111. C9 serves as a storage capacitor. A transistor TR2 is connected downstream of this capacitor. tet, which with the help of the series connection of the diodes D2 and D3 and the resistor R13 forms an analog adder. The signal tapped at resistor R13 is also fed to the comparator IC U6.

7, the pulse generator 110 is shown in detail. An integrated circuit U9 of the type Altera EPM 5032 is connected to ground and to the supply voltage + 5V. Instead of this IC type, another programmable module with a comparable function can also be used. A clock signal CL, a signal CS from the second comparator circuit and the keying pulse 109 are supplied to the circuit U9. The only one for them

The output signal required is the shortened keying pulse 111.

Claims

1. A method for separating the synchronization signal from an image signal (101), characterized in that first of all a second reference voltage (105) is formed from a first reference voltage corresponding to the voltage level of the synchronous ground (U) of the image signal their level lies approximately in the middle between the voltage level of the synchronous base and the blanking level (U) of the image signal, and that with the aid of the second reference voltage and the image signal, which is filtered in particular to suppress the color carrier, a key signal (109) corresponding to the synchronization pulse is obtained , which is converted into a time-shortened key signal (111), and that subsequently with the aid of a sample and hold function, which is triggered with this shortened pulse, and to which the image signal is supplied, and an offset addition, a third te reference voltage (115) is generated, whose level is approximately in the middle between the Sp the level of the synchronous base and the blanking level of the image signal and from which a chronologically accurate synch signal (117) is formed by a comparison with the image signal, which is filtered in particular to suppress the color carrier.

2. The method according to claim 1, characterized in that instead of the original image signal (101) a decoupled image signal (103) for the formation of the second reference voltage (105), the image carrier-suppressed filtered image signal and in the sample and hold function ver ¬ is used.

\. A method according to claim 1 or 2, characterized gekennzeich¬ net that the first reference voltage by appropriate charging of a capacitor (Cl) and the second reference voltage (105) by the subtraction of a fixed Voltage from the first reference voltage (105) is formed.

Device for a method according to one or more of claims 1 to 3, provided with a first reference voltage circuit (104), the input of which is supplied with an image signal (103) and which is based on the voltage level of the synchronous base (US) of the Image signal corresponding to the first reference voltage forms a second reference voltage (105), whose level lies approximately in the middle between the voltage level of the synchronous floor and the blanking level (U) of the image signal, with a filter (106), which also the image signal (103) is supplied and in which at least the color carrier of the image signal is suppressed, with a first comparator circuit (108) connected downstream of the first reference voltage circuit and the filter and which detects a synchronization pulse of the image signal (103) speaks tactile signal (109), which in a subsequent pulse generator (110) is converted into a temporally shortened tactile signal (111) and the tact input is fed to a sample and hold circuit (112), at the signal input of which the image signal (103) is present and which generates a third reference voltage (115) from the sampled synchronous floor level of the image signal with the aid of a downstream offset adder (114) The level of which lies approximately in the middle between the voltage level of the synchronous floor and the blanking level of the image signal and with a second comparator circuit (116) connected downstream, to which the output signal (107) of the filter (106) is additionally fed and which forms a precise synch signal (117).

Device according to claim 4, characterized in that the pulse generator (110) contains an analogue differentiating circuit and an all-pass.