WO1993002517A1

WO1993002517A1 - 'van' system with additional access protocol for open circuit conditions

Info

Publication number: WO1993002517A1
Application number: PCT/EP1992/001685
Authority: WO
Inventors: Jean-Pierre Loncle; Thierry SALÄUN
Original assignee: Siemens Automotive S.A.
Priority date: 1991-07-23
Filing date: 1992-07-23
Publication date: 1993-02-04
Also published as: FR2679723A1; JPH07500227A; FR2679723B1; EP0595985A1; KR940701617A

Abstract

A frame sender-receiver module (1) comprises a line sender (5) and a receiver with three comparators (RO, ERRI, ERR2) connected on the bus (DATA, D^¨B7A^¨B7T^¨B7A^¨B7), simultaneous take-over of this bus by several such modules being prohibited by a bit-by-bit arbitration procedure. According to the invention, the appearance of a possible open circuit on one of the lines of the bus is monitored and then the arbitration procedure is complemented by a procedure, which is at least partially random, for attributing sending-time windows which are particular to each module, after each of the signal frames successively sent on the bus, as long as the latter is affected by an open circuit. Application to a local communications network for a motor vehicle.

Description

"VAN" system with additional access protocol for open circuit conditions.

The present invention relates to a transmission method for digital data sent in the form of differential voltage signal frames which are detectable by at least two electronic modules between first and second lines of a data communications bus interconnecting these modules.

More particularly, the present invention relates to such a method designed in order to be implemented in a set of multiplexed electronic modules controlling various functions in a motor vehicle. Even more particularly, the present invention relates to such a method designed to resist the possible presence of accidental open circuits which can affect the transmission of information between modules. „ *

Studies are currently under way to replace the conventional electrical cabling of a motor vehicle with an electrical supply bus and with a digital data trans¬ mission bus interconnecting electronic modules for control of actuators or for acquisition of signals received from sensors. By way of example, the French preliminary draft standard R13-708 corresponding to the working document referenced ISO/TC22/SC3/WG1 N429 Part 2 published by the International Standardisation Organisa- tion, describes the general architecture of a communica¬ tions network called "VAN" designed to be installed in a motor vehicle.

As shown diagrammatically in Figure 1 of the attached drawing, a VAN-type network comprises a plurality of electronic modules A, B, C for example, interconnected by a two-wire bus DATA, DATA which is suitable for transmitting digital data sent by one of the electronic modules in the form of voltage signal frames which are detectable differentially between the two wires or lines of the bus. Every module coupled to this bus comprises a sender, a receiver or a sender/receiver unit such as that referenced 1 on Figure 2 of the attached drawing, for receiving information transmitted by the bus and for sending information on this bus. The receiver part conventially comprises, as is known from the docu¬ ments US-A-4 792 950 and FR-A-2 627 036 _r a first comparator RO whose inputs are connected to the DATA, DATA lines respectively and second (ERR1) and third (ERR2) "common mode" comparators whose non-inverting and inverting inputs are connected to the DATA,. DATA lines respectively and whose inverting and non-inverting inputs respectively are connected to a reference voltage source V_rβf adjusted to a value lying in the excursion of the voltage between the two lines of the bus. Two filters 3 and 4 are arranged between the DATA and DATA lines respectively and the inputs of the comparators. The purpose of these filters is to limit the influence of parasites which can affect the signals transmitted on the lines.

It is clear that if the lines are unaffected by a defect, the comparator RO is sufficient for detecting the differential voltage between the lines of the bus in order to deliver, on its output, a binary signal changing over with the sign of the input voltage. However, by virtue of the two comparators ERR1 and ERR2, it is possible to take advantage of the complementarity of the logic states of the DATA, DATA lines so that the informa¬ tion item circulating on the bus is transmitted to a module operating in reception, even when one of the two lines suffers a short-circuit or an open circuit. Analysis of the outputs of the three comparators makes it possible to detect the defect and to select one of the three outputs, the one which is correctly transmitting the information item. To this end, the line sender/receiver 1 comprises defect diagnostic means 2 permitting a valid comparator output to be selected, these means being associated with management means for a particular transmission protocol chosen for transmission of the information received from the bus to an "applic¬ ation" such as an actuator command or acquisition of signals supplied by a sensor, for example.

The sender/receiver further comprises a line sender 5 whose single-polarity input is connected to the means 2 and whose output, differential, is connected to the DATA, DATA lines through possible protection means 6. All this is well known in the technology and has no need of further description.

In the foregoing, it turns out that a sending module can "re-read" itself via its receiver part. This rereading allows certain defect diagnoses as will be seen later.

Among the defects which can affect the operation of a network such as that represented in Figure 1, must be noted the appearance, transient or permanent, of open circuits such as that shown diagrammatically at 7 by an open switch on the DATA line for example, between the modules B and C. Such open circuits can be present during the transmission of a signal frame, sent for example by module B, while the comparator selected in module C for reading the information on the bus is the comparator RO, which is not reliable in these circumstances as has been seen above. A first solution to this problem is afforded by the transmission method for digital data which forms the subject of the French Patent Application No. 91 03379 filed on the 20th March 1991 by the applicant. This solution consists in carrying out a diagnosis of the presence of an open circuit in the course of reading a frame sent on the bus, on at least one predetermined intermediate sequence of signals for passing the control of the bus from one sender module to another module, and in selecting, on return, the comparator adapted for correct reading of this frame, despite the presence of an open circuit on one of the two lines of the bus.

In a network of the VAN type, it must, however, be noted that access to the bus is asynchronous and that several modules can send simultaneously, the "contention" being regulated by bit-by-bit arbitration over a defined field of the frame, according to a "collision avoidance" procedure to the benefit of the highest-priority message. The modules which lose the arbitration then immediately cease to send.

If then two modules gain access simultaneously to the bus in the presence of an open circuit on one of the lines of the bus between these modules, the bit-by-bit arbitration cannot be carried out correctly as the frames sent are reread on the differential comparators RO of the two modules, comparators which are not reliable in the circumstances, as has been seen above.

The bit-by-bit arbitration can then not take place on the part of the frame provided, or be resolved by the attribution of the bus to the module which is the sender of the lowest-priority message, which generates malfunctions such as: high rate of incorrect frames on the bus, blocking of certain messages or certain modules, paralysis of the network, etc.

The object of the present invention therefore is to provide a reliable transmission of the signal frames sent on the bus, despite a possible open circuit in one of the lines of the bus which is likely to disturb a bit- by-bit arbitration phase between several modules trying to simultaneously access the bus.

This aim of the invention is achieved, as well as others which will appear on reading the description which will follow, with a transmission method for digital data sent in the form of differential voltage signal frames which are detectable by at least two electronic modules between first and second lines of a data communication bus interconnecting these modules, at least one of the modules comprising a frame sender and a receiver designed to receive signal frames sent on the bus through one comparator, selected from first, second and third com¬ parators, the inputs of the first comparator being connected to the two lines of the bus, one of the inputs of the second and third comparators being connected to the first and second lines of the bus respectively, while the other input is connected to a reference voltage situated within the voltage excursion of the lines, the probability of several modules taking control of the bus simultaneously being minimised by a bit-by-bit arbitra¬ tion procedure. According to the invention, the appearance of a possible open circuit in one of the lines of the bus is detected and then the bit-by-bit arbitration procedure is complemented by a procedure, which is at least partially random, for attributing sending-time windows which are particular to each module, after each of the signal frames successively sent on the bus, as long as the latter is affected by an open circuit.

This arrangement makes it possible, in the event of an open circuit, to avoid access to the bus being strictly hierarchical which would prohibit practically all access to the bus by modules low down in the hier¬ archy.

According to another advantageous characteristic of the method according to the invention, the attribution procedure takes account also of the priority rating of the messages contained in the frames sent on the bus.

Other characteristics and advantages of the method according to the invention will appear on reading the description which will follow and on examining the attached drawing, in which:

- Figure 1 shows diagrammatically a network of electronic modules interconnected by a differential bus and Figure 2 represents a line sender/receiver incor¬ porated into such a module, these two figures having been commented on in the preamble to the present description,

- Figure 3 is a timing diagram of the output signals from the comparators of the receivers of the modules of the network of Figure 1, these timing diagrams being useful for explaining the detection of an open circuit on one of the lines of the bus, a detection prior to the attribution of particular sending windows to the modules according to the invention, and - Figure 4 is a timing diagram of the same output signals from the comparators of the modules and from the senders of the modules of the network of Figure 1, which is useful for the explanation of the sending window attribution method according to the invention.

As was seen above, the present invention assumes that means are available for detection of an accidental open circuit in one of the lines of the bus (such as that shown diagrammatically by the switch 7 in Figure 1, which affects the transmission of data between the modules A and B on the one hand and C on the other hand, these detection means being incorporated into the diagnostic and protocol management means 2 of the sending/receiving unit 1 of each module of the network, for example. These means are suitably programmed in such a way as to be able to deduce a possible open circuit of one line of the bus, from observation and comparison of the outputs of the comparators during the sending on the bus of at least two successive signal frames, as will now be explained in connection with the examination of the timing diagrams of Figure 3.

It will firstly be recalled that, as shown diagrammatically on the timing diagram of the output of the comparator ERR1 of the module A, a signal frame in a communications protocol of the VAN type, comprises a certain number of successive fields at the head of which is found a SOF field for "start of frame", this field exhibiting a predetermined configuration which allows it to be recognised and distinguished with respect to possible parasitic signals on the bus, as is explained in the French Patent Application No. 91 02592 filed on the 5th March 1991 by the applicant. The SOF field precedes an "identifier" fields, a "control" field, a "data" field and other accessory fields, shown diagrammatically to- gether by the hatched area which follows the SOF field. Let us now suppose that, in the presence of an open circuit 7 which has not yet been detected, module C takes control of the bus in order to send a signal frame (see "control of the bus" line. Figure 3), this sending being followed by that of another frame by module A before module C retakes control of the bus in order to send a new frame. The three comparators of module C, not being affected by the open circuit 7, all reread the frame sent by the sender 5 of the module C during first taking control of the bus, whereas this frame is perceived only by the comparators ERR2 of modules A and B. When module A next takes control of the bus, the frame that it sends is correctly reread by all of its comparators and by those of module B (not then affected by the open circuit 7) , whereas module C perceives the frame only through its comparator ERR2,. the operation of its comparators ERR1 and RO being affected by the open circuit 7.

Thus the modules A and B, in the presence of such an open circuit, receive a first frame on a single comparator and the following frame on the three com- para ors.

It is the same for module C when it re-takes control of the bus in order to reread itself then com¬ pletely on its three comparators, as only its comparator ERR2 had perceived the preceding frame. Put another way, during sending of two successive frames by two distinct modules placed on either side of the open circuit, each module of the network can diagnose (see the "diag" arrows. Figure 3) the presence of an open circuit on one line of the bus if it successively receives the first frame on one common-mode comparator (ERR1 or ERR2) and the second frame on its comparator RO (and, at the same time, on the two other common-mode comparators).

Having thus detected the presence of an open circuit on the bus, according to the present invention, the possible failure of the bit-by-bit arbitration procedure for access to the bus by the modules that such an open circuit could give rise to will be prevented by then complementing this procedure, according to the present invention, by the procedure for attribution of distinct sending windows to the modules, which will be described below in connection with the timing diagrams of Figure 4.

Prior to this description, it is necessary to dwell on two notions which are indispensable to the understanding of the method according to the invention, namely those of "potentially sending module" and of "priority". A "potentially sending module" is capable of spontaneously sending frames but is not, however, per¬ manently in a position to send a message.

Moreover, the urgency of the transmission on the bus of a message sent by a module can vary from one type of message to another. It can be imagined, for example, that a message relating to a parameter with frequent variations (speed of the engine, for example) might be attributed priority for passage on the bus over a para¬ meter with slow variations (temperature of the engine, for example) . It is, moreover, this which is the motive for the existence, in normal operation, of a bit-by-bit arbitration procedure for access to the bus, on the basis of the priority for passage accorded to the messages sent by such and such a module. In the VAN protocol, this arbitration is exercised on bits of the "identifier" field.

According to one essential characteristic of the method according to the invention, in the presence of an open circuit on one of the lines of the bus, each poten- tially sending module attributes to itself a time window during which it can send a message on the bus, to the extent, obviously, where it has a need to send such a message and where no other module has previously taken control of the bus. Each module is equipped with internal logic which is duly programmed to execute the window calculations by applying the following rules.

As represented on line n of the timing diagrams of Figure 4, at the end of each frame sent on the bus, (n+1) successive windows of identical durations d are determined by each module, the heads of these windows of order number n_t being indexed by the pulses referenced 0, 1, 2, 3, 4, 5, etc.

The order number n*_ of the window which a module A attributes itself (i=l), B (i=2) or C (i=3) is calculated by addition of an integer number _t quantifying the priority of the message which the module has to transmit and by a number a_t drawn by the module in a random manner from among (A+l) integer numbers (0 ≤ a_t < A) . Hence:

The window distribution method according to the invention will be explained via a numerical example, in connection with Figure 4 which illustrates it.

As was seen above, the window allocations are made at each end of frame seen on the bus. Assuming the existence of eight classes of priorities (0 < p_± < 7, 0 being the highest priority) and of eight possible integer values for the random number a (0 < ai < 7) , it is possible to calculate, as follows, three successive window allocations, each rendering the previous alloca¬ tion obsolete: 1st allocation: p₂=4,a₁=2→n₁=6 (module A allots itself the 7thwindow) p₂=2,a₂=7->n₂=9 (module B allots itself the 10th window) p₃=3,a₃=4→n₃=7 (module C allots itself the 8thwindow) 2nd allocation:

(module A allots itself the 8thwindow) p₂ ⁼0, ₂ ⁼5-»n₂ ⁼5 (module B allots itself the 6th window) p₃=3,a₃=l->n₃=4 (module C allots itself the 5th window)

3rd allocation: p_x=4,a₁=2-+n₁=6 (module A allots itself the 7thwindow) p₂=0,a₂ ^s-*0-**n₂=0 (module B allots itself the 1stwindow) p₃=5,a₃ ^*=4→*n₃=9 (module C allots itself the 10th window)

Hence, during the first allocation (see Figure 4) module A having drawn the 7th window (n^β) starts to send the SOF field and the start of the identifier field on which the bit-by-bit arbitration is exercised (see line "data sent" DE) . Module B having to send a message of higher priority (p₂=2) than the modules A and C, "latches" onto the SOF field sent by module A on the bus and sends the said message after having gained priority over module A which ceases to send after the bit-by-bit arbitration of priorities applied to the "identifier" fields which follow the SOF fields, as was seen above. On the opening of the 8th window which module C had attributed to itself, the latter notes that the bus is occupied by module B and therefore cannot send. As, by hypothesis, the DATA line of the bus is open-circuit, only the comparator ERR2 of module C reads the frame present on the bus.

When module B ceases to send, the bus again becomes free and, according to the invention, a new window allocation procedure comes into play. By virtue of the random component a._L which comes into the calculation of the order number of the windows then attributed to the 3 modules, the probability that the new attribution is strictly identical to the preceding one (that it replaces) is very small. Hence access to the bus is not ordained or hierarchical solely on the basis of the priorities p_L of the messages sent by the modules. By virtue of the present invention, a message which does not have a high priority nevertheless has a chance of being sent on the line with sufficient frequency to be useful, even when an open circuit affects the communications between modules established by the bus. With this hypo¬ thesis, access to the bus is thus rendered pseudo-random, - li ¬

the random component a_t tempering the access inflexibility which would be defined by taking into account only the priority p_L of the message.

It is thus that the second window allocation attributes priority for taking control of the bus to module C (n₃=4) which sees itself allotted the fifth window, while module B (n₂=5) receives only the sixth window. At pulse 5 when this latter window opens, module

B notes that the bus is controlled by module C and therefore remains silent (see line DE). Here again, due to the open circuit in the DATA line, it is via the comparator ERR2 that module B detects occupation of the bus by module C. When the latter ceases to send, a third window allocation is carried out, as soon as the bus is judged "free", module B then taking control of the bus as soon as the first window (n₂=0) opens, and so on, for as long as an open circuit defect affects one of the lines of the bus.

Needless to say, modules A, B and C operate independently of one another and each proceed with separate random drawing of the value a_A; it can happen that, for the same allocation, the same window is attributed to two or more different modules. On the opening of the said window, a collision will then im- mediately be detected by the modules and a new window allocation procedure initiated as from the following window. This new procedure carried out with a new random drawing of a_t has only a very small probability of reproducing the untoward preceding attribution and access to the bus for the modules will then be unblocked.

The duration d of a window is chosen in such a way as to permit a module whose window is opening to differentiate between occupation of the bus by a parasi¬ tic signal and take-over of the bus by another module during a previous window. A procedure to this effect is described in the French Patent Application No. 91 02592 filed on the 5th March 1991 by the applicant, which may be referred to for more detail on this point. This procedure is based essentially on recognition of the SOF start-of-frame field, a field onto which a module having priority can "latch" as was seen above in the description of the first window allocation. It will be understood then that it is necessary for the duration d of a window to be at least equal to the duration of a SOF field so that the latter can be recognised before the opening of the following window. The procedure of latching onto a SOF field is, however, possible only between modules which do not suffer from an open circuit of one of the lines of the bus, as is the case for modules A and B in the case of the open circuit 7 represented by way of example in Figure 1.

If a potentially sending module has no message to send at the moment of calculation of the order number of its sending window, the number is calculated by according an average priority to the virtual message. If the module still has no message to send at the moment where its window opens, it does not send. In contrast, if it has a message to send next, it considers the first window which follows the send request to be open.

It now appears that the transmission method for data according to the invention makes it quite possible to achieve the declared objective. Hence, in the event of an open circuit, simultaneous access to the bus is limited due to the fact that each module has available only one window to initiate sending. The modules are, moreover, largely insensitive to common-mode noise as every sending which does not begin with a time window is adjudged to be a noise and rejected as such. Moreover, the only partially random character of the window at¬ tribution, which takes into account the priority of the messages, makes it possible not to increase the time scale for sending high-priority messages by too much. Hence introduction of the random component a._t makes it possible to accord two different windows to two messages of the same priority and to make the priorities "rotate" in order not to penalise low-priority messages too greatly.

It is clear in this respect that if all the messages sent by the modules were of the same priority, attribution of the sending windows could be. carried out via a completely, and not partially,^* random procedure.

Needless to say, the invention is not limited to the embodiment described and represented which has been given only by way of example. Thus the invention extends to other communications networks, for motor vehicles (such as the CAN network) or other applications. The method described is adaptable to this or that application as it is possible to play on the various possible com¬ binations of parameters a_i and pj. in order to increase the weight of the random component a_A with respect to the priority p_A or conversely. The duration of the window d is, in the same way, adjusted on -the basis of the com¬ promise desired between the delay that the emission of a frame takes (with respect to normal) and the security required in the recognition of frame signals with respect to parasites.

Claims

CLAIMS 1. Transmission method for digital data sent in the form of differential signal frames which are detectable by at least two electronic modules between-first (DATA) and second (DATA) lines of a data communication bus interconnecting these modules, at least one of the modules comprising a frame sender and a receiver designed to receive signal frames sent on the bus through one comparator, selected from first (RO) , second (ERR1) and third (ERR2) comparators, the inputs of the first com¬ parator (RO) being connected to the two lines of the bus, one of the inputs of the second (ERRl) and third (ERR2) comparators being connected to the first (DATA) and second (DATA) lines of the bus respectively, while the other input is connected to a reference voltage situated within the voltage excursion of the lines, the probabi¬ lity of several modules taking control of the bus simul¬ taneously being minimised by a bit-by-bit arbitration procedure, characterised in that the appearance of a possible open circuit in one of the lines of the bus is monitored and then the bit-by-bit arbitration procedure is complemented by a procedure, which is at least par¬ tially random, for attributing sending-time windows which are particular to each module, after each of the signal frames successively sent on the bus, as long as the latter is affected by an open circuit.

2. Method according to Claim 1, characterised in that the window attribution procedure takes account of the priority of the various messages sent by the modules.

3. Method according to Claim 2, characterised in that an integer number (a ) forming part of a plurality of such consecutive integer numbers is drawn randomly in each module, during a sending window attribution proce¬ dure, and the order number (n_t) of the window attributed to the said module is calculated by adding an integer number (p_±) quantifying the priority of a message which the module perhaps has to send, to the integer number (a,,) drawn randomly by the module.

4. Method according to Claim 3, characterised in that, if a module has no message to send at the moment of the calculation of the order number (n of the window which is allotted to it, this calculation is carried out by giving an average value to the number (p quantifying the priority of a message.

5. Method according to any one of Claims 1 to 3, characterised in that a collision on the bus is detected when two modules at least attempt to take control of the bus after attribution of the same window to these two modules and the partially-random attribution procedure is reinitiated on opening of the window which follows the window during which the collision took place.

6. Method according to any one of Claims 1 to 5, characterised in that each window exhibits a duration (d) at least equal to that of a field (SOF) placed at the start of the signal frame.

7. Method according to any one of Claims 1 to 6, characterised in that the presence of an open-circuit defect on one line of the bus between two modules is diagnosed when a module detects two consecutive frames sent by two distinct modules successively on either of the second (ERRl) and third (ERR2) comparators, and on the comparator (RO) , respectively.