WO1992022128A1 - Improved signal generator and testing apparatus - Google Patents

Abstract

An RF source for generating RF signals by which components can be tested, which comprises a master oscillator (26), coarse and fine tuning controls (110, 112) and circuit means (Figure 6 and (34) Figure 5) for generating two sets of harmonically related markers for calibration, a low resolution set for coarse calibration and a higher resolution set (separated by smaller frequency intervals) for more accurate calibration, and signal generating means (20, 28) for producing control signals for operating the coarse and fine tuning controls, the values of the control signals being determined by reference to the harmonically related markers and the displacement of the desired frequency at which the master oscillator is to oscillate from the frequency of at least the nearest marker. A method of setting up such an RF source to oscillate at a particular frequency F is described using the two sets of markers to calibrate the signal generator.

Description

Title: Improved signal generator and testing apparatus

Field of invention

This invention concerns apparatus for generating radio frequency (RF) signals up to 20GHz in frequency and beyond and test apparatus for use therewith whereby the response of electrical and electronic components and assemblies (devices) can be tested at specific frequencies and over bands of frequencies. For convenience such apparatus will be referred to as RF test apparatus and the signal generator will be referred to as an RF signal generator while the components and assemblies under test will be referred to as RF components or devices - it being understood that the expression RF is not in any way limiting as to the frequency of the generated signal or the frequency at which a component or device under test is to perform. The test apparatus typically comprises a signal analyser.

Background

An RF signal generator is described in UK Patent Specification 2181911 capable of operating in the GHz range. In practice the apparatus described therein is suitable for operating up to approximately 2GHz and generating frequency sweeps for testing RF devices. Above that frequency the techniques described have been found to require refinement to enable accurate setting up of frequency such as for example to define the start position for a sweep.

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It is an object of the present invention to provide a method and apparatus for improving the accuracy of the frequency of

SUBSTITUTESHEET oscillation of such an RF generator, and test appartus including such an RF generator, thereby offering inter alia enhanced sweep start accuracy.

Summary of the invention

According to the present invention in an RF source which comprises a master oscillator having coarse and fine tuning controls, two sets of harmonically related markers are generated for calibration, a low resolution set for coarse calibration and a higher resolution set (separated by smaller frequency intervals) for accurate calibration.

A method of setting up such an RF source, to oscillate at a particular frequency (for example to define the start position of a frequency sweep) may comprise the steps of:

(1) calibrating the oscillator using the coarse calibration markers,

(2) using this calibration to generate a control signal for the coarse tuning control to enable the oscillator to oscillate somewhere in the range F + f (where F is the desired frequency and 2f is the resolution of the coarse calibration) ;

(3) calibrating the fine tuning control of the oscillator using the high resolution calibration markers between two coarse calibration markers, for frequencies in the range F + f,

(4) using the high resolution calibration markers to determine the value of a signal to be applied to the fine tuning control of the oscillator to adjust the oscillator frequency to the desired frequency F, and

(5) applying the coarse and fine control signals thereby generated to the coarse and fine tuning controls respectively, to obtain the desired frequency of oscillation F.

Conveniently the coarse calibration is performed by digitising the coarse frequency controlling signal over the • complete range of the oscillator and storing the digital values of the signal when the frequency of the latter coincide with each one of the coarse calibration markers . Using the stored values (and extrapolating therebetween to obtain a coarse control signal value for a frequency intermediate those for which signals are stored) enables a control signal to be generated for causing the oscillator to oscillate nominally at the desired frequency albeit within a range +f (where 2f is the coarse calibration marker frequency spacing) of the desired frequency.

In a similar manner the fine calibration may be performed by digitising the fine frequency controlling signal between two fine calibration markers, one on either side of the frequency at which the oscillator is actually oscillating and in the range (F +_ f) and storing the digital values of the signal when the frequency of the latter coincides with the high resolution calibration markers within the defined range. Using the stored values and extrapolating therebetween it is possible to obtain a fine control signal value which if applied to the fine tuning control of the oscillator will in combination with the previously computed coarse control signal, cause the oscillator to oscillate at the desired frequency F.

SUBSTITUTESHEET The coarse calibration of the oscillator may be achieved by sampling at 4096 points throughout the range of frequencies produced by the oscillator.

The more accurate calibration of the oscillator may be achieved by similarly sampling at 4096 points between two high resolution calibration markers on either side of the frequency of oscillation selected by the course frequency controlling signal.

The method may also include the step of altering the control signal to at least the coarse frequency control of the oscillator so as to first of all increase the oscillator frequency and sweep the latter from the desired frequency F up to a higher frequency, and back again, by reversing the change in the frequency controlling signal supplied thereto, and thereafter checking the frequency of oscillation after the oscillator has been returned to the start position using at least the high resolution calibration markers, to determine the final frequency of oscillation, and effecting any further adjustment necessary to the frequency determining control signals (but particularly the signal supplied to the fine tuning control) so that the latter brings the frequency of oscillation to the desired frequency F at the end of the sweep.

The method of the invention may be performed at regular intervals of time and corrections made to the frequency controlling signals applied to the oscillator so as to maintain the frequency of oscillation thereof at the desired frequency.

Where the RF source is a YIG oscillator the recalibration step is typically performed every 200 milliseconds.

SUBSTITUTE SHEET

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In order to achieve this degree controlling contol, the calibration steps and alteration of the frequency controlling signals supplied to the oscillator (particularly to the fine tuning control thereof) , are under microprocessor control. Conveniently the latter includes or is associated with memory into which the results of the calibration sweeps and other data are stored for reference . purposes.

The harmonically related marker signals are preferably generated with reference to a temperature controlled crystal oscillator.

The invention also lies in apparatus for performing any of the aforementioned methods.

As described and claimed in our co-pending application reference 264W, the RF source, detector and associated control unit are preferably contained within a single unitary housing together with relevant power supplies and internal environmental controls to maintain temperature, etc and thereby improve reliability and consistency of operation. A signal analyser and display may be located within the same housing.

Where the analyser includes display means the integrated arrangement provides additional advantages in that preliminary calibration procedures, if desired, can be highlighted in the display, if appropriate, to indicate that the instrument is proceeding through a calibration process, and when calibration has been completed, a signal to that effect can be applied to the display to produce an indication therein as a reassurance to the user. Such interaction ^"between the RF source and the analyser display is only possible when the units are combined in an integral arrangement.

Where the frequency range of the sweep following the calibrated start position includes changes in the RF source (such as mode changes) which will result in different noise levels in the signal to be handled by the detector and analyser, the auto-zeroing feature (ie. compensation for electrical noise) disclosed in our co-pending application reference 264W may be incorporated to advantage, so that the sensitivity of the instrument remains substantially constant over the entire range of the sweep, and any indication (such as a visual display) of the response of the device under test will not be distorted due to wide band or other noise content of the signal detected.

An instrument embodying the present invention (with or without the auto-zeroing feature of our co-pending application 264W) may also include the techniques disclosed in our co-pending application 263W and the techniques and refinements described in those two applications are hereby imported into the present application by reference thereto.

According to another aspect of the present invention test apparatus for use in the GHz range of RF frequencies, by which the response of devices under test can be ascertained to signals in that range, comprises:

(1) an RF source for generating RF signals up to tens of GHz with output means for delivering signals to a device under test;

(2) RF detector means adapted to receive signal(s) from a device under test and generate signal(s) indicative of the attentuation of the device to the supplied RF signal(s); and

(3) microprocessor based control means receptive of signals from and adapted to generate control signals for both the RF source and the detector for calibration and control of the source and to optimise the sensitivity of the detector to the RF signals and decrease its sensitivity to electrical noise signals,

wherein all of items (1) to (3) are contained within a common housing to facilitate the transfer of information between the source, the detector and the microprocessor based control unit.

Display means for visually displaying the measurements made on the device under test may also be included within or associated with the common housing.

The invention will now be described by way of example with reference to the accompanying drawings, in which:

Figure 1 is a block schematic diagram of an RF test apparatus constructed in accordance with the invention;

Figure 2 is a similar block schematic diagram of the CPU based control module of Figure 1 ;

Figure 3 is a block schematic diagram of that section of the system of Figure 1 which controls the YIG oscillator and provides for marker detection;

Figure 4 is a block circuit diagram of an RF souce for

SUBSTITUTE SHEET generating signals in the 8-27GHz range;

Figure 5 is a block circuit diagram of an RF source for generating signals in the dc-8GHz range;

Figure 6 is a block circuit diagram of that part of the RF signal generator which generates 500MHz markers;

Figure 7 is a block circuit diagram of that part of the RF signal generator which generates 25MHz markers for use with the 500 MHz markers;

Figure 8 is a block circuit diagram of a voltage controlled oscillator source for generating a comb of frequencies;

Figure 9 is a block circuit diagram of a frequency divider module as employed in the apparatus of the foregoing drawings;

Figure 10 is a block circuit diagram of a frequency divider module and 25MHz marker pulse generator, for use with the low band RF source of Figure 5;

Figure 11 is a block circuit diagram of those parts of the system which perform noise signal compensation on the RF signals, processed by the analyser, of which it forms a part; and

Figure 12 illustrates a common housing testing apparatus embodying the invention.

Detailed description of the drawings

An overall system embodying the invention is shown in Figure

SUBSTITUTESHEET 1 in which a device under test 10 is supplied with an RF signal from the output 12 of the test system and after passing through the device under test 10, the signal is applied to the input 14 of a signal analyser 16. The latter produces via ADC 18 a digital signal whose value is proportional to the amplitude of the RF signal at the input 14.

This digital signal is routed via a central processor unit 20 (based on an Intel 80C88-2 processor) to a display 22 which may be LCD or CRT based, to produce a visible trace representative of the attentuation of the device 10 to different frequencies. To this end the processor unit 20 produces additional signals for generating in the display calibration traces for reference, corresponding to amplitude and frequency, which additional signals are supplied also to the display.

The operation of the processor unit is under the control of front panel controls which may include a keyboard 24, and the latter and the control unit are not only employed to control the display 22 but also the operation of the overall system as will be described later.

The RF signal is obtained from a YIG oscillator 26, control signals for which are derived from a source control unit 28 itself under the control of the processor unit 20. The unit 28 includes inter alia Digital to Analogue devices (DAC's) 30 for generating currents for driving the YIG oscillator coils from digital signals and a detector circuit 32 adapted to detect markers generated by a crystal controlled oscillator contained in a marker generator 34.

Where a range of frequency greater than that obtainable from

SUBSTITUTESHEET a single YIG oscillator is required, additional RF signal sources such as shown in dotted outline at 36 may be provided, and the appropriate source (YIG or otherwise) selected and caused to operate under the control of the source control unit 28 as required by demand signals from the processor unit 20. In addition or alternatively down conversion techniques may be employed such as described in UK Patent Specification 2181911 to achieve RF frequencies below 2GHz. It is to be understood that the references to a YIG oscillator in Figure 1 is intended to cover all such systems as appropriate.

The different elements of the overall system and their mode of operation will now be described:

CPU based control unit (Figure 2)

Figure 2 is a block schematic circuit diagram of the control unit of item 20 of Figure 1. The actual processor (typically an Intel 80C88-2 chip) is denoted at 38 and the control signals therefor (clock, reset and wait state signals) are generated by 40 to which acknowledgement and other signals are supplied by the processor 38. The usual address and data buffers are denoted by 42 and 44 respectively and data from an EPROM 46 and RAM 48 is supplied via the data bus 50 either to the processor 28 (via the buffer 44) or to the output/input data buffer 52. Externally generated data supplied to the buffer 52 can also be routed either to the processor 38 and/or the EPROM 46 and/or RAM 48. Address information from the processor 38 is decoded by memory select decode unit 54 and is supplied to the address line of the EPROM direct and the RAM via control unit 56, by which inter alia data in the RAM can be preserved in conventional manner by refresh techniques. Interrupts for controlling inter alia the processor 38 are obtained from an interrupt generator 58 which also receives interrupts from external sources along line 60 and supplies interrupts to and receives interrupts from other devices along interrupt line 62 and the main data bus 50.

Certain address signals from buffer 42 on address line 64 are to enable internal devices and a device selector 66 is supplied with the address signals and in turn enables different I/O ports 68, 70, 72 and 74 depending on the address signal, via address line 76. A time slice generator 78 also derives signals from the output signal of decoder 66.

The input signal 40 on line 41 is derived from a graphics display processor (not shown) and is a signal which inhibits operation of the CPU 38 until the display CPU is ready to change the graphics display.

The interrupts on line 60 will in general be derived from front panel and/or keyboard, to prevent operation of the CPU 38 until the front panel controls and/or keyboard have been left untouched for a programmed interval of time.

The time slice device 78 is a monostable device which fires every 30ms to trigger the controller 58.

The address bus 82 and I/O select bus 86 provide the signals for addressing devices external to the unit 20, and routing signals to and from the unit 20 and between other devices external thereto, and enabling the disabling devices in units external to 20. Thus the address bus 82 controls addressable devices in other units (yet to be described),

SUBSTITUTE SHEET whilst the signals on 86 enable for example selected DAC's, the YIG oscillator, front panel and/or keyboard controls etc.

The data bus 58 provides inter alia numerical values for the DAC's 30 in the YIG control unit 28.

The GPIB port 68 is a parallel port allowing remote control to IEE 488.

The switched filter port 70 provides control signals for switching different remote filters into and out of operation (to be described) and in the same way port 74 provides control signals for the step attenuator incorporated in the YIG based RF source to be described with reference to Figures 4 and 5.

The bus 59 is an important element in that it contains information by which the CPU 38 can be informed as to where a particular interrupt signal has originated. Thus for example the front panel may generate an interrupt signal whereupon an appropriate signal appears on the bus 59 which via data bus 50 relays this to the CPU. In that circumstance the latter is programmed internally to address the front panel to determine what front panel control has been altered. Likewise keyboard interrupts identify that the CPU 38 should interrogate the keyboard.

Lastly, the processor control unit 20 includes an address buffer 80 for routing addresses to external devices (not shown) via line 82 and an input/output selector 84 by which external input and output devices (not shown) can be addressed and/or selected to operate in a particular manner by signals along line 86.

^SUBSTITUTESHEET The data bus for the units external to unit 20 is denoted by 88. The external bus associated with the GPIB port 68 is denoted by 90, and the signal output lines of ports 70-74 are denoted by 92-96 respectively.

Control of YIG oscillator

Figure 3 shows in more detail the relevant sections of item 28 of Figure 1 for controlling the YIG oscillator 26.

Data along line 88 is buffered by data buffer 98 onto a data bus 102. Similarly Address data and sSlect signals on 82 and 86 are decoded by an input/output decoder 100 onto a bus 104.

Address signals on 104 are supplied to different elements of the circuit including a marker detector 106 which will be described later.

Data, address and select signals are supplied to the control port 108 within the YIG control circuit which essentially controls the currents flowing in a main YIG coil 110 and a subsidiary FM coil 112. The main YIG coil current is controlled by a summing amplifier 114 one input of which is derived from a digital to analogue converter 116 set to respond to a digital data signal on bus 102 to produce a mean current for the main coil corresponding to the centre of the range which the YIG oscillator is intended to sweep.

The frequency range swept by the YIG oscillator is determined by the analogue signal from a second digital to analogue converter 118 again supplied with digital data from

iUBS_TϊTUTESHEET bus 102 but additionally with a ramp signal from a third digital to analogue converter 120 also supplied with digital data from bus 102 so as to generate a ramp signal which causes the sweep width DAC 118 to generate an appropriate bi-polar ramping signal to effect the sweep.

The output from DAC 118 is shown supplied via switch 122 to the second input of summing amplifier 114. In this mode of operation the width DAC output combines with the centre DAC output signal to generate a current for the main YIG coil which starts at a low value and increases to a high value or vice versa, to effect a desired sweep centred about a desired centre frequency.

A fourth digital to analogue converter 124 also receives digital data from the bus 102 and supplies an output signal via summing amplifier 126 to control the FM coil current. The frequency change effected by the FM coil is relatively small and the signal from DAC 124 is essentially a fine tuning control. In use, the digital data appropriate to initiating the sweep and causing the YIG oscillator to oscillate at the start frequency are provided to the appropriate DAC'S 116, 118, and the actual YIG oscillator frequency is determined using the marker signals (to be described) and in accordance with the technique described in our British Patent 2181911. Any adjustment needed to the YIG oscillator to bring the frequency within the desired range of accuracy of the start frequency is achieved by generating appropriate digital data and supplying this to the error DAC 124 so as to generate a bi-polar signal for supply to the FM coil to fine tune the YIG oscillator to the desired frequency.

In low band ranges, the frequency swing achievable by the FM

SUBSTITUTESHEET coil 112 may in fact be sufficient to achieve the desired frequency sweep and in these situations, switch 122 may be placed in the alternative position shown in dotted outline shown in Figure 3 so that the width DAC output 118 is supplied to summing amplifier 126 and this signal is used to swing the YIG frequency between two extremes within the range of sweep capability determined by the FM coil 112. As before the centre frequency will be determined by the signal supplied by the centre DAC 116 to the main YIG coil 110 via summing amplifier 114 but with switch 122 in the alternative position, the centre DAC signal will not be altered during the sweep and the change in frequency of the YIG oscillator is achieved solely by changing the signal to the FM coil.

Further error adjustment may be made by checking the frequency of the YIG oscillator at the end of the sweep as well as the beginning and noting any change in error DAC signal needed to bring the YIG oscillator frequency to the target frequency at the end of the sweep. Any such change in error signal to be delivered by the error DAC 124 during the sweep can then be apportioned over the sweep in any desired manner either linearly or according to an algorithm so that the error signals produced by the error DAC 124 at the beginning and the end of the sweep produce the precise start and finish points of the sweep and to a first approximation the correct error signal is delivered by the error DAC 124 during the sweep at all intermediate frequencies.

Signals for the error DAC may be stored in a memory associated with the processor 38 and the central processor is adapted to interrogate the frequency of the YIG oscillator and compare this with the markers generated by circuit 34 so as to determine precisely the frequency of oscillation and enable error signals to be computed so as to correct the operation of the YIG oscillator to achieve the desired frequency at the beginning and the end of the sweep.

Two sets of markers are generated one set at 25MHz intervals and one at 500MHZ intervals. The manner in which these signals generate will be described in more detail in relation to later drawings but for the purposes of Figure 3, the 25MHz spaced markers are shown incoming on line 130 and the 500MHz spaced markers on line 132. Both inputs are supplied to each of an edge detector circuit 134 and 142, one of which is set to determine leading edges and the other trailing edges of pulses appearing on the inputs 130 and 132. The outputs from the detectors 134 and 142 appear on lines 138 and 144 and logic circuits 140 are provided for inspecting the outputs of the detectors to determine one unique condition, namely when a leading edge is detected immediately after a trailing edge. In this situation the logic circuit 140 generates a pulse for delivery along line 141 as a data signal for routing to the microprocessor to inform the latter that a marker pulse has been seen.

The precise position of the mid point can be determined from the position of the detected trailing and leading edges and additional logic circuits may be provided to determine the positions of the leading and trailing edges of a dip in amplitude for this purpose.

In general the circuit of Figure 3 will be used with the switch 122 in the position shown where the sweep range is in excess of 40MHz. For sweep widths less than 40MHz, the alternative position of the switch 122 may be used since sweeps of less than 40MHz can be normally be accommodated by alteration of the current to the FM coil 112 via the summing amplifer 126.

RF High-band source

Figure 4 shows in detail the essential parts of a high-band RF source for use in a test system according to the invention. Essentially the source can be used for signals in excess of 2GHz up to the maximum frequency obtainable from a YIG oscillator, typically between 20-30GHz. In practice, any one user only has a requirement for a range of frequencies well within the overall range capability of a YIG oscillator and typically a variety of instruments may be offered each having the same basic design but with component selection and YIG oscillator design specific to the restricted band for that particular users requirements. Thus an instrument might well be offered having a range 2- 8.4GHz, another between 8-12.4GHz, another between 12.4- 20GHz etc.

In Figure 4, the YIG oscillator 148 is shown driven by coils 110 and 112 as previously referred to and the output from the YIG oscillator is supplied to a control modulator 150 to which an automatic level control signal is supplied along line 152 and a gating pulse along 154. The latter is used to gate the RF signal since in practice it may be desirable to be able to gate the RF signal without turning the YIG oscillator on and off.

The signals passed by the circuit 150 enter a directional detector 156 the operation of which is to sample signals passing from left to right in Figure 4 but not from right to left. The circuit is based on a diode detector so as to generate an amplitude proportional signal for controlling

SUBSTITUTESHEET the level of the RF signal supplied thereto via the ALC circuit in the control modulator 150. To this end the signal along line 157 is supplied to the ALC input 152. Essentially the circuit operates so as to restrict the amplitude of the signal supplied from the directional detector 156 so that the RF signal is substantially constant in amplitude throughout the working range of the oscillator. Normally this will mean restricting the amplitude of the RF signal to the lowest amplitude obtained and normally amplitude reduces with frequency so that the lower frequencies will be attenuated more than the higher.

The RF output appears at the output socket 158 and an optional user controlled step attenuator 160 may be inserted as shown to allow selective attenuation of the RF signal. A step attenuator is essentially frequency independent so that any attenuation introduced is uniform across the range.

Marker pulses at 500MHz spacings and 25MHz spacings are obtained using the circuit in the lower section of Figure 4. To this end part of the RF signal from the YIG oscillator 148 is tapped off from the control modulator 150 via line 161 to form one input to a sampler or mixer 162. The other input for the sampler is a comb of frequencies produced from a voltage controlled oscillator and appropriate harmonic generating circuit 164. These will be described in greater detail in relation to later drawings. It is sufficient to note that the signal supplied to the sampler 162 is made up of a 500MHz fundamental and a large number of harmonics (typically 50 or more) each spaced from the other by 500MHz.

The effect of the sampler is to produce a beat signal as the IG oscillator signal sweeps through frequencies

SUBSTITUTESHEET corresponding to the different harmonics in the input along line 165 and as each coincidence occurs, the difference signal from the sampler 162 will sweep from a high frequency through a low frequency (possibly DC) up to a high frequency again. An IF amplifier 166 is set to produce 500MHz pulses in the region of each frequency excursion through DC along line 167 and a mid-range sweep from 250MHz through DC back up to 250MHz is supplied along line 169. This signal is a by-product of the action of amplifier 166 as will be described later.

A divider 168 serves to generate a 25MHz signal from the 500MHz voltage controlled oscillator output of 164. This is also supplied to a 25MHz marker pulse generator 170 which in combination with the signal along line 169 produces a series of marker pulses similar to the 500MHz pulses but of reduced width and spaced by 25MHz intervals as the YIG oscillator is swept through its range.

The circuit shown in dotted outline in Figure 4 thus corresponds to the marker generation circuit 34 of Figure 1.

Alternative low-band RF source

Figure 5 shows an alternative source which can be switched between low and high band operation to give an extended range of frequency from frequencies well below those at which a YIG oscillator will normally oscillate through to signals in the YIG oscillator range. In the high range, 500MHz and 25MHz marker pulses are required and to this end part of the circuit of Figure 5 is identical to that shown in Figure 4 and is enclosed within dotted outline 34. For frequencies below 3GHz, it is possible to lock the YIG oscillator using 25MHz markers only and to this end an alternative marker pulse circuit is shown at 34'.

As with Figure 4, the YIG oscillator 148 is shown driven by coils 110 and 114 and the control modulator, directional detector and step attenuator operate in the same manner as described in relation to Figure 4, to provide an RF output at 158. The additional circuit elements essentially comprise a down converter 172, switched filter 174 and the alternative 25MHz marker pulse generator 178.

The down converter 172 operates in essentially the same manner as that described in our British Patent Specification 2181911 particularly with regard to Figure 7 thereof.

Signals in the range 6-8.3GHz are supplied to the down converter along line 176 which includes a local oscillator at the lower frequency to generate a heteradyne signal in the range DC to 2GHz for supply to a switched filter 174. The latter operates on the signal on line 175 from the control modulator 150 or the line 177 from the down converter and provides the RF output signal to the directional detector 156.

The switched filter 174 passes the fundamental and removes any harmonics and it is this part of the system which tends to produce different broad band noise as it is switched to allow the passage of lower or higher frequency signals. Compensation for this introduced noise must be provided and is a feature of the circuit.

For instruments designed to operate up to 8.4GHz, the down converter 172 is included together with the appropriate switched filter 174. For instruments operating in the GHz range only, it can be constructed in accordance with Figure 4.

The control modulator unit 150 also provides an output signal corresponding to the YIG oscillator frequency to a sampler 162 of the type described in UK Patent Specification 2181911. The device is additionally supplied with a comb signal at 500MHz and harmonics from a voltage controlled crystal oscillator and power amplifier 164.

The sampler output is subjected to filtering and processing in an amplifier 166 to provide 500 MHz marker pulses. The amplifier 166 will be described in more detail with reference to Figure 6.

The basic 500 MHz signal from oscillator 164 is divided by a divider 168 to produce a 25 MHz signal locked in frequency and phase to the 500 MHz source and this together with a signal which varies from 250MHz to DC and back from the amplifier 166 are supplied to a second amplifier and signal processing device 170 for producing markers separated by 25 MHz.

Figure 5 is in many respects similar to Figure 4 except for the down conversion and switched filter which enable the device to operate in the MHz range as well as in the GHz range.

In general a YIG oscillator does not operate reliably much below 2 GHz and consequently for frequencies below 2 GHz the down conversion technique is employed either to enable the overall range of a single instrument to be increased or to permit a low band instrument to be produced.

SUBSTITUTESHEET As shown in Figure 5, the instrument can be used i;ό generate radio 'frequency signals from DC to 8.3 GHz. This is done in two separate modes of operation. Below 2 GHz a hetrodyne principle is employed using a local oscillator operating at 6.3 GHz in the down converter 172 so as to obtain frequencies in the range DC to 2GHz which appear at the RF output 158. Above 2 GHz, the RF signal can be derived directly from the oscillator 148 via the modulator 150 and in this mode the down converter 172 is are effectively removed from circuit. The filter 174 is required to remove other products of the heterodyne mixing above 2GHz.

The switched filter 174 is a device which is arranged to pass the fundamental but remove any harmonics. By its nature it will tend to introduce electrical noise into the signal so that when the filter is switched in, the electrical noise in the RF output signal at 158 will be different from that when the filter is switched out.

In addition to the RF take-off applied to the switched filter 174, there is an RF take-off also in the range DC to 2 GHz which is applied to a hetrodyne 25 MHz IF amplifier to produce marker pulses at 25 MHz intervals using a sampler and 25 MHz local oscillator. This is designated by reference numeral 178 and will be described in more detail with referenc to Figure 10.

The 25 MHz spaced marker pulses from 178 can be compared with the 500 MHZ spaced marker pulses from circuit 166. If there is no offset then it can be assumed that the down converter local oscillator is working correctly. Ideally there should be no offset.

..- t -** a ^j. Ϊ <_» t is. t_* ;£.&T 500 MHz Marker Pulse Generator

Figure 6 indicates in greater detail the construction and operation of circuit 166 of Figure 5.

The sampler or mixer 162 is supplied with two signals. The first is a comb signal of harmonics at 500 MHz intervals derived from a voltage controlled oscillator 164 as will be described in more detail later. This is applied as input ^■ 180.

The second input is derived from the control modulator 150 and is denoted as input 182 to the sampler 162. This signal is essentially the output of the YIG oscillator 148 and as the latter is swept from one frequency to another, all intermediate frequencies will be seen at input 182 and will be mixed with the signals from 180.

The harmonic content of the signal at 180 is sufficient to extend up to the highest of the frequencies at which the YIG oscillator 148 will operate so that as the latter is swept through its entire range, the output of the sampler or mixer 162 will contain beat frequency signals as the frequency of the signal from the YIG oscillator sweeps through each of the harmonic frequencies in the comb signal from 164. The pattern of beat frequencies at each coincidence will follow a similar pattern and the output signal from the sampler 162 will in each case begin at a high frequency sweep down to a very low frequency or even d.c. and then up again as the point of coincidence is passed.

A single marker pulse is derived from the output of the sampler to appear on line L3 for each point of coincidence by first of all amplifying the sampler output in amplifier

SUBSTITU 184, splitting the signal in the output of 184 by means of a power split 186 and feeding some of the signal via buffer amplifier 188 to a low pass filter 190 whose cutoff frequency is approximtely 10 MHz. Two high gain amplifiers 192 and 194 provide a relatively fast rise time rectangular pulse to one input of a differential amplifier 196 the other input of which is provided with a threshold voltage on line 198 from a potentiometer 200 which is preset during manufacture. The action of the differential amplifier 196 is to produce a relatively square pulse for the duration of the amplitude excursion in the output of amplifer 194 which exceeds the threshold voltage set by potentiometer 200. If the low pass filter has a sharp cutoff at 10 MHz and the amplifiers 192 and 194 are wide band amplifiers, the pulse at input 202 of differential amplifier 196 will be relatively steep sided. The width of the pulse will therefore correspond to approximtely 20 MHz and the halfway point along the width of the pulse will correspond to the point of coincidence of the YIG oscillator frequency with the particular harmonic in the comb signal supplied to input 180 to which the marker pulse refers.

A second signal is derived from the output of amplifier 184 which is used to produce the 25 MHz marker pulses between each 500 MHz marker pulse produced by the circuit 170 of Figure 5. To this end the remainder of the signal split by device 186 is amplified in amplifier 204 and passed through a low pass filter 206 having a cutoff frequency of 250 MHz. The filtered output is again amplified by amplifier 208 to appear on line LI. With reference to the previous discussion, the signal entering the low pass filter 206 will be varying in frequency between very high frequencies and approximately DC as the YIG oscillator sweeps through each of the harmonics in the comb signal supplied to the sampler along line 180. The effect of the low pass filter will be to remove frequencies above 250 MHz. It will be seen that since the comb signal is based on 500 MHz and harmonics thereof, the sampler output signal will always contain a component in the range DC to 250 MHz since, considering a rising YIG oscillator frequency, after the YIG oscillator frequency has equalled and begun to exceed the frequency of the nth harmonic in the comb signal 180, the difference signal will begin to increase until, when the YIG signal is halfway towards the (n+l)th harmonic, the difference signal will equal 250 MHz. As the YIG oscillator increases in frequency, the difference signal between it and the nth harmonic will become greater than 250 MHz and will be attenuated by the low pass filter 206 but the new difference signal occurring as a result of beating between the YIG oscillator signal and the (n + l)th harmonic in the comb signal 180, will enter the 250 MHz band and start falling in frequency as the YIG oscillator frequency continues to rise towards the (n + l)th harmonic.

The output signal along line LI will therefore cycle between 250 MHz and a very low frequency or DC and back to 250 MHz as the YIG oscillator frequency sweeps through each of the harmonics in the comb signal 180.

25 MHz IF Amplifier

Figure 7 shows in detail the construction and operation of circuit 170 of Figure 5.

As in the case of the 500 MHz pulse generator 166, the 25 MHz pulse generator of Figure 7 has two input signals. The first is derived from line LI output of Figure 6 and comprises the 250 MHz to DC to 250 MHz varying signal

SUBSTITUTESHEET obtained as the YIG oscillator sweeps through the comb of harmonics. This is applied at input 210 of sampler 212.

The second input is a 25 MHz pulse train obtained from divider 168 (see Figure 5) the construction and operation of which will be described in more detail later. This is applied along line L2 to two amplifiers 214 and 216 to produce a suitable signal for driving a step recovery diode circuit 218 (which will be described in more detail later) to produce a comb of harmonics based on a fundamental of 25 MHz. The characteristic of the diode is selected so as to produce at least 10 harmonics so that signals at 25 MHz intervals up to 250 MHz are obtained. The comb signal is amplified by amplifer 220 and provides the second input to the sampler or mixer 212.

The output of the sampler is amplified by a wide band amplifier 222 and then subject to low pass filtering by a first low pass filter 224 having a cutoff frequency of 1 MHz. The filtered signal is amplified again by amplifier 226 and again filtered by a second low pass filter 228 again having a cutoff frequency of 1 MHz. The filtered output signal is amplified by two amplifiers 230 and 232 to drive a further low pass filter 234 having a cutoff frequency of 400 KHz. The output signal on line 236 thus comprises signals in the range 400 KHz down to zero and back up to 400 KHz again as the frequency bearing signal on line LI sweeps through each of the 25 MHz harmonics in the comb signal from 218.

The signals on line 236 are supplied as one input to a differential amplifier 238 the other input of which at 240 is derived by summing two signals via summing resistors 242 and 244. The action of differential amplifier 238 is to

SUBSTIT produce a generally reactangular pulse for the duration of each cyclic variation of frequency from low pass filter 234 between 400 KHz through zero and back to 400 KHz.

The signal applied to input 245 takes account of the variation of YIG oscillator output with frequency and therefore will tend to fall in value on the YIG sweep frequency increase.

The rectangular pulses so produced appear on line 246 and are centered about frequencies in the rising frequency YIG oscillator output correspond to the harmonics in the comb signal from generator 218. Twenty such pulses will therefore be produced in succession as the YIG oscillator sweeps from one 25 MHz harmonic up to and through the next in the signal from the comb generator 218.

Voltage Controlled Oscillator Circuit

Figure 8 shows in detail the construction and operation of the voltage controlled oscillator circuit of 164 in Figure 5.

This circuit serves to provide a comb output comprising a fundamental at 500 MHz and at least 50 harmonics above 500 MHz each separated by 500 MHz from adjoining harmonics.

A primary signal is generated by an oscillator 248 the frequency of which is determined by a control voltage on line 250 derived from an active feedback loop. The latter will be described in more detail in relation to Figure 9 from which two signals are derived for application at inputs 252 and 254 respectively of a differential amplifier 256. A high pass RC feedback loop 258 is connected between input 252 and the amplifier output line 250 and a second similar RC network 260 is provided between input 254 and earth.

The oscillator 248 is controlled so as to produce a stable 500 MHz signal which is split in a power splitter 262 to provide an input signal to the first of two amplifiers 264 and 266 the output of which comprises a 500 MHz drive signal on the line 268 to a divider circuit (to be described) for producing a lower frequency of 25 MHz.

The other signal from the power splitter 262 is amplified by a chain of amplifiers 270,272,274 and 276, to provide a gain of 27 dB at 500 MHz before the signal is applied to a step recovery diode based comb generator circuit 278. The diode characteristic is selected so as to produce at least 50 harmonics based on the 500 MHz fundamental signal in a comb signal at output 280. The latter provides the input for sampler (mixer) 162 of Figures 5 and 6.

500 - 25 MHz Divider and Feedback Signal Generator for Voltage Controlled Oscillator

Figure 9 illustrates the construction and mode of operation of the divider 168 of Figure 5.

The function of the divider circuit is to produce two lower frequency signals from the 500 MHz output signal 268 of Figure 8. The fist signal (at 25 MHz) comprises the 25 MHz input on line L2 of the 25 MHz marker generator 170 of Figure 5. The second signal at 10 MHz is compared with another 10 MHz signal derived from a crystal controlled oscillator to generate the control signals for the feedback loop generating the voltage control signal for the voltage controlled oscillator 248 described with reference to Figure

SUBSTITUTESHEET 8 .

The 25 MHz output signal is obtained by two stages of division. To this end the 500 MHz signal is divided by 10 in divider 282 to produce a signal at 50 MHz and the 50 MHz signal is divided by two in divider 284 to produce a 25 MHz output signal on line 2.

The second signal is obtained by a third divider 286 to which is supplied the 50 MHz signal. 286 divides by 5 to produce a 10 MHz signal on line 288 which provides one input to a phase detector 290.

A crystal controlled 10 MHz oscillator 292 in a temperature controlled environment (not shown) so as to maintain a very high stability 10 MHz signal provides an output signal which is buffered by amplifier 194 to provide the second 10 MHz input to the phase detector 290. The latter generates signals on lines 296 and 298 for supply to input terminals 252 and 254 of the differential amplifier 256 forming the feedback loop controlling the frequency of oscillation of the voltage controlled oscillator 248 of Figure 8. The phase detector indicates whether the 10 MHz signal on line 288 is increasing or decreasing in frequency and produces feedback signals to control the frequency of the oscillator 248 accordingly.

25 MHz Hetrodyne Amplifier (Figure 5)

Figure 10 shows the construction and operation of the 25 MHz hetrodyne amplifier 178 of Figure 5 by which 25 MHz marker pulses are derived in the low frequency range of operation i.e. d.c. to 2 GHz when the down converter 172 is in operation.

SUBSTITUTESHEET Although 25 MHz spaced pulses are generated by marker pulse generator 170 these are related to the 500 MHz pulses and in the lower frequency ranges (up to 2 GHz) it is not essential for 500 MHz marker pulses to be generated in order to be able to determine the frequency of the YIG oscillator by hetrodyne principles. In the range 0 - 2 GHz, it is merely sufficient to generate 25 MHz spaced marker pulses from 25 MHz up to 2 GHz and this is achieved by the circuit of Figure 10.

The circuit includes two inputs. A first comprises an RF takeoff from the down converter 172 and comprises line 173 of Figure 5. The other input is a signal derived from a crystal controlled oscillator 300 which supplies an accurate frequency signal at 25 MHz along line 302.

The signal on line 302 is amplified by two amplifiers 304 and 306 which drive a step recovery diode comb generator circuit 308 to produce up to 100 harmonics based on 25 MHz in the output signal line 310. Further amplification in amplifier 312 provides the comb signal on line 314.

The signals on lines 173 and 314 are combined in a sampler (mixer) 316 and the output from the sampler appears along line 318. Marker pulses are produced by subjecting the varying frequency signal on line 318 to low pass filtering by a first low pass filter 320 having a cutoff frequency of 1MHz, amplifying the filtered signal in amplifier 322, further low pass filtering in a low pass filter 324 having a cutoff frequency of 500 KHz and further amplification by means of amplifier 326. The pulses so obtained provide one input to a differential amplifier 328 the other input of which is derived from the addition of two signals one from a

.*,_3 _* ^ift**»TfTϋTESWPP potentiometer 330 and the other from a threshold tracking of the voltage source.

The operation of differential amplifier 328 is to produce a rectangular pulse in the output at 332 at each point of frequency coincidence during a sweep of frequency from the down converter with one of the harmonics from the comb generator 308. The effect of the low pass filters 320 and 324 is to control the duration of each pulse so that it starts approximately 500 KHz before the coincidence of the down converter frequency and one of the harmonics in the signal on line 310, to a point at which the down converter signal exceeds the nearest harmonic by 500 KHz.

Since the lowest frequency at which the YIG oscillator will operate reliably is well defined, it is readily straightforward to determine accurately the frequency at the beginning of a sweep by adjusting the YIG oscillator to operate at a frequency just below 2 GHz and which differs from 2 GHz by less than 25 MHz. As the YIG oscillator is increased in frequency the first point of coincidence (25 MHz marker pulse at 332) will correspond to the 2GHz frequency of the YIG oscillator and by counting the 25 MHz markers as they occur so the frequency of oscillation of the YIG oscillator can be determined accurately by reference to the 25 MHz marker pulses. Furthermore since the precise frequency of oscillation of the YIG oscillator can be adjusted within a range of approximately 25 MHz by adjustment of the current flowing in the FM coil so it is possible to adjust the YIG oscillator frequency to any frequency intermediate to 25 MHz ' s markers by first adjusting the main coil current to produce oscillation at the closer of the two markers on one side or the other of the desired frequency, and thereafter adjusting the current to the FM coil by a calibrated amount so as to adjust the YIG oscillator to the desired frequency of operation.

Detector and Detected Signal Amplifier

Figure 11 illustrates in detail the construction of operation of the signal detector shown only basically in Figure 1 at 16.

The detector 334 converts the RF signal transmitted by the device under test (10 in Figure 1) into a low frequency^* signal or d.c. level. This is supplied to an instrumentation amplifier 336 the output of which is further amplified by 338 to provide an output signal the amplitude or d.c. level of which can be digitised by the ADC 18 (not shown in Figure 11) before transmission to the control processor unit 20 and thence to the display drivers.

The signals to be detailed will typically be below 100 microvolts and at these signal levels it is important to compensate for errors produced by voltage offsets produced by amplifiers following the detector 334, and for wide-band noise generated f om within the RF signal source. To this end correction signals are derived by the micro-processor unit 20 (as will hereinafter be described) and after digital to analogue conversion by DAC 340 the coarse signal (for amplification by amplifier 342) and the fine control signal (for amplification by amplifier 344) are combined by mixer 346 for combination with the output signal of amplifier 336.

The current value for the signals supplied from the CPU 38 (Figure 2) are obtained by turning off the YIG oscillator 26 and any other RF source and noting the value of the signal

^SUBSTITUTESHEET V a 348. The processor 38 is programmed to produce two digital values (the coarse and fine feedback signals) to produce a signal at the output of 346 which when combined with the output of 336 reduces V o zero.

The noise introduced by the amplifiers 338 and filters etc will tend to be at a constant level and the wide band noise introduced by the source can likewise be assumed constant for frequency sweeps which do not involve a source change. • However if the sweep covers a number of Bands for each of which the wide-band noise is different, it is necessary to initiate the feedback signal compilation at the beginning of the sweep and at each band/source change.

Since automatic band/source changing can be effected under control of the microprocessor 38, it is a simple matter, provided the RF source and detector and associated amplifier and display(s) are all in the same housing, for the processor 38 to initiate at least a correction signal change at appropriate band/source changes.

The values of the coarse/fine control signals may be derived at the beginning of each sweep and at each band/source change or the values may be computed and stored in a look-up table or memory (not shown) which can be addressed by the processor 38 during a sweep as band and/or source are changed, to provide the appropriate correction signals at the output of 346.

In practice the coarse DAC signal provides a bipolar output voltage to cover the main range of correction and the fine DAC signal provides for the accurate setting of the noise cancelling signal. In Figure 12 there is shown an RF test apparatus having an RF output socket 410 and an input socket 412 between which a device under test 414 is connected via leads 416, 418. A Keyboard 420 power on/off switch and controls 424 enable the user to set up the apparatus to deliver either a fixed frequency RF signal or a sweep signal (which varies in frequency through a preselected range of frequencies) to the device under test 414.

Connected to the input socket 412 (internally) is an RF detector and instrumentation amplifier (not shown) for producing a signal whose magnitude is proportional to at least the amplitude of the RF signal transmitted by the device 414. The magnitude is displayed by a trace or bar graph (or the like) against frequency, in a display (typically a CRT based display) 426. Further displays may be provided as at 428, 430 to indicate eg digitally the start and stop frequencies of the range of frequencies applied to the device 414.

Also within the housing (but not shown in Figure 12) is a microprocessor based control unit and power supply means for the RF source and detector, processor and amplifier circuits and the display(s), details of which can be obtained by reference to the foregoing description in respect of Figures 1 to 11.

Most importantly the unitary mounting of the devices making up the test apparatus aforesaid enables feedback data to be supplied from the detector and the RF source to the control unit to enable control and correction signals to be generated by the microprocessor for supply to the detector and amplifier to compensate for different electrical noise levels due to range and mode changes in the RF source, thereby enabling a greater consistency of sensitivity to be obtained over the swept ranges of frequency than would otherwise be the case.

General description of operation of system under software control

The frequency source (YIG) 148 is designed to sweep from a start frequency "FI" to a stop frequency "F2" and the microprocessor based control unit is programmed accordingly, see section below entitled "Microprocessor programming" .

As mentioned the source frequency is controlled by four DACs. Start DAC 116 on the main coil, Width and Ramp DACs 118 and 128 combined on the main or FM coils, and error DAC 124 on the FM coil. For a normal sweep from "Fl" to "F2", the source is controlled by the Start, Width and Ramp DACs. The Error DAC is used to fine tune the start frequency "Fl" and any adjustment made here will also affect all points within the swept frequency range.

The Start DAC is used to set the sweep centre frequency Fl, the Ramp DACs is set to its ramp start value, the Width DAC is set accordingly and the Error DAC is set to give no contribution. The stop frequency "F2" can be obtained by sweeping the Ramp DAC from its start value to its stop value. When the Ramp DAC is at its start value, the source frequency should be at "Fl". If not, it is possible to finely adjust the frequency to "Fl" using the Error DAC (NB this would also adjust "F2" by the same amount) .

Accuracy for the above operations is obtained using two sets of hardware generated markers occuring at fixed intervals such as 25MHz. Knowing the position of these

SUBSTITUTE SHEE markers means that all the DACs can be calibrated in terms of so many bits per frequency. This is covered in greater detail under the headings of "Calibration" and "Operation" below. The software assumes a specification for the markers, coupled to the ability of the hardware to reliably detect the markers.

In dual band instruments, there are two sets of 25MHz markers, one for each band, and one set of 500MHz markers generated in the YIG band.

2.1 Typical frequency ranges

For simplicity reference will be made to a range of oscillators to be supplied by the Applicant, by reference to the Type numbers to be allocated thereto by the Applicant.

Type Band start Band stop Centre DAC resolution (12 bit)

5407 1.0 MHz 1000 MHz 243 kHz/bit

5409 10.0 MHz 2000 MHz 485 kHz/bit

5411 5.0 MHz 3000 MHz 731 kHz/bit

5417 10.0 MHz 8.4 GHz 1.56 MHz/bit

5419* 2.0 GHz 8.4 GHz 1.56 MHz/bit

5428 8.0 GHz 12.4 GHz 1.07 MHz/bit

5430 12.4 GHz 20.0 GHz 1.85 MHz/bit

5431 10.0 GHz 16.0 GHz 1.46 MHz/bit

5436 17.0 GHz 26.5 GHz 2.32 MHz/bit

5437 2.0 GHz 20.0 GHz 4.39 MHz/bit 5447*10.0 MHz 20.0 GHz 4.39 MHz

* indicates dual band instrument.

For Het (low) band frequencies ie frequencies less than 2GHz

SUBSTITUTESHEET on Types 5417 and 5447 and all frequencies on Types 5407, 5409 and 5411), the source output is obtained by shifting the YIG frequency down using a down-converter. Those types having a 10MHz-8.4GHz range (Types 5417 and 5447) require a down-converter with a 6.3GHz local oscillator and while the 5407, 5409 and 5411 Types use a down-converter with a 10GHz local oscillator.

The 5437 and 5447 Types used a YIG oscillator with two oscillator elements. One covers the range 2GHz-8.4GHz and the other covers 8.4GHz-20GHz. It is of course necessary to ensure that the correct oscillator element is active.

The Start DAC resolution is quoted, as this specifies to what accuracy it is possible to point to any given frequency, using the main coil only. This is especially important when finding 500MHz markers (or 75MHz markers) .

2.2 Useable sweep frequencies

The user is allowed to sweep from a fixed amount below "Band Start" to a fixed amount above "Band Stop" (BS) .

If BS is below 10MHz, min Start = BS

If BS is above 10MHz, min Start = (BS-lOMHz)

Max stop = (BS + 10MHz) which is limited by the software, since it is necessary to be able to reach 500MHz or 75MHz markers on or above Upper Band end (UBE) using Width DAC when on main coil, with Ramp DAC set to Ramp Stop value) .

2.3 Sweep accuracy

Start accuracy:

SUBSTITUTESHEET - will lock to specified frequency +/- 200kHz

- RF models +/- lOOKHz

- (in most cases with both channels off, this is seen to be better than +/-50kHz)

Step accuracy:

- corrected in software, but not specified.

2.4 Marker specifications

These are the limits within which the software will operate.

25MHz:- repeated every 25MHz width 0.8MHz (min) to 1.2MHz (max) must be symmetrical about 25MHz centre frequency

if marker profile has a hole in the middle, then the marker skirts should be greater than 500kHz and the hole in the middle should be less than 500kHz.

75MHz:- repeated every 75MHz width = 3.0MHz (min) to 5.0MHz (max) must be symmetrical about 75MHz centre frequency.

500MHz:-repeated every 500MHz width = 7MHz (min) to 20MHz (max)

(symmetrical about each 500MHz marker) for multiband units (ie 5437 and 5447) the min. width of 10MHz must be symmetrical around each 500MHz marker centre frequenc . 2.5 YIG main coil software set up

With the "Width" "Ramp" DAC set-up to give no contribution, it is necessary to be able to move source frequency using "Start" DAC only, over the following range:

Start DAC source frequency range required

minimum Band start -350MHz to -150MHz

maximum Band stop +50MHz to +350MHz

RF models

minimum Band start -110MHz to -30MHz

maximum Band stop +30MHz to +110MHZ

^SUBSTITUTESHEET 2.6 YIG FM coil software set-up

By moving only one DAC at a time, the following frequency ranges need to be covered:

Width & Ramp DACS -23MHz to +23MHz (min)

(max) (0 - 10V)

Error DAC -23MHz to +26MHz (min)

(min to max)

The Error DAC must always be able to "see" at least two 25MHz markers otherwise it is impossible to define the scalar that allows movement by 25MHz.

3.0 Calibration

There are four DACs used to control the YIG frequency. These are:

(a) the Start DAC which controls the main coil,

(b) with Width DAC which scales the signal from the Ramp DAC, and which controls either the Main or FM coil,

(c) the Error DAC which controls the FM coil only which can modify the frequency by +/- 25MHz, and

(d) the Ramp DAC which moves the Width DAC output from = to "width".

Calibration is used to determine scaling factors (bits/frequency) for all the DACs, to allow swept frequency conditions to be set-up accurately. When a DAC is being swept and a marker is being looked for, it is possible to build a profile of the DAC in terms of the type of marker looked for. The DAC profile is a data array, where each member represents a DAC value and this member will hold a value denoting the presence or absence of a marker, for this DAC value.

In a preferred system, all DACs are 12 bit (ie they can have values in the range OOO to OFFFH) . They are calibrated on the specified coils in the following order using 500MHz or 75MHz (depending on model) and 25MHz hardware markers previously defined.

For the duration of calibration, RF power is forced on regardless at a minimum level (0 dBm) , to ensure that hardware markers are generated correctly.

When searching a DAC profile for a marker the following procedure may be used.

Look for start of marker.

When found, step through profile to jump over the marker. (For 500MHz markers jump 25MHz, for 75MHz markers jump 10MHz and for 25MHz markers jump 5MHz) .

Having jumped over the marker, then search back through the profile looking for the other edge of the marker.

Having found both marker edges, the centre point of the marker can be determined since the centre is half way between the marker start and stop.

3.1 Start DAC on main coil

Determine position of all 500MHz markers (or 75MHz markers) within swept frequency range. This allows the Start DAC to be accurately set up when changing frequency parameters.

Build up a table of approximate DAC values for all 500MHz (or 75MHz) marker positions knowing the Start DAC maximum value and full frequency range including any undershoot and overshoot. With no contribution from any other DAC (Width=0, Error=800H) and with the CW filter out, sweep the Start DAC from 200MHz below the estimated position of the first marker through to 200MHz above the estimated position of the last marker, building a DAC profile of all the 500MHz markers (or 75MHz markers) . If a switched filter is fitted (5417 and 5419 types) it must be switched to the highest band, so that the source can be monitored if necessary while calibrating.

Search the profile from the high frequency end looking for three markers, checking marker width is within specification. Out of the three markers found, test for two markers greater than approximately 400MHz (60MHz for 75MHz markers) but less than 600MHz (90MHz for 75MHz markers) apart. Using these two markers, the exact DAC value for 500MHz (or 75MHz) can be determined.

Search the rest of the profile for all other markers, where the centre of each marker should be between 400MHz (60MHz for 75MHz markers) and 600MHz (90MHz for 75MHz markers) away from the previous one.

If no marker is found, store a position 500MHz (75MHz) away from the previous marker. (This 500MHz (75MHz) spacing is derived from the spacing between the first two good markers) . A spurious marker or sub-size marker in the right position will be noted as a marker but an error flag may be set to show there was a size problem. The result will be a table of Centre DAC values against multiples of 500MHz (75MHz) within a permitted range of source frequency.

In multiband units (ie 5437 and 5447), the Start DAC is calibrated differently. With no contribution from any other DAC (Width=0, Error =800H) and with the CW filter "out", sweep the start DAC from 200MHz below the estimated position of the first marker to 200MHz above the estimated position of the last marker, building a DAC profile of all the 500MHz markers. This sweep is done with the YIG high band selected and the switched filter set to the highest band.

Search the profile from the high frequency end looking for three markers as above.

Having found two markers 500MHz apart, the profile can be searched for all other 500MHz markers. This produces the

Start DAC values for all 500MHz markers in the YIG high band.

With the YIG now set up to operate in its low band and the switched filter set to operate in its highest band within the YIG low band, sweep the YIG from 200MHz below the first marker to approximately 250MHz above the first marker in the high band, where position has been found as previously described. The markers previously found in the high band should be left in the profile. Search the profile from the high frequency end again looking for three markers as above. Having found two markers 500MHz apart, the profile can be searched fo all other 500MHz markers. The result is a set of Start DAC values for all the 500MHz markers across the full frequency range of the instrument.

If no markers are found, the Start DAC can still be set to approximately the right frequency as the default values are calculated for all the marker positions.

Start DAC scalar value is determined using the highest and lowest frequency 500MHz (75MHz markers). This is defined as the change in Start DAC value required to move the YIG oscillator through 500MHz (75MHz).

3.2 Error DAC on FM coil

In order to permit accurate adjustment of the source frequency using the FM coil, it is necessary to determine the change in Error DAC value to move 25MHz on the FM coil.

Calibration is possible only if 500MHz (75MHz) markers have previously been found. If not a default value for 25MHz is used. With no contribution from any other DAC (Width=0, Error=800H) and with the CW filter out, use the Start DAC calibration figures to set the Start DAC to point to mid range 500MHz (75MHz) marker, ie the marker at or below the mid range frequency given by:

(Band Start + Band Stop)/2.

If a switched filter is fitted as in Types 5417, 5419, 5437, 5447 it must be switched to the highest band.

SUBSTITUTESHEET In a multiband unit it is important to ensure that the correct YIG frequency has been selected.

With the CW filter in, sweep the Error DAC over its full range from minimum value to maximum value and back again.

While sweeping, build up a profile of 25MHz markers.

Search the profile from the low frequency end for at least two markers possibly three, checking that each marker width is greater than approximately 500KHz.

Out of the possible three markers found, test for two markers greater than 20MHz but less than 30MHz apart.

Using these two markers, it is possible to determine the exact DAC value for 25MHz.

This is the FM Error sealer, defined as the change in Error DAC value required to move the YIG through 25MHz at the calibration frequency.

3.3 Width DAC on main coil

Determine the position of all the 500MHz (or 75MHz markers) within the swept frequency range, using Width DAC with the Ramp DAC set to its ramp stop position. This allows the Width DAC to be accurately set up for all width frequencies.

An identical technique is used as in Start DAC calibration, the only difference being that the Start DAC is set to 0, the Ramp DAC is set to its ramp stop value (ie the largest value within its range that can be exactly divided by 400, to allow a 401 point sweep to be actioned) and the Width DAC is swept over its complete range.

The initial table of approximate DAC values for marker positions is a direct copy of the Start DAC marker positions as the Start DAC and Width DAC cover very similar frequency ranges.

The only difference is on multiband units. With no contribution from any other DAC (Start=0, Error=800H, Ramp=ramp stop) and with the CW filter out, sweep the start DAC from 200MHz below the first marker through to 250MHz above the first marker in the YIG high band, building a DAC profile of all the 500MHZ markers. Perform this sweep with the YIG low band selected and the switched filter set to its highest band within the YIG low band.

Search the profile from high frequency end looking for three markers as before.

Having found two markers 500MHz apart, the profile can be searched for all other 500MHz markers.

The result should be the Width DAC values for all 500 MHz markers in the YIG low band and the first marker in the YIG high band.

With the YIG now set up to operate in its high band and the switched filter set to its highest band, sweep the YIG from 250MHz below the first marker in the YIG high band, as previously found, to the maximum DAC value.

The markers previously found in the low band should be left in the profile.

SUBSTITUTESHEET Search the profile from the low frequency end looking for three markers as above. After two markers 500MHz apart are found the profile should be searched for all other 500MHz markers. Should now have width DAC values for all 500MHz markers across the full frequency range of the instrument.

The markers are found in the low band first since the Start and Width DAC values for these markers will be very similar.

At the higher frequency range, ie large DAC values, there is no guarantee that the DAC values will be similar for the same frequency, since the Ramp DAC at its ramp stop value does not provide the Width DAC with exactly the same reference voltage as that provided to the Start DAC. Also, since DACs are multiplying DACs, the errors will increase with DAC value.

3.4 Width DAC on FM coil

In order to allow the Width DAC to be set up for an FM coil sweep, it is necessary to determine a DAC value that gives a width of 40MHz on the FM coil. This allows the Width DAC to be set up for as FM coil sweep when changing the frequency parameters. This can be used for sweep widths less than 40MHz to get lower residual FM and greater width accuracy.

Only calibrate if 500MHz markers (or 75MHz markers) previously found, else use default value. With no contribution from any other DAC (Width=0, Error=800H) and with the CW-filter out, set Start DAC to point 12.5MHz below mid-range 500MHz (or 75MHZ) marker as previously defined in Error DAC calibration.

Ensure Width DAC is set up to drive the FM coil.

If switched filter is fitted (as in models 5417, 5419, 5437 and 5447), it is important to ensure that it is switched to the correct band.

With the CW filter in, set the Ramp DAC to the ramp stop value.

Sweep the Width DAC from minimum value to maximum value and back again.

When sweeping build up profile of 25MHz markers.

Search the profile from the low frequency end for at least two markers, checking marker width is within specificatio .

Out of the markers found, test for two markers greater than approximately 20MHz but less than approximately 30MHz apart.

Using these two markers, can determine exact width DAC value for 25MHz when Ramp DAC is set to the ramp stop value. Knowing the Width DAC value for 25MHz, it is possible to multiply this value to get a Width DAC value for 40MHz. This width DAC value is known as the FM Width Scalar.

3.5 Het band calibration (for low and dual band instruments) The accuracy of the down converter local oscillator can be checked by checking the offset of the HET band 25MHz markers from a YIG band 500MHz marker. Ideally there should be no offset.

Check 25MHz marker pack by calibrating Error DAC on the FM coil.

Calibration is only possible if 500MHz markers have previously been found.

With no contribution from any other DAC (Width=0, Error=800H) and with the CW filter out, set Start DAC to point to nearest YIG band 500MHz marker below the HET band mid-range frequency. YIG band 500MHz markers do not occur at multiples of 500MHz in the HET band since the down converter frequency shift is not a multiple of 500MHz.

Ensure switched filter is switched to HET band.

With the CW filter in, sweep Error DAC over its full range from minimum value to maximum value. When sweeping, build up profile of 25MHz and 500MHz markers.

Search the profile for a 500MHz marker and then for at least two, possibly three, 25MHz markers. Out of the possible three 25MHz markers, test for 2 markers greater than 20MHz but less than 30MHz apart. Using these two markers, it is possible to determine the exact DAC value for 25MHz. If this value for 25MHz is between the values calculated for 20MHz and 30MHz from the YIG band Error DAC calibration, it can be assumed that the HET band 25MHz marker system is functioning correctly. Search for the 25MHz marker which is closest to the 500MHz marker and determine the difference (if any) in DAC values. Using a DAC value for 25MHz, the frequency difference between the 500MHz marker and the closest 25MHz marker can be determined.

If this frequency is greater than 5MHz, then the local oscillator in the down-converter is not functioning correctly. In this connection, if the local oscillator is more than 12.5MHz out of specification, it is possible to lock to the wrong 25MHz marker.

4. Software set-up operations

These can be split into the following sections.

1. Major mode change - this happens any time a frequency related parameter is changed. It involves accurately setting up all the DACs for the selected frequency range(s) , using calibration data and performing multiple locks and searches for markers (25MHz and 500MHz) .

2. Retrace and Prepare Sweeper - this ensures that the correct frequency information is being used for the next sweep, and that the YIG is at the correct frequency before starting to sweep.

3. Sweep control - this ensures that DACs are set up correctly for each data point and controls band changes in dual band units.

4. Error locking - this involves finely tuning the YIG oscillator to a specified frequency using the error DAC

SUBSTITUTESHEET and the 25MHz hardware markers. (Used in "Major mode" change and "Prepare Sweeper" sections) .

4.1 Major mode change

This ensures accuracy by checking Start and Width DAC values, by locking to 500MHz and 25MHz markers where necessary. This has to be done, because calibration is only performed for one set of frequencies. It is necessary to accurately calibrate the DACs for the current sweep frequencies. This is achived in a number of stages. There are various differences between main coil mode and FM coil mode.

mode conditions (sweep width)

main coil greater than 40MHz, CW filter out

FM coil less than/equal to 40MHz, CW filter in

The above modes are valid even in CW mode with both channels turned off.

In a dual band instrument, a sweep covering the HET and YIG bands is validated as two individual sweeps occurring one after the other. If alternate sweep is also selected, it is possible to end up validating up to four individual sweeps. In a dual band instrument, steps 4.1.2 to 4.1.7 (with the exception of step 4.1.4b) should always be carried out in the YIG band. This is because the Width DAC validation is done using 500MHz markers and to use an accurate centre frequency, 25MHz markers are needed that correspond exactly to the 500MHz markers. These only appear in the YIG band, as the HET band 25MHz markers can be offset from the 500MHz markers due to the different frequency sources.

A Major mode change is always carried out with the CW filter switched out.

4.1.1 For each sweep to be validated, it is important to check the sweep mode and ensure that the Width DAC is set up to drive the correct coil. If a switched filter is fitted, it is necessary to ensure that the highest band filter is selected - this is always in the YIG band.

4.1.2 With no contribution from any other DAC ( idth=0, error=800H) , the oscillator can be locked to the Start frequency using 500MHz markers and Start DAC.

Determine the two nearest attainable 500MHz (75MHz) markers to the band start frequency.

If the stop frequency is not an integer multiple of the marker frequency, the RF models can always access the next marker up, and on all other units, if the nearest marker would be the next one up, then that can be accessed.

If band start frequency coincides with a marker, look at the marker at the start frequency and the next marker up.

If the band start frequency is less than the lowest marker frequency, look at the lowest marker and the next one up.

From power-on calibration, the Start DAC values are known for all the 500MHz (75MHz) markers. This allows the Start DAC to be moved approximately 50MHz (30MHz) below the 500MHz (75MHz) marker calibration position, and then sweep the Start DAC to approximately 50MHz (30MHz) above the marker building a profile of the 500MHz (75MHz) marker. From the marker profile we can determine the exact centre of the 500MHz (75MHz) marker. This can be done for r the two nearest 500MHz (75MHz) markers, and the calibration table of Start DAC marker positions for these two markers, can be updated.

Knowing the positions of these two 500MHz (75MHz) markers, we can determine the Start DAC value for the required frequency. The absolute position of the nearest marker is known, and the Start DAC value to move 500MHz (75MHz) can add or subtract fractions of 500MHz (75MHz) to reach the start frequency. Set the Start DAC to the appropriate position.

4.1.3 Without changing any other DAC, relock to the sweep Start frequency using the markers and the Error DAC, recalculating the FM error scalar at the same time.

The error locking process as described below in section 4.4 may be used.

4.1.4a For a main coil sweep with more than one data point in the sweep, the Ramp and Width DACs can be used by moving to the sweep stop frequency and locking to at least one 500MHz (or 75MHz) marker, to validate the Width DAC setting.

Determine the two nearest attainable 500MHz (75MHz) markers to the band stop frequency. If the stop frequency is not an integer multiple of the marker frequency in the RF models, it is always possible to access the next marker up, and on all other units, if the nearest marker would be the next one up, then that can be accessed.

SUBSTITUTESHEET If the band stop frequency coincides a marker, then look at the marker at the stop frequency and the next marker up.

If there are no marker frequencies between the band start and stop frequencies, then only the marker above the band stop frequency is used.

If there are no marker frequencies above the band stop frequency, an attempt should be made to use the nearest two markers below the band stop frequency, both being between the band start and band stop frequencies.

If only one marker exists, then that one should be used.

From power-on calibration, the Width DAC values for all the 500MHz (75MHz) markers can be calculated relative to the band start frequency. This allows the Width DAC to be moved to approximately 50MHz (30MHz) below the 500MHz (75MHz) marker calibration position, and then swept to approximately 50MHz (30MHz) above the marker, building a profile of the 500MHz (75MHz) marker.

From the marker profile the exact centre of the 500MHz (75MHz) marker can be determined. This can be the nearest one or two 500MHz (75MHz) markers.

This should be done with the Ramp DAC set to its ramp stop value, and the Start and Error DACs set to the values determined above in sections 4.1.2 and 4.1.3,

Knowing the positions of the two 500MHz (75MHz) markers, the Width DAC value can be determined for the required stop frequency. The width frequencies and DAC values required to get to the markers, and the Width DAC value required to move 500MHz (75MHz) are known so that appropriate fractions of 500MHz (75MHz) can be added or subtracted to reach the stop frequency.

If only one marker can be locked to, the Width DAC value for the required stop frequency can still be determined since the Width frequency required to get to the marker is known so that the DAC value can be scaled up or down to achieve the stop frequency.

It is best to use two markers where possible, as the linearity of the YIG can vary across its frequency range ie the DAC value to move 500MHz from 2GHz might not be the same as that to move 500MHz from 5GHz.

4.1.4b From an FM coil sweep with more than one data point in the sweep, the calibration values obtained for the Error DAC scalars, and the value for the FM Error scalar obtained when error locking in section 4.1.3 can be used to calculate the FM Width scalar and set the Width DAC to an appropriate value.

4.2 Retrace and prepare sweeper

This involves completing the following operations.

Ensure that the CW filter is set correctly.

Check Width DAC is connected through to correct coil.

If a dual band sweep, check and note the band changeover data point. Check Start and Width DACs are set correctly; check Ramp DAC is set correctly.

Check switched filter (if fitted) is set correctly.

When all the previous checks have been completed, it is possible to lock to the sweep start frequency. The procedure for this is listed in section 4.4 below.

4.3 Sweep control

This ^"involves moving the source onto the frequency for the next data point. In most cases this will involve incrementing the Ramp DAC and checking that the switched filter (if fitted) is set to the correct band.

In a dual band sweep, it is necessary to check each new data point to see if this will move the instrument into the YIG band or a new YIG band. If the band is changed, ensure the Start, Width and Ramp DACs are set correctly for the new band and also ensure that the measurement system uses the appropriate noise compensating (auto-zero) data for the new band. As well as sorting out the switched filter, also lock to the frequency of the first data point in the appropriate band, again using the procedure listed in section 4.4 below.

In a multiband unit, when changing from the YIG low band to the YIG high band, only lock at the start of the YIG high band for the first few sweeps after a major mode change. After locking, store the difference in Error DAC values for the YIG low band start lock and the YIG high band start lock.

SUBSTITUTESHEET When not locking at the start of the high band, the Error DAC value required can be calculated by adding the difference value to the lock value just obtained for the YIG low band.

4.4 Error locking

This involves locking to a frequency using 25MHz markers and the Error DAC.

There are two types of error lock possible;

(a) slow lock, and

(b) fast lock.

Slow locking is always used for the calibration and major mode change sections.

For normal run time locking, slow locking uses three complete sets of sweeps and providing there are no locking problems, fast locking is used thereafter.

A major difference between slow and fast locking is the frequency range swept by the Error DAC. Slow locking sweeps over the complete range of the Error DAC, while fast locking only sweeps over approximately 16MHz.

Error locking is disabled if:

(a) no 500MHz markers are found in calibration and/or

(b) the RF power is turned off.

Before locking, it is assmued that the selected frequency will be close to that produced by a value of 800H on the Error DAC. This is because the YIG is positioned as accurately as possible at the selected frequency by the Start and Width DACs with no contribution from the Error DAC. It also means that the frequency can easily be corrected by +/- 12.5MHz without worrying about running out of range on the DAC.

For Start frequencies less than 25MHz, the Start DAC is set up for a frequency of 25MHz, with the Error DAC set to mid-range. Using an Error DAC centre value of 25MHz allows the Start frequency to be locked, but still enables the Error DAC to be swept over two 25MHz markers to allow the local FM Error DAC scalar to be determined. The Error DAC has a range of approximately 60MHz.

Slow Locking

4.4.1 When presented with a frequency to lock to, determine the frequency offset (if any) from the nearest 25MHz marker and whether nearest marker is above or below selected frequency. Knowing the approximate Error DAC value to shift the oscillator through 25MHz, calculate an approximate Error DAC value for a frequency mid-way between the two nearest markers.

If the selected frequency is below 25MHz, the closest marker will be at 25MHz and the second marker will be at 50MHz.

If the selected frequency is below 50MHz it is necessary to determine an approximate Error DAC value for 15 MHz. This is necessary when the Error DAC is swept, because the lowest frequency marker normally looked for is at 25MHz

SUBSTITUTESHEET and starting to sweep from 15MHz should give enough leeway to find this marker.

4.4.2 Sweep the Error DAC across its full range, building a profile of all available 25MHz markers, ensuring that when sweeping the DAC is never taken down below 15MHz, using the DAC value determined in section 4.4.1 above.

Starting at the sweep start value (either 0 or 15MHz value), sweep the Error DAC up to a Stop value (in this case FFF) , and then back again, building a profile of 2MHz markers as detailed below.

Step DAC forwards in large steps of approximately 210KHz. At each point, look for the presence of a 25MHz marker.

If no marker is detected continue sweeping in large steps.

If a marker is detected, take another large step and if a marker is again detected, go back two steps to ensure the system is at a frequency where a marker is not detected.

If a marker not detected on the second large step, set byte in profile to show that a spurious marker has been found, and continue to step DAC forwards in sweep in large steps.

Having found two repetitive occurences of a marker and stepped back two large steps, step back another two large steps if this is possible without going below the start point, to find the exact start point of the marker. Wait a short while for the YIG to settle. Step forwards through the sweep again but this time in small steps of

SUBSTITUTESHEET approximately 25KHz looking for the marker.

If the marker is found, set byte in profile and step DAC forwards again in small steps.

If marker not found, increment "marker not found" count, and step DAC forwards again in small steps.

If 32 small steps are taken without a marker being found (ie the system has gone past the trailing edge of the marker) , revert to stepping forwards through the sweep in large steps again looking for markers.

Continue to step forwards through the sweep until the stop value is reached or a value is reached such that if another step is taken, it would exceed the stop value.

Sweep the DAC back down to the start value in large steps looking for markers in the same manner as when sweeping up. Again when a marker is found use the same procedure as when sweeping up the DAC range, remembering that stepping back from the marker involves moving up in frequency, not down. It is still necessary to ensure that the system does not go below the start value or above the stop value.

This will produce a profile of all 25MHz markers occuring between Error DAC start and stop values. It will also provide a record of where spurious markers were found, but these are ignored.

4.4.3 Starting from the mid-way DAC value calculated in 4.4.1 above, search the profile down in frequency until the first 25MHz marker is found. Again, starting from the same DAC value, search the profile up in frequency until the first 25MHz marker is found.

When searching the profile for markers, find one edge first, jump over the marker and search back the other way for the second edge, and split the difference between the two edges to find the marker centre.

4.4.4 Test the DAC values of the marker centres found. If a marker is found on the edge of the profile, then another marker is searched for on the other side of the marker that was found. Once two marker values are obtained, update the value of the FM Error scalar (Error DAC value to move 25MHz) . Compare this with the value from the Calibration step to check for valid result.

4.4.5 Using the DAC value for the nearest marker to the selected frequency, the updated value of FM error scalar and the offset of the selected frequency from the marker, allows the Error DAC value to be determined for the selected frequency.

Fast locking

4.4.6 To be able to do a fast lock at a specific frequency, several slow locks with the same sweep conditions must first have been performed. From the last slow lock with the same sweep conditions, a DAC value exists for the nearest marker to the selected frequency, as determined in section 4.4.1. Using this marker DAC value, the range over which the Error DAC is to be swept can be determined. Ideally the system should be swept from approximately 8MHz below the marker position from the last slow lock, to approximately 8MHz above.

SUBSTITUTESHEET 4.4.7 Sweep the Error DAC across the limited range set-up in 4.4.6 above, building the profile of the 25MHz markers using the same procedure as in section 4.4.2.

4.4.8 Search the profile for a 25MHz marker. Find one edge first, jump over the marker and seach back the other way for the second edge. Split the difference between the two edges to find the marker centre.

4.4.9 Using the DAC value for this marker, the latest value of the FM error scalar from last slow lock with the same sweep frequency conditions and offset of selected frequency from the marker, allows the Error DAC value for the selected frequency to be determined.

4.5 Stop Locking

This is a special type of error lock. It is only done at the end of the first sweep after a major mode change. If in alternate mode, on a multiband unit, with each sweep crossing several bands, a stop lock should be performed at the end of each band on both channels.

When a major mode change has been finished, the Start DAC with no addition from any other DAC approximates to the start frequency. With the Ramp DAC set to its ramp stop value, the Width DAC approximates to the stop frequency.

At the start of every sweep, the start frequency is corrected by doing slow error locks following later by fast error locks.

To ensure that the stop frequency is accurate, the process should be performed at the end of a first sweep.

This involves doing a slow Error lock at the stop frequency, as at the start, and determining the amount of correction required to be added/subtracted to the Error DAC setting to give the accurate stop frequency. Do the stop lock at the end of the first sweep rather than during the major mode change, as the YIG will be moving at its normal sweep speed.

Having determined the amount of error correction required at the end of a sweep, this can be related back to the Start frequency Error correction, since the Stop frequency Error DAC value = the Start frequency Error DAC value + X (where X can be positive or negative) .

The correction X can be progressively applied across the sweep.

As a range is swept from start to stop, the Error DAC value is modified by X/(number of steps in the band), so in effect the Error DAC is swept over a very limited range as the Ramp DAC is swept.

Calibration of a YIG oscillator RF source may be rendered more simple if the DACs controlling the frequency determining currents to the Main and Fine coils of the YIG oscillator are preset so that the full scale sweep of the YIG oscillator is just greater than and thereby overshoots the extremes of the calibration range at both ends thereof.

Thus if the calibration range is 2.0GHz to 20GHz the microprocessor generated signals for the DACs are arranged

SU to cause the YIG to sweep in frequency from say 1.9GHz to 20.1GHz. Starting at the lowest YIG position, and altering the DAC signals to produce an increasing frequency of oscillation means that the first frequency coincidence of the YIG output with and of the harmonically related coarse calibration 500MHz related markers will be with the fourth harmonic of the 500MHz fundamental of the marker comb (ie 2.00GHz). Likewise at the other end of the overall sweep, if the YIG is driven to its highest controlled frequency (20.1GHz), the first harmonically related coarse calibration (500MHz related) marker to be "seen" as the YIG oscillator frequency is decreased, will be the 40th harmonic (based on the 500MH comb fundamental) ie the 00GHz component of the comb.

By building in these calibration precursors, so preliminary calibration of the oscillator using the coarse comb of markers can be run simply and reliably by driving the YIG oscillator to one precursor or the other and then increasing or decreasing the frequency by appropriate control signals under microprocessor control.

Microprocessor programming

Programming of the microprocessor to perform the tasks described herein should present no problem to a skilled programmer but for completeness reference is made to the source code listings deposited in the UK Software Registry by the applicant company under the following registrations:

No. Title

910606001 3JDEF . INC and others

SUBSTITUTE SHEET 910606002 DATAQ.ATM and STEI A.ASM 910606003 3J010PLA1

filed on 6th June 1991.

These source code listings defie the programmes which may be stored in EPROM (not shown) in the processor control unit or entered into RAM (not shown) on the processor control unit, by downloading from a disc or tape or the like.

Claims

1. An RF source for generating RF signals by which components can be tested, which comprises a master oscillator, coarse and fine tuning controls, and circuit means for generating two sets of harmonically related markers for calibration, a low resolution set for coarse calibration and a higher resolution set (separated by smaller frequency intervals) for more accurate calibration, and signal generating means for producing control signals for operating the coarse and fine tuning controls, the values of the control signals being determined by reference to the harmonically related markers and the displacement of the desired frequency at which the master oscillator is to oscillate from the frequency of at least the nearest marker.

2. A method of setting up an RF source as claimed in claim 1, to oscillate at a particular frequency F comprising the steps of:

(1) calibrating the oscillator using the coarse calibration markers,

(2) using this calibration to generate a control signal for the coarse tuning control to enable the oscillator to oscillate somewhere in the range (F +_ f) (where 2f is the resolution of the coarse calibration) ,

(3) calibrating the fine tuning control of the oscillator using the high resolution calibration markers between two coarse calibration markers, for frequencies in the range (F + f),

(4) using the high resolution calibration markers to determine the value of a signal to be applied to the fine tuning control of the oscillator to adjust the oscillator frequency to the desired frequency F, and

(5) applying the coarse and fine control signals thereby generated to the coarse and fine tuning controls respectively, to obtain the desired frequency of oscillation F.

3. A method as claimed in claim 2, wherein the coarse calibration is performed by digitising the coarse frequency controlling signal SC over the complete range of the oscillator, storing digital values of the signal SC when the frequency of the latter coincides with each one of the coarse calibration markers, and using the stored values and extrapolating between adjacent marker control signals to generate a control signal to cause the oscillator to oscillate nominally at the desired frequency within a range +f of the desired frequency.

4. A method as claimed in claim 3, wherein the fine calibration is performed by digitising the fine frequency controlling signal between two fine calibration markers, one or either side of the frequency at which the oscillator is actually oscillating and in the range (F +_ f) , storing the digital values of the signal when the frequency of the latter coincides with the high resolution calibration markers within the defined range, using the stored values and extrapolating between adjacent fine control signal markers, generating a fine control signal

SUBSTITUTESHEET value which if applied to the fine tuning control of the oscillator will shift the frequency of oscillation from that determined by the previously computed coarse control signal, by an amount such as will cause the oscillator to oscillate at the desired frequency F.

5. A method as claimed in any one of claims 2 to 4 wherein the coarse calibration of the oscillator is achieved by sampling at 4096 points throughout the range of frequencies produced by the oscillator.

6. A method as claimed in any one of claims 2 to 5 wherein the more accurate fine calibration of the oscillator is achieved by sampling at 4096 points between the two high resolution calibration markers located on either side of the frequency of oscillation set up by the coarse frequency controlling signal.

7. A method as claimed in any one of claims 2 to 6 further including the step of altering the control signal for at least the coarse frequency control of the oscillator so as to first of all increase the oscillator frequency and sweep the latter from the desired frequency F up to a higher frequency and then back again by reversing the change in the frequency controlling signal, so as to revert the frequency controlling signal to its start value, thereafter checking the frequency of oscillation of the meter using at least the high resolution calibration markers, and effecting such further adjustment as is necessary to at least the fine frequency determining control signal so that the latter is changed to bring the frequency of oscillation of the master oscillator to the desired frequency F at the end of the sweep.

SUBSTITUTESHEET

8. A method as claimed in any one of claims 2 to 7 when performed at regular intervals of time during the operation of the RF source so that corrections are made to the frequency controlling signals applied to the master oscillator by way of recalibration so as to maintain the desired frequency of oscillation as accurately as the calibration and control system will permit.

9. A method as claimed in claim 8, wherein the RF source is a YIG oscillator and the recalibration step is performed every 200 milliseconds.

10. A method as claimed in claim 9, wherein the calibration steps and alteration of at least the frequency controlling signals supplied to the oscillator are under microprocessor control.

11. A method as claimed in claim 10, wherein the microprocessor includes or is associated with memory means into which the results of the calibration sweeps and other data are stored for reference purposes.

12. A method as claimed in claim 11, wherein the harmonically related marker signals are generated with reference to a crystal oscillator.

13. Apparatus for performing the method as claimed in any one of claims 2 to 12.

14. Apparatus as claimed in claim 1 or 13, wherein the RF source, detector and associated control unit are contained within a single unitary housing together with relevant power supplies and internal environmental controls to maintain constant at least the temperature within the housing and thereby improve reliability and consistency of operation.

15. Apparatus as claimed in claim 14 further comprising a signal analyser and display means within the same housing.

16. Apparatus as claimed in either of claims 14 and 15 further comprising circuit means for generating readable information to appear in the display to indicate when the instrument is proceeding through a calibration process, and when calibration has been completed.

17. Testing apparatus for use in the GHz range of RF frequencies, by which the response of devices under test can be ascertained to signals in that range, comprising:

(1) an RF source for generating RF signals up to tens of GHz with output means for delivering signals to a device under test;

(2) RF detector means adapted to receive signal(s) from a device under test and generate signal(s) indicative of the attentuation of the device to the supplied RF signal(s); and

(3) microprocessor based control means receptive of signals from and adapted to generate control signals for both the RF source and the detector for calibration and control of the source and to optimise the sensitivity of the detector to the RF signals and decrease its sensitivity to electrical noise signals.

SUBSTITUTE SHEET wherein all of items (1) to (3) are contained within a common housing to facilitate the transfer of information between the source the detector and the microprocessor based control unit.

18. Test apparatus as claimed in claim 17, further comprising display means for visually displaying the results of measurements made on the device under test also within or associated with the common housing.

19. Methods and apparatus as herein described with reference to and as illustrated in the accompanying drawings.