WO1992021092A1

WO1992021092A1 - Hardware modeler with simultaneous model execution, shared memory and multiple height cartridge capability

Info

Publication number: WO1992021092A1
Application number: PCT/US1992/003796
Authority: WO
Inventors: Roy C. Mcneil, Jr.; Edward Joseph Lhotak, Jr.; Simon Kin-Hu Chan
Original assignee: Racal-Redac, Inc.
Priority date: 1991-05-10
Filing date: 1992-05-08
Publication date: 1992-11-26

Abstract

An improved high speed hardware modeler for use in circuit simulation including fault simulation includes a plurality of pin memory controllers coupled to separate cartridge buses to effect simultaneous hardware model evaluation. By providing multiple data paths from pin memory to multiple cartridge buses, memory sharing between pin memory controllers can be effected. In addition, multiple pin memory controllers can be linked and synchronized to drive cartridges which span two or more pin memory controllers to accommodate hardware devices with more pins than can be handled by a single pin memory controller. The cartridges include a ROM containing configuration information for programming the cartridge to communicate with various types of DUS. The programming is done by the system upon plugging the cartridge into the hardware modeler.

Description

HARDWARE MODELER WITH SIMULTANEOUS MODEL

EXECUTION, SHARED MEMORY AND MULTIPLE

HEIGHT CARTRIDGE CAPABILITY

Cross Reference to Related Documents This application is related to a co-pending patent application entitled "Active Cartridge Display For Hardware Modeler," to Ed Lhotak et al., S/N 07/614,428 filed November 15, 1990 and commonly owned which is incorporated herein by reference.

The present invention is described in an article describing a product embodying the present invention entitled "Concurrent Hardware Modeling Speeds Simulation," by Ed Lhotak et al., in High Performance Systems, June 1990, CMP Publications, Inc. pp. 41-45. This article is hereby incorporated by reference.

Background

1. Field of the Invention

This invention relates generally to the field of circuit simulation devices including hardware modelers. More particularly, this invention relates to a hardware modeler method and apparatus capable of simultaneous execution of multiple models, shared memory and virtual memory capability, and multiple height cartridge execution using multiple pin memory controllers operating in synchronization.

2. Background of the Invention

Circuit simulators are in common use for modeling the performance of complex electronic circuits. Often, complex circuits such as microprocessors and custom LSI and ASIC circuits are modeled by one of the actual circuits appropriately interfaced to a simulator. Such devices are commercially available as, for example, the CATS® hardware modeler used in conjunction with the CADAT* simulation software (both products produced by Racal-Redac, Inc. the assignee of the present invention) . Hardware modeling has also been described in, for example, U.S. patent nos. 4,590,581 and 4,635,218 both to Widdoes, Jr. which are incorporated herein by reference.

Briefly, in hardware modeling, an actual device which is being modeled is used as a substitute for a software description of the device. The actual device is used for simulating performance of the device in a circuit. For simpler devices such as AND gates, OR gates, NOR gates, etc. it is more common to use a software description of the device function for the simulation. Test vectors (an array of input signals, generally but not necessarily digital in nature) are applied to the device from the simulation software. The response of the device to this stimulation is fed back to the simulation software for further processing.

Commercially available hardware modelers are arranged as banks or card cages of circuit boards or cartridges carrying the various hardware devices to be modeled. In addition, the units contain the timing and interfacing circuitry necessary to operate the particular device to be modeled. The terms "board", "card" and "cartridge" are used interchangeably _ throughout.

In many synchronous dynamic devices such as microprocessors, each time the hardware model is accessed, it must be initialized. Each previously applied stimulation vector must be sequentially applied to the device so that it can be restored to the correct internal state prior to application of the current stimulation vector.

When simulation of a complex system with hundreds or thousands of nodes is undertaken, the simulation process can often take hours or days even with modern high speed computers performing the simulation. This is particularly the case when performing fault simulation on such a circuit. In fault simulation of logic circuits, the circuit is simulated as a good circuit and then repeatedly as a circuit having a fault (short to logic high and logic low) at each node of the circuit. For a network of N nodes, this means a total of as many as 2N + 1 complete simulations. Fault simulation of complex circuits can routinely take days or weeks of computer time to complete.

For each simulation, there may be many instances of a particular hardware model (that is, the same type of device may appear in the circuit being simulated several times) as well as more than one hardware model required per simulation.

In fault simulation particularly, this can result in huge memory requirements since a portion of the available memory must be allocated for each instance of the device in an adequate quantity to hold a complete sequence of vectors applied to the device during the whole simulation. In some prior art hardware modelers, the result of running out of memory is that the simulation "crashes" resulting in wasted time and resources. As previously stated, this wasted time can be measured in days.

Since such simulations may take hours or days to complete, any enhancement to the speed of simulation can directly reduce the completion time of a development project. Conversely, any delays are added to the required development time. Prior art hardware modelers are strictly serial devices in which only one hardware device may be modeled at any given time.

In these prior art systems, a single pin memory controller is used to control the pin memory of the modeler. Since only one hardware model cartridge (be it single or multiple height) is used at a time, this arrangement was found to be acceptable. However, in the present invention, it is desired to produce a hardware modeler capable of execution of multiple hardware models simultaneously. In order to accomplish this, multiple controllers are required. This in turn causes a problem when it is desired to use multiple controllers to control a multiple height cartridge, since both controllers must then operate in synchronization.

The problems of enhanced throughput to the modeler by simultaneous execution and extensive memory requirements for fault simulation as well as the issue of handling multiple height model cartridges, as well as other problems are addressed in the present invention. Summary of the Invention

It is an object of the present invention to provide an improved hardware modeler.

It is a feature that the present invention provides a mechanism for a hardware modeler to share available memory resources to a greater extent than known hardware modelers.

It is an advantage that the present invention permits use of disk memory as virtual pin memory in the event actual pin memory is used up.

It is another advantage that separate memory is used for each cartridge bank, but some sharing of the available memory can be done to prevent crashing of a simulation or resorting to virtual memory techniques until necessary.

It is a further advantage that the present hardware modeler can perform simultaneous execution of modeling by multiple hardware cartridges enhancing throughput of the modeler and thus simulation speed.

These and other objects, advantages and features of the invention will become apparent to those skilled in the art upon consideration of the following description of the invention.

In one aspect of the present invention, an improved high speed hardware modeler for use in circuit simulation (including fault simulation) includes a plurality of pin memory controllers coupled to separate cartridge buses to effect simultaneous hardware model evaluation. By providing multiple data paths from pin memory to multiple cartridge busses, memory sharing between pin memory controllers can be effected. In addition, multiple pin memory controllers can be linked and synchronized to drive cartridges which span two or more pin memory controllers to accommodate hardware devices with more pins than can be handled by a single pin memory controller. The cartridges include a ROM containing configuration information for programming the cartridge to communicate with various types of DUS. The programming is done by the system upon plugging the cartridge into the hardware modeler.

In another aspect of the present invention, a hardware modeling system includes a model circuit cartridge containing a model circuit for use in modeling operation of the model circuit. The model circuit includes a plurality of input pins divided into first and second sets of pins. A first pin memory stores a first sequence of vectors to be applied to the first set of pins of the model circuit. A second pin memory stores a second sequence of vectors to be applied to the second set of pins of the model circuit. A first pin memory controller applies the first sequence of vectors to the first set of pins of the model circuit. A second pin memory controller applies the second sequence of vectors to the second set of pins of the model circuit. A synchronization circuit synchronizes operation of the first and second controllers so that the first and second controllers apply the first and second sequence of vectors to the first and second set of pins in synchronization.

The synchronization circuit preferably allows for establishing either one of the first and second controllers as a master and the other as a slave. One of the first and second controllers is situated physically closer to a source of clock signals than the other controller, and this is the controller which is selected to be the master since clock signals arrive at this controller first. Synchronization is obtained by transmitting synchronization signals from the master to the slave with an equal number of time delays being encountered in both the master and the slave prior to the synchronization signals reaching a clock pre-scaler.

According to another aspect of the present invention, a hardware modeling system for circuit simulation includes a first model circuit cartridge containing a first model circuit for use in modeling operation of the first model circuit. A second model circuit cartridge contains a second model circuit for use in modeling operation of the second model circuit. A first pin memory stores a first sequence of vectors to be applied to the first model circuit. A second pin memory stores a second sequence of vectors to be applied to the second model circuit. A first controller applies the first sequence of vectors to the first model circuit. The second controller independently applies the second sequence of vectors to the second model circuit while the first controller is simultaneously applying the first sequence of vectors to the first model circuit.

A method, according to the invention, for programming a model cartridge of a hardware modeler, the model cartridge including a device to be simulated, includes the steps of: reading the contents of a memory situated on the cartridge; assigning either a driver or a sensor or both or neither to each pin on the device to be simulated based upon a pin configuration map stored in the memory; and establishing reference signal levels to represent the possible states of pins on the device to be simulated.

In another aspect of the present invention, a model cartridge for a hardware modeler includes a device to be simulated, the device having a plurality of pins including an input pin and an output pin. A memory stores pin configuration information for the device. A driver drives the input pin with input signals and a sensor senses output signals from the output pin. Switching circuitry is used for assigning the driver to the input pin and the sensor to the output pin in accordance with the pin configuration information stored in the memory.

In a further aspect of the present invention, a hardware modeling system for use in circuit simulation includes a first model cartridge connector and a second model cartridge connector. A first pin memory stores a first sequence of vectors to be applied to a cartridge installed in the first model cartridge connector. A second pin memory stores a second sequence of vectors to be applied to a cartridge installed in the second cartridge connector. A first controller applies the first sequence of vectors to the first model cartridge connector and a second controller applies the second sequence of vectors to the second model cartridge connector. The modeler can be configured to provide a plurality of operational modes such as: (1) a first operational mode wherein first and second model cartridges are installed in the first and second model cartridge connectors, and the first and second sequence of vectors are applied to the first and second cartridges simultaneously and independently; (2) a second operational mode wherein a double height model cartridge is installed in the first and second model cartridge connectors, and the first and second sequence of vectors comprise a double wide sequence of vectors applied by the first and second controller in synchronization to the double height cartridge; and (3) a first model cartridge is installed in the first model cartridge connector, and the first and second controllers retrieve the first and second sequence of vectors from the first and second pin memory, and apply the first and second sequence of vectors to the first model cartridge so that the first and second pin memory is shared for a single cartridge.

In a subset of the second mode of operation described above, the system includes a third model cartridge connector, third pin memory for storing a third sequence of vectors to be applied to a cartridge installed in the third model cartridge connector, and a third controller for applying the third sequence of vectors to the third model cartridge connector. In this mode, a triple height model cartridge is installed in the first, second and third model cartridge connectors, and the first, second and third sequence of vectors comprise a triple wide sequence of vectors applied by the first, second and third control means in synchronization with the triple height cartridge. Of course, this arrangement could be extended to four or more connectors without departing from the present invention.

In another aspect of the present invention, a circuit ulation system using multiple hardware modelers includes a Local Area Network (LAN) and a first hardware modeler residing on the LAN. A second hardware modeler also resides on the LAN. A first packet containing a request to execute a hardware instance is transmitted to the first hardware modeler a second packet containing a request to execute a hardware instance is transmitted to the second hardware modeler immediately after transmitting the first packet and prior to receiving a response to the first packet. Preferably, the first packet includes a plurality of requests for executing a plurality of hardware instances and the second packet includes a. plurality of requests for executing a plurality of hardware instances.

The features of the invention believed to be novel are set forth with particularity in the appended claims. The invention itself however, both as to organization and method of operation, together with further objects, features and advantages thereof, may be best understood by reference to the following description taken in conjunction with the accompanying drawing.

Brief Description of the Drawing

FIGURE 1 is a block diagram of the hardware modeling system of the present invention.

FIGURE 2 illustrates the physical layout of the modeler system of the present embodiment of the invention.

FIGURE 3 is a block diagram of the cartridges used in the present invention.

FIGURE 4 is a flow chart of the process of programming the driver/sensor ASICs of a cartridge according to the cartridge ROM.

FIGURE 5 is a block diagram of the Pin Memory Controller (PMC) of the present invention.

FIGURE 6 is a block diagram of the Controller Clock Generator (CCG) circuit of the Pin Memory Controller of the present invention.

FIGURE 7 shows the interconnection of three PMC cards for master / slave operation.

FIGURE 8 shows a more detailed diagram of the timing circuits used to synchronize the PMC cards. FIGURE 9 is a flow chart describing the overall operation of the timing process of FIGURE 8.

FIGURE 10 is a schematic of a master PMC board configuration according to the present invention.

FIGURE 11 is a schematic of a slave PMC board configuration according to the present invention.

FIGURE 12 is a schematic of a driver/sensor circuit from driver/sensor ASIC 202.

FIGURE 13 shows a time line diagram for multiple modelers operating on a Local Area Network.

FIGURE 14 shows a time line diagram for multiple modelers operating on a Local Area Network.

Detailed description of the invention

Turning now to FIGURE 1, the basic architecture of the improved hardware modeling system of the present invention is shown. A central processor 12 along with its associated memory 13 is coupled to a bus such as the industry standard VME bus 14 (or other bus structure). In the preferred embodiment, the processor is a SUN Microsystems, Inc. SPARC™ processor board having a built in Ethernet/FDDI interface to permit access to a local area network 19. A keyboard 16 and a monitor 18 as well as possibly a mouse or other input device (not shown) provide the user interface hardware to the processor and simulation software.

A plurality of hardware cartridges such as 20, 22 and 24 containing the hardware devices being modeled are attached to one or more cartridge busses 30, 32, 34, 36, 38 and 40. These busses, in the preferred embodiment, are 160 lines wide with 128 lines devoted to servicing the Device Under Simulation's (DUS) input / output pins to provide access to pin memory, while the remaining pins are dedicated to timing, control, 5. clock, etc.

The modeler hardware operates as a VME bus slave to the SUN host. This arrangement provides a full 32 bit data bus and a 32 bit address bus as well as access to many industry standard peripherals. The present SUN host provides 16 MIPS of processing power to process simulation, modeling and control code. This allows all simulation activity, e.g., modeling, fault simulation, timing analysis, to run on one local workstation that also can be accessed remotely. For multiple users, networking can be provided through the LAN interface of processor 12.

FIGURE 1 shows three different types of cartridges that can be handled in the present embodiment: single height, double height and triple height. The term "height" is used loosely herein, since a horizontal arrangement, etc., is entirely equivalent. This capability is provided to overcome pin-out limitations so that devices having more than 128 input/output pins can be modeled. Each single height cartridge, as mentioned above, can provide for 128 pin-outs on a DUS. By permitting a cartridge to span more than one cartridge bank, it can use the pin memory and Pin Memory Controller (PMC) from a vertically adjacent bank, as well as utilize the available pin-outs of the PMC card connected to the vertically adjacent cartridge bank.

The cartridges are arranged in banks of up to 5 (in this embodiment) cartridges per bank with a total of 6 banks in the present embodiment, but this is not to be limiting. Other embodiments may, for example, have only two or four banks. while others may have more than six. Similarly, the number of cartridges per bank and other similar parameters may be varied as the situation dictates. For each bank, a block of pin memory and a Pin Memory Controller (PMC) is provided. Thus, six such memory blocks and PMC circuits are provided. To simplify the illustration, three such PMC and memory blocks are shown in FIGURE 1 and designated 60, 62 and 64 respectively for the PMC circuits and 70, 72 and 74 for their associated memory blocks respectively.

The pin memory (70, 72, 74, etc.) is used to store a sequence of vectors to be applied to the input pins of the device under simulation (DUS) sequentially to first recreate the proper state of the device and then to apply a new vector to determine response to that new vector in a known manner. This new vector is then stored as the latest in the sequence of vectors to be applied as part of the initialization for successive new vectors. The PMCs 60, 62, 64 etc. provide memory management, synchronization among PMC cards, interface to the VME bus, clock functions for the cartridges and bus drivers/receivers for the cartridges.

Each cartridge 20, 22 and 24 includes a read only memory (ROM) such as an electrically alterable ROM or EAROM (not shown) . Each respective ROM contains identifying information regarding a respective device under simulation (DUS) respectively. While three cartridges are shown in the figure, those skilled in the art will appreciate that any suitable number, e.g., 30, such cartridges can be accommodated in such a hardware modeler.

Also connected to the VME bus 14 is a display interface circuit 48 which includes a display driver circuit that may be based upon, for example, the Yamaha V6366 general purpose display driver. The display interface 48 is coupled to a display/switch panel 50 by a separate bus 52. The display/switch panel includes, for example, a 320 X 200 or 640 X 200 LCD or other display with indicator lights and a pause switch.

In the preferred embodiment, six PMC boards, each with its own memory of, for example, 1 Mbit video DRAMs, are provided which can communicate via a separate PMC Sync Bus 80. The PMC represents an essentially complete, except for a hardware cartridge, hardware modeler on a single printed circuit board. Up to 2.5 M of high speed memory for each of 128 pins is provided on each PMC card of the preferred embodiment. This permits a user to shift in up to 2.5 X 2 20 vectors from one PMC card to any cartridge pin. Alternatively, two to one multiplexing can be used to achieve memory depth of 5 M for each of 64 pins. The memory is organized as hardwired page tables with 10K pages, each capable of handling 512 vectors. The PMC Sync bus 80 is used to communicate timing and synchronization control signals as will be explained in greater detail later.

A vector memory list processor enables the vectors to be applied to the hardware model at speeds of up to 33 Mhz in the present embodiment. It also manages noncontiguous vectors, allowing blocks of vectors to be identified with different users or instances. Vector memory list processing helps manage pin memory efficiently and allows reclaiming of available pin memory for maximum utilization. When a particular simulation is completed, the memory is freed and can be used by the next simulation. This feature is important for simulation runs in which faults are resolved and removed continuously from memory. The list processor allows faults to share pin memory before they are resolved. After a fault is detected, its memory is freed for other tasks. The preferred SUN SPARC™ CPU includes interface circuits for connecting a disk 82 and tape 84 system via a Small Computer System Interface (SCSI) bus 86. In general, this disk system is slower than desired, therefore, a separate disk controller 88 may be^" attached to the VME bus to control an external disk subsystem 90 to provide expandable and possibly faster storage.

In operation, the processor 12, which may be a SUN SPARC™ or other suitable processor, is used to determine which cartridges are present in the cartridge bank of the hardware modeler. The processor also reads the contents of the cartridge ROMs to determine what type of device is being carried in each cartridge. In addition, the processor is used to oversee the access to each cartridge in the cartridge bank.

The processor therefore knows at any given time which cartridges are active and which are inactive. The processor may also be used to run the simulation software to provide not only a hardware modeler function, but also to provide a full function stand alone simulator.

Information from cartridge ROMs associated with each cartridge is formatted and sent to the display interface 48 which generates appropriate Images for the display panel of display/switch panel 50. In the preferred embodiment, the processor informs the display Interface of which cartridges are active and the display interface displays the information relating to those active cartridges in reverse video. In other embodiments, the active cartridges can be indicated by other means such as different color or different intensity.

The display/switch panel also includes a "PAUSE" switch and various status lights which are controlled by the processor. The "PAUSE" switch is used by the operator to temporarily pause operation of the hardware modeler prior to

SUBSTITUTESHEET accessing the cartridge bank for service, reconfiguration, etc. The status lights are used to indicate whether or not the system is active, paused or in the process of being paused (wait) . The operation of these display features are better _ understood upon consideration of a co-pending patent application entitled "Active Cartridge Display For Hardware Modeler," S/N 07/614,428 filed November 15, 1990 and commonly owned which is incorporated herein by reference.

Turning now to FIGURE 2, an illustration of the housing configuration for the hardware modeler of the preferred embodiment of the present invention is shown and generally designated 150. For purposes of illustration, the housing door 151 is shown in the open position though, as will become clear later, the display indicates that four of the cartridges are active. The display/switch panel 50, in this embodiment, is situated on an upper panel of the housing 150. This display/switch panel 50 includes the LCD display 152 as well as pause switch 154, "IN USE" light 156 and "SUSPENDED" light 158.

In the preferred embodiment, the housing is logically and physically arranged in six compartments 161 through 166. Each compartment potentially carries a bank of up to five cartridges sharing a PMC board for a total of thirty cartridges. As illustrated, the right-most cartridge of banks 164 and 165 is not present. Double height cartridge 22 is illustrated spanning banks 162 and 163.

The display panel 152 is similarly arranged to show six regions with five display areas per region. The absence of cartridges in banks 164 and 165 is reflected in the display panel 152 by blank display areas in the corresponding region of the display. The display is arranged in a manner to correspond to the physical layout of the cartridge.banks for easy correlation between display and cartridge bank. In this illustration, that means a two wide by three down array of regions corresponding to the cartridge banks with each region having five display areas across. In this example, four of _ the cartridges are indicated as being active by the shading of the correlating display areas. Specifically, the second and fourth cartridge from the left in bank 161, the third cartridge in bank 164 and the fourth cartridge in bank 162 are shown as active by the shading of the display areas correlating to those cartridge representing reverse video display of the information.

In the preferred embodiment, single height, double height and triple height cartridges can be used. For example, cartridge 22 is shown as a double height cartridge. A single PMC card is allocated per cartridge bank; but, in four of six of the PMC cards, the cards can actually span two vertically adjacent banks of cartridges. The cartridge banks are arranged so that cartridge banks 162 and 163 can share the resources of their respective PMC cards and cartridge banks 165 and 166 can share the resources of their respective PMC cards. To accomplish this, the timing generator and vector memory list processors are linked and synchronized to each other before starting, as will be explained later.

The present modeler is automatically configured (or the configuration can be modified or overridden by the user) to operate in any one of three separate modes, depending upon the height of the cartridge and the information stored in the cartridge ROM. The operational mode can be overridden by the user via the user interface. The present modeler can also use cartridges designed for earlier versions of the CATS™ hardware modelers, (e.g. CATS 10,000 and CATS 12,000). With these cartridges, the system reads the address and location from the cartridge. By default, the system assumes the cartridge is a single height cartridge. If this is incorrect, the user manually reconfigures the module as a double or triple height.

The first mode of cartridge operation is that of independent operation of one single height cartridge in each of the cartridge banks (Six such banks are present in the preferred embodiment, but this is not to be limiting.). Therefore, simultaneous independent operation of up to six single height cartridges via independent start up of six PMC boards is possible in the preferred embodiment with each of the six PMC boards connected to a different cartridge bank.

The second mode of operation involves operation of double or triple height cartridges by linking PMC boards together and running them simultaneously in a master / slave configuration. In this mode, it is possible to drive one double or triple height cartridge per linked set of PMC boards. A double height cartridge always requires the resources of two PMC boards (one master and one slave to the master) and a triple height cartridge always requires the resources of three linked PMC boards (one master and two slaves to the master), in the present embodiment. As the system is maximally configured, two double height cartridges may be run simultaneously with two single height cartridges. Or, two triple height cartridges may be run simultaneously. Again, each PMC board is connected to a separate cartridge bank, for a total of six PMC cards in the example configuration.

The third mode of operation is the sharing of memory by splitting faults (or users in a multi-user environment) for the same cartridge across two PMC boards. This is accomplished under software control making use of the PMC board's ability to drive vectors out on either one of two connectors. In this case the boards are run independently, not simultaneously, and not linked via hardware master / slave mode operation. Instead, a logical connection is made in software to relate memory locations that hold vectors on each PMC board to the same instance of the model. Physically, in the present system, this is possible in the two pairs of PMC 5 boards that drive banks 162 and 163, and 165 and 166 of FIGURE

2.

Returning to FIGURE 1, PMC cards 60 and 62 are arranged as PMC cards which can share resources between two banks utilizing cartridge buses 38 and 40. PMC card 60 is connected

10 to bus 38 and bus 40 and can selectively be made to service either bus. Similarly, PMC card 62 is connected to both bus 38 and 40 and can similarly service either bus. PMC card 64 is shown as connected only to bus 32 and thus can only be allocated to a cartridge attached to bus 32 either alone or in

15 conjunction with another bus.

Turning briefly to FIGURE 3, the cartridge of the present invention is shown in block diagram form. These cartridges are compatible with the cartridges used in the commercially available CATS™ modeler manufactured and marketed by Racal-

20 Redac, Inc., the assignee of the present invention. The device under simulation, shown as 200 in FIGURE 3, may be any arbitrary hardware device or devices. Power and ground are provided to the DUS by discrete wiring. Inputs of the DUS are driven by input drivers with simulation vectors over the

25 cartridge bus. The outputs of the DUS are sensed by output sensors and captured on the cartridge to be thereafter read back over the cartridge bus by the CPU. To accomplish this, the cartridge can be wired to connect the input pins of the DUS and the output pins of the DUS to the output sensors. '30 Alternatively, an input driver and an output sensor pair can be assigned to each pin of the DUS and be programmed and controlled to accomplish the same function. In the present embodiment, this is accomplished using a plurality of CMOS Application Specific Integrated Circuits (ASICs) developed for this purpose and shown collectively as driver/sensor ASICs 202 which are discussed in greater detail in conjunction with FIGURE 12.

Briefly, the driver/sensor ASICs 202 are arrays of drivers, sensors and switches. The drivers are CMOS registers capable of driving either CMOS or TTL devices. The sensors are made up of a pair of CMOS comparators interconnected to set up a voltage window to determine whether an input signal is a logic 1, logic 0 or tri-state level. The voltage window is externally programmable so that any of several circuit technologies can be accommodated. The switching circuitry is used to configure each of eight such driver/sensor pairs per ASIC as either a driver, a sensor or both to account for a pin being either an input, an output or a bus. Power supply and ground pins are separately wired in the present embodiment.

Under the control of bus interface control circuit 204, the ASIC circuits are configured as input drivers or output sensors, or both to define a bus, or bi-directional pin, respectively. Effectively, this process connects a cartridge bus pin that is being driven with simulation vectors to a DUS input pin, and likewise, a DUS output pin is sensed and the data returned over the cartridge bus. The interface drivers 208 provide buffering of the cartridge bus signals to and from the driver/sensor ASICs. The ROM 210 containing identifying information regarding the DUS 200 may be considered a part of the bus interface control circuitry 204 as shown.

The ROM 210 is also used to store a pin configuration map. For each DUS pin, the pin configuration map stores whether a pin is an input, an output, a clock, a power supply, ground, tri-state, bus, etc. In addition, the ROM 210 indicates which of, e.g., four, drive clocks and/or sense clocks each pin is associated. ROM 210 also stores the height of each cartridge and the reference voltage levels used by the window comparators on the driver/sensor ASICs 202. A check¬ sum is provided for error detection.

Turning to FIGURE 4, the process by which a cartridge is initialized is shown. The process starts, in an active system, by a user initiated pause at step 211. This is done by the user pressing the front panel "PAUSE" button. A cartridge is then inserted at step 212 (or, the system is reconfigured by rearrangement of cartridges). Next a cartridge search/initialize sequence is entered at step 213. This is done either by the user again pressing the "PAUSE" button or by the elapse of a predetermined time period, e.g., 5 minutes, from the time of the previous pressing of the "PAUSE" button. Step 213 also can be viewed as an entry point into this routine at power-up of the system. The remaining steps are then carried out for each cartridge in the system.

At step 214, ROM 210 is read by the system and its check¬ sum is verified to assure no errors. If errors are found an error message is displayed on the display to indicate to the user that corrective action should be taken. In other embodiments, other corrective action may be implemented.

At step 215, one or more PMC cards (as required) are mapped to the cartridge since communication with the cartridge and programming of the driver/sensor ASICs is carried out through the PMC card(s). Next, at step 216, the driver/sensor ASICs' pin-outs are programmed according to the information in the ROM 210 pin configuration map (or table). This programming determines how each pin of the DUS will be treated in simulation (e.g., as input, output, bus, etc.). According to this map, either a driver or a sensor or both or neither will be assigned to each pin of the DUS.

SUBSTITUTESHEET At step 217, the driver/sensor ASIC's reference windows are programmed so that the window comparators can determine whether signals are logic 1 levels, logic 0 levels, tri-state levels, etc. At 218, a READY bit is set on the cartridge, _ indicating that the cartridge is programmed and ready for use. The connection between PMC and cartridge is then released at step 219. If the current cartridge is not the last to be programmed, control returns to step 214 where processing of the next cartridge is undertaken. If, on the other hand, the current cartridge is the last to be processed, the system reverts to its normal operational state.

Referring now to FIGURE 5, a block diagram of a PMC board according to the present invention is shown. The central feature of the PMC board is an array of pin memory 220. As is common in the hardware modeler technology, high speed video memory circuits are used for pin memory since speed is critical and random access is not required on every memory cycle.

The memory on the PMC board of the preferred embodiment is designed to hold 320 video D-RAM circuits. These RAMs can be either 256K X 4 parts or may be 2M X 4 parts. With the 256K X 4 parts, the PMC with its attached memory board (a piggyback arrangement) holds 320 X 1Mbit / (8 bits / byte) = 40 M bytes of vector or "pin" memory. This memory can be configured in at least two different ways according to the present invention:

1. As a 128 pin wide bus with 2.5 M bits or vectors behind each of 128 possible pins. This is the generalized mode of operation that permits driving 128 pins from one PMC board to either of two 160 pin connectors. 2. As a 64 pin wide bus with 5 M bits or vectors behind each pin. This permits higher speed operation since the 128 bits are fed into a 2:1 multiplexer and controlled to permit a slower access at the RAM side of 1/2 of the vector rate at the output side of the multiplexer. The

PMCs can additionally be configured so that each drives 64 bits into separate pins on the same connector to run a 128 pin cartridge at the higher vector rates.

The pin memory 220 is allocated under the control of memory management block 222. Memory management 222 allocates memory in pages of 512 bits per pin as required using known memory management techniques. Since each physical device modeled may have different timing and clock requirements, a custom ECL ASIC circuit referred to as the Controller Clock Generator (CCG) circuit 226 is provided and coupled to the PMC sync bus 80. The CCG 226 provides various clock outputs as well as coordinating synchronization in timing of the PMC cards. The CCG 226 is coupled to the memory management 222, memory 220 as well as the cartridges via a cartridge bus driver 230.

In the event the simulation requires so much memory that the pin memory available to any device is exhausted, the memory manager writes out a portion of the pin memory to disk and frees up that memory for further use in the simulation. Although disk storage is much slower than RAM memory (particularly the high speed video RAM used in the preferred embodiment), this technique prevents the simulation from crashing and will result in net time savings in most situations. By using caching techniques, slowdown from disk limitations can be reduced. Also, shared memory techniques may be used in the fault simulation environment to further prolong pin memory swapping to disk (or other persistent storage media). Pin memory sharing during fault simulation is possible because pin memory pages are allocated for many different fault instances. These fault instances can be spread across PMC cards which share the same cartridge bus, increasing the effective pin memory depth.

_ Cartridge bus driver 230 interfaces the pin memory, clocks and control signals from the VME bus, via a VME bus interface 234. The PMC sync bus 80 is not seen by the cartridge; it is a separate bus running strictly between PMC cards over the system back-plane. In the preferred embodiment, two identical cartridge bus drivers 230 are provided (only one shown) so that the PMC card can be coupled to two vertically adjacent cartridge banks as previously described. The selection between the two cartridge bus drivers is made under software control.

The VME Bus Interface Circuitry 234 controls VME Bus transactions between the CPU and the PMC card. These transactions take place across the system back-plane, which couples the CPU to all PMC boards. The VME Bus Interface 234 steers data to and from the CPU from and to the PMC Board Control Registers, pin memory 220, memory management page tables, etc.

The pin memory 220 is organized in four banks of 512K X 32 bits on the base PMC board at the VME Bus Interface 234. In terms of the cartridge bus interface, these four banks can be configured to produce one bank each of 512K X 128 bits or 1M X 64 bits under software control. With the additional piggy-back memory board, the four banks of pin memory grow to 2.5M X 32 bits at the VME Bus Interface 234 and either 2.5M X 128 or 5M x 64 bits at the cartridge interface.

The pin memory 220 includes error detection and correction circuitry that can detect any single or double bit errors and correct all single bit errors during a vector run using known error detection and correction techniques. This feature is important to preserve data integrity over the vast pin memory 220, especially for very long vector runs during fault simulation. Without such error detection and correction, a single error could cause a simulation to crash or, even worse, produce erroneous results for single bit errors.

The memory management circuitry 222 includes page tables and support circuitry to link together pages of pin memory allocated to various users. Since the hardware modeler is designed to operate in a multi-user environment, it is designed to create and store pin memory information across many pages on demand. As a result, a particular user's pin memory data may be spread across many non-contiguous pages.

Each page of memory contains 512 vectors. Internal to the Memory Management block 222 is a jump counter whose job is to signal a branch to the next page address after the current 512 vectors on a page are exhausted. A vector clock is sent from the CCG 226 to both the pin memory 220 and the memory management block 222 to synchronize page jumping with vector application.

The CCG 226 is the timing generation unit on the PMC board. In the preferred embodiment, it operates on a signal from a 100 MHZ master clock, but this is not to be limiting since other master clock frequencies could also be used. From this master clock signal, several lower frequency clocks are derived by dividers. Under CPU control, the CCG 226 is programmed via the VME Bus interface 234 to produce whatever clock frequencies are required by the next active cartridge. Some of these clocks are sent through the cartridge bus drivers 230 to distribute clocks to the various cartridges in the cartridge bank. Others remain on the PMC board to drive the control logic necessary to produce vectors at the cartridge.

In addition, the CCG 226 is linked to the PMC Sync Bus 80. The sync bus 80 is a high speed ECL bus distributed across the back-plane of the system. It is used to "lock" together the timing of adjacent PMC boards for double and triple height cartridge execution.

The cartridge bus drivers 230 drive vector data and vector clocks to the cartridge banks. There are two sets of Bus Drivers each of which drive separate cartridge banks. Only one bus driver bank may be active at a time. Bank selection is determined by cartridge location. A bank is programmed to be active behind the next active cartridge. Programming is accomplished through the VME Bus Interface 234. The cartridge bus drivers 230 also receive response data back from the cartridge. This data is registered and read back under CPU control through the VME Bus Interface 234.

The CCG ASIC 226 is shown in greater detail in FIGURE 6. A programming bus 250 carries programming information from the CPU to each block of the CCG circuit 226. A system clock 254, which in the preferred embodiment is operating at 100 Mhz, is coupled into a pre-scaler 258 in order to divide down this frequency into a plurality of lower speed reference frequencies. These reference frequencies are then used by a clock generator 262 to generate whatever clocking signals are required by the PMC card and the cartridges.

A synchronization circuit 264 is coupled to the system clock 254 as well as the PMC sync bus and is used to synchronize operation of the pre-scaler and run time control logic circuit 266 among the several PMC cards as will be described in greater detail later. A vector counter 272 is used to keep track of the vectors being applied to the cartridge in order to control application of the vectors used to initialize the DUS on the cartridge and apply the new vector as required by the simulation.

In the preferred embodiment, a master clock is provided at 100 Mhz. At this frequency, it becomes somewhat difficult to synchronize the PMC cards which are linked together. To permit operation of double height and triple height cartridges, the timing of the cards must be synchronized. It is not sufficient that the cards operate at the same frequency from the same clock source to guarantee that they will be synchronized. A simultaneous start-up should be effected to provide a common reference time. This allows for multiple phase vector clocks to be in synchronization.

In the preferred embodiment, this is accomplished by effecting a master/slave relationship among the PMC cards. Due to the high speed of the clock, the master is selected to be the PMC card situated physically closest to the clock source on the back-plane. This master PMC card sends a reset pulse down the sync bus (also located on the back-plane) in order to dictate that the next clock pulse will be considered a timing reference point. By selecting the master to be the PMC card closest to the clock source and at the end of the sync bus, the clock and reset pulse will propagate down the back-plane in the same direction and will encounter similar propagation delays.

In order that the PMC cards are operating in synchronization so that double or triple height cartridges may be used, a master/slave relationship is established among the

PMC cards. Consider, for example, FIGURE 7 showing three PMC cards 300, 302 and 304 which are to be synchronized. PMC card 300 is selected as master and is preferably situated on the back-plane adjacent the closest point where the master clock signal CLOCK 308 from 254 is coupled to the back-plane. This permits the clock to propagate down the back-plane in the same direction as the START and RESET signals which will be described.

The START signal is used to trigger the application of vectors to the cartridge after the RESET signal synchronizes the CCG pre-scaler clocks on adjacent PMC boards. Both the START and RESET signals are initially generated by the master PMC board and transmitted along a START line 314 and a RESET line 320 on the back-plane. In the preferred embodiment, the CLOCK 308 line, START line 314 and the RESET line 320 are actually differential signal lines generated using differential emitter coupled logic (ECL) . In addition, the same circuitry is used in the master PMC card as in the slave PMC card so that the START lines 314 and the RESET lines 320 are also bi-directional ECL. The START and RESET lines are driven by differential ECL drivers with cutoff mode capability. The cutoff mode drivers allow a party line configuration for differential ECL signals, which is normally not possible for differential ECL. Normally, if two sets of differential signals were bussed together and one set goes active, then the aggregate differential signal would be made up of two signals at the logic 1 level because of a wire-OR condition. A differential pair with both signals at logic 1 is an undefined condition for a differential receiver.

Differential ECL is used due to its high speed capability as well as its inherent noise immunity. Cutoff mode drivers are used to preserve the benefits of differential ECL in a party line configuration. A party line configuration is used because various master / slave configurations are possible among the PMC cards depending upon where double height or triple height cartridges are plugged into the system.

The operation of this synchronization process is best understood by consideration of FIGURE 8 taken in conjunction _^ with FIGURE 9. FIGURE 8 shows the active internal circuitry of the master PMC 300 and the slave PMC 302. This circuitry on both the master and the slave PMC cards is located in the CCG ASIC 226. Slave PMC 304 is identical to slave PMC 302 and is thus not shown. Referring first to the master PMC 300, the differential CLOCK signal 308 is converted to a single ended clock signal by differential input ECL gate 322, which clocks D flip-flops 324, 326, 328 and 330 as well as the master PMC card's pre-scaler 334. When the internal RESET signal 336 is coupled to the D input of flip-flop 324, it is clocked in by the clock at the next clock transition producing an output at the Q output of flip-flop 324. This output drives a differential output ECL gate 340 to launch the RESET signal 320 out on the differential bus lines along the back-plane. The Q output of 324 is similarly latched into D flip-flop 326 the output of which is applied to the pre-scaler 334 to initialize the pre-scaler so that an initialization time is established.

In a similar manner, the internally generated START signal 340 is applied to the D input of flip-flop 328 and is latched in on the next clock transition. The Q output of 328 is applied to a differential output ECL gate 344 which launches the START signal 314 down the differential bus lines on the back-plane. The output of flip-flop 328 is also applied to the D input of flip-flop 330, the output of which is applied to the master PMC card's run time controller 348 to establish a starting time for the run time controller 348. The START and RESET signals are generated under software control. They come from a CCG ASIC 226 internal register which is programmed via the programming bus 250 of FIGURE 6.

Both the Master run time controller and the Slave run time controller are identical circuits in the preferred embodiment. Upon receipt of a START derived control signal, each of these run time controllers synchronously step through a sequence of events whose end result is the production of "run time" clocks used to apply vector data from the PMC card to the active cartridge.

Referring now to the slave PMC card 302, the differential RESET 320, START 314 and CLOCK 308 signals are respectively converted to single ended signals by differential ECL gates 352, 354 and 356 internal to the CCG ASIC 226. The single ended RESET signal from the output of 352 is applied to the D input of flip-flop 360 and is clocked in by the next CLOCK signal to produce a Q output which is applied to the slave's pre-scaler 364. In a similar manner, the single ended START signal from the output of 356 is applied to the D input of flip-flop 368 where it is latched in at the next CLOCK pulse from the output of 354. The Q output of 368 is applied to the slave's run time controller 370 to indicate the starting time.

FIGURE 9 shows a flow chart of the above process. The operation of the synchronization process will be clear upon reference to the discussion to follow describing FIGURE 10 and FIGURE 11. The process begins at step 400 where the master CCG is programmed as master. The slave CCG is then programmed at 402. A reset pulse is then issued on the master CCG to lock the master and slave pre-scalers together. The master CCG then issues a START pulse at 406 and the master and slave(s) then produce synchronous clocks at 408. FIGURES 10 and 11 describe the circuitry and signal pathways used to implement the START and RESET functions on the PMC Board for master and slave operation. A PMC Board will be a master when either a single cartridge is used (128 driver pins or less required) or when a double or triple cartridge is used and the PMC Board is the closer of the two or three boards to the Master Clock Oscillator. A PMC Board will be a slave board only when a double or triple cartridge is used and the PMC Board is not the closer of the two or three boards to the Display/Oscillator Board. For a double cartridge, two PMC Boards are used: one master board and one slave board. For a triple cartridge, three PMC Boards are used: one master board and two slave boards.

To run a double or triple height cartridge, two or three PMC Boards must be configured so that their vector data and clocks are synchronized at the time vectors are applied to the cartridge. In order to accomplish this, a master/slave relationship must be set up between the participating PMC Boards. The master board provides the control signals to synchronize and start vector and clock data to the cartridge under evaluation. The slave board listens to and synchronizes itself to the master board signals.

FIGURE 8 above showed the functionality of a master/slave relationship set up between two PMC Boards after each board has been configured appropriately. FIGURES 10 and 11 show the complete circuitry on a PMC Board and how the different pathways are arranged to produce the logic arrangement of FIGURE 8. The active signal paths are highlighted with arrows in FIGURES 10 and 11.

FIGURE 10 shows how a master PMC Board is configured.

First, the signal SLAVE is set to a logic 0 on the PMC Board under CPU control. The SLAVE signal, appropriately set. switches the pathways to the master configuration. The logic elements which are affected by the state of the signal SLAVE are AND gate 500, Multiplexer (MUX) 502 and DRIVER 504 for the reset circuitry, and AND gate 506, MUX 508 and DRIVER 510 for the start circuitry. SLAVE = 0 enables the highlighted pathway of FIGURE 10. The pathways which are enabled insure that when the VRESET signal is activated, it passes through three flip-flops: 512, 514 and then 520 via AND 516 prior to reaching the Pre-scaler circuitry 522. VRESET also passes through flip-flop 521 prior to reaching DRIVER 504. Similarly, the pathway from the VSTARTN signal to the Run Time Control Logic 524 passes through three flip-flops: 526, 528 and then 530 via AND gate 532. VSTARTN also encounters flip- flop 533 prior to reaching DRIVER 510. In addition, DRIVERS 504 and 510 are set to drive the differential signal pairs EVRESETN, EVRESET; EPSTARTN, EPSTART onto the back-plane. These differential signal pairs correspond to the single ended RESET and START signals respectively.

FIGURE 11 shows the slave board configuration for a PMC Board. When the SLAVE signal is set to logic 1, the highlighted pathway of FIGURE 11 is enabled. Note that in this slave configuration, only one flip-flop is encountered for the reset pathway to the Pre-scaler and only one flip-flop

542 is encountered on the start pathway to the Run Time Control Logic 524. Note that in the master configuration, the

EVRESETN EVRESET; EPSTARTN, EPSTART signal pairs are outputs from the PMC board, whereas in the slave configuration, these signals are inputs. The EPSTART, EPSTARTN signal pair is converted to a single ended output by RECEIVER 525 prior to encountering AND 506.

The key to the synchronization process is that both the VRESET and VSTARTN signals (which are activated on the master board) pass through the same number of flip-flops on the master board as on the slave board before reaching the Pre- scaler and Run Time Control Logic, respectively. The number of flip-flops on the master board is apparent from FIGURE 10; the total is three for both the VRESET and VSTARTN paths. For the slave board, in FIGURE 11, only one flip-flop is traversed for each path.

FIGURES 10 and 11 should be viewed simultaneously to see the full path of travel from VRESET and VSTARTN on the master PMC board to the Pre-scaler 522 and Run-Time Control Logic 524 on the slave PMC board. On FIGURE 10, VRESET passes through flip-flops 512 and 546 to the differential DRIVER 504 and onto the back-plane as EVRESETN, EVRESET. On FIGURE 11, the differential RECEIVER 548 passes EVRESETN, EVRESET to AND 500 and through the rest of the path highlighted on FIGURE 11. Before these differential signals were received by the slave PMC board, they passed through two flip-flops on the master PMC board (512 and 521 of FIGURE 10) and one additional flip- flop on the slave PMC board (540 of FIGURE 11). This totals three flip-flops. A similar situation can be found if one traces the VSTARTN signal from the master PMC board to the Run Time Control circuitry 524 of the slave PMC board.

It should be noted that all of the flip-flops described above are clocked from the same clock. This clock was shown in FIGURE 8 as deriving from the 100 MHz Clock block (254) and distributed differentially along the back-plane. Each PMC Board would then receive the clock signal and further distribute it through the sequential circuitry used in the synchronization process. This clock has been omitted from FIGURES 9 and 10 to preserve the clarity of the functional blocks described.

In summary, the pathways from the VRESET and VSTARTN signals to the Pre-scaler or Run Time Control Logic are equivalent, in terms of timing, whether the PMC is a master or a slave.. Given this equivalence, once each PMC board is set up as a master or a slave, using the SLAVE signal, then each board may be controlled identically by the actions of the VRESET and VSTARTN on the master board.

To synchronize master and slave PMC boards, the VRESET signal is toggled high then low on the master board. This causes the Pre-scaler clocks on each board to be held inactive, after the three flip-fop delay, until VRESET goes low. At this time, all master and slave Pre-scaler clocks will start up in phase with each other. Because the Pre- scaler clocks serve as the base frequencies for all other timing on the PMC Boards, once these signals have been synchronized across boards, then each board will produce vectors at the same time provided each board is started at precisely the same instant.

To start a vector run, the VSTARTN line is toggled low then high on the master board. After VSTARTN passes through the three flip-flops on both the master and slave boards, it reaches the Run Time Control Logic on each board and vector data is synchronously clocked out of the master and slave boards.

Turning now to FIGURE 12, the a driver/sensor circuit, as used in the driver/sensor ASICs is shown in greater detail. Each driver/sensor ASIC contains 8 such circuits, in the present embodiment, with 16 such ASICs on each single height cartridge. The ASIC is programmed by providing several signals to the ASIC. In order to establish the appropriate logic levels for output pins from the DUS, two voltage reference levels are established external to the ASICs using digital to analog converters. These reference voltages are shown as VHIREF and VLOREF which establish upper and lower thresholds for a pair comparators 602 and 604 connected as window comparators 608. Input signals from a DUS pin are applied to the window comparators which compare the signal level to VHIREF and VLOREF to produce two signals which are fed to registers 610 and 612. The registers' outputs are read out through two tri-state drivers 628 and 620 under the control of a Read Control signal 622 so that three possible states of the DUS pin are encoded as a two bit code which is multiplexed out onto the Data output line.

For pins that are output pins, tri-state driver 626 is turned off under the control of tri-state control line 628 from Program Control 630. For pins that are input pins, driver 626 is turned on and data is passed from the data in line through drive register 636 and driver 626 to the DUS pin. Since the circuit is implemented in CMOS, the output of driver 626 can equally well drive TTL or CMOS circuitry.

The drive clocks from the clock bus are passed through a 4:1 multiplexer 640 where one is selected under control of MUX Control signal 644 to clock the drive register 636. The ASIC is programmed by Program Data line(s) 648 which determine the state of driver 626 and which of the four clocks is passes by MUX 640. The cartridge provides further programming of the ASICs by selecting the window comparator reference voltages with a D/A converter external to the ASIC.

When the modeler of the present invention is connected to a Local Area Network (LAN), multiple users are given access to the modeler. In addition, a single user may have access to multiple modelers on the same network which can simultaneously and independently provide model execution under control of a single simulation. The communication between simulation and modeler is optimized to permit multiple modelers to execute simultaneously and independently with minimal delays and maximal parallelism. Communication is carried out using the TCP-IP facilities of the UNIX operating system. The modeler's communications facility has access to the physical location of all cartridges for the simulation.

All packets sent from the simulation to the modeler are buffered and sent out (flushed) in bursts. By this mechanism, the packets are sent back-to-back without introduction of additional delays since there is no requirement to wait for an acknowledgement of one packet prior to sending another. The modelers can acknowledge receipt of these packets asynchronously in any order so that modeling can be carried out independently and simultaneously at two or more different modelers. At the simulator, responses are received from the modeler and buffered until such time as the simulator has completed evaluation of software events. Thus, multiple modelers may operate in parallel with each other and with the simulator to improve performance.

The flow of signals at the simulator can be described by the following pseudocode:

Begin

Signal modeler communication facility to start buffering; for each hardware instance, send packet to modeler communication facility; end for; Signal modeler communication facility to send response;

End.

The flow of signals at the hardware modeler communication facility can be described by the following pseudocode:

Begin for each hardware modeler, if there is something to send, then send it; end for; End.

This is more readily understood by considering a grossly simplified example of part of a simulation session with 10 instances running on a network and accessing three modelers as follows:

Instance #1 directed to Modeler #1 Instance #2 directed to Modeler #1

Instance #3 directed to Modeler #1

Instance #4 directed to Modeler #1

Instance #5 directed to Modeler #2

Instance #6 directed to Modeler #2 Instance #7 directed to Modeler #2

Instance #8 directed to Modeler #3

Instance #9 directed to Modeler #3

Instance #10 directed to Modeler #3

At time zero, three packets are constructed and sequentially sent over the LAN as follows:

packet #1 (instances # 1-4) sent to Modeler #1 packet #2 (instances # 5-7) sent to Modeler #2 Packet #3 (instances # 8-10) sent to Modeler #3

The timing of the communication is as follows:

Time 0 - packet #1 delivery over the network

Time 1 - packet #2 delivery over the network simultaneously. Modeler #1 processes request Time 2 - packet #3 delivery over the network simultaneously. Modeler #2 processes request (Modeler #1 may also still be processing) Time 3 - Modeler #3 processes request

(Modelers #1 and 2 may still be processing)

For this example, let us simplify by making the following assumptions. If the time for delivery of a packet (one way) = T, then the round trip time for a packet = 2T. Let the vector execution time for each instance = E then:

Total time to process 10 instances in 1 modeler = 2T + 10E.

In a purely serial system with a single modeler, the amount of time taken to process these 10 instances would be 10 * (2T + E) = 20T + 10E. The present invention substantially improves on this performance.

Since there is substantial overlap of delivery time for packets in the present example (often as much as 2T for each execution): Total time to process 10 instances in the present invention assuming each instance must be handled serially within each modeler is approximated by = (4E + 2T) + (3E + 2T) + (3E + 2T) - β, where β represents the time savings due to overlap in transit and/or processing times. For the case where T is the dominant variable in each parenthetical term, this simplifies to approximately 4T, since the middle parenthetical term is handled totally in parallel with other operations. For the case where E is a greatly dominant variable in each parenthetical term, this simplifies to approximately 4E, (actually 4E + 2T since all transit time and processing time occurs in parallel with the exception of the first and last packet transmission time).

In the event each modeler can handle the instances in parallel, the processing time improves to (E + 2T) + (E + 2T) + (E + 2T) - β. Where either T or E is dominant, this again becomes approximately 4T + E. This can be seen more clearly in FIGURE 13 where T is shown to dominate E and in FIGURE 14 where E is shown to dominate T. In each FIGURE, the shaded blocks represent packets transmitted first to the hardware modeler and next back from the hardware modeler to the simulator.

Many variations of the present invention will occur to those skilled in the art without departing from the present invention. For example, more or fewer cartridges may be provided in each bank and more or fewer PMC circuits may be used. Higher speed bus operation can be anticipated as the technology permits. ECL technology is used for some circuits in the present embodiment while CMOS is used for others, but other alternatives are also possible. Also, different processor hosts can be used, memory depth can be varied, the cartridge banks and PMC partitioning can be changed, and the system can use either an internal or externally connected host. Other variations will occur to those skilled in the art.

Thus it is apparent that in accordance with the present invention, an apparatus that fully satisfies the objectives, aims and advantages is set forth above. While the invention has been described in conjunction with specific embodiments, it is evident that many alternatives, modifications and variations will become apparent to those skilled in the art in light of the foregoing description. Accordingly, it is intended that the present invention embrace all such alternatives, modifications and variations as fall within the scope of the appended claims.

What is claimed is:

Claims

1. A hardware modeling system, comprising in combination: model circuit means including a model circuit for use in modeling operation of a model circuit, said model J5 circuit including a plurality of input pins divided into first and second sets of pins; first pin memory means for storing a first sequence of vectors to be applied to said first set of pins of said model circuit; 0 second pin memory means for storing a second sequence of vectors to be applied to said second set of pins of said model circuit; first control means for applying said first sequence of vectors to said first set of pins of said model 5 circuit; second control means for applying said second sequence of vectors to said second set of pins of said model circuit; and synchronization means for synchronizing operation of 0 said first and second control means so that said first and second control means apply said first and second sequence of vectors to said first and second set of pins in synchronization.

2. The apparatus of claim 1 further comprising circuit simulation means for calling said first and second control means and transmitting a new vector respectively thereto for application to said first and second sets of pins of said model circuit means, and for receiving an output from said first and second control means indicative of the respective states of said model circuit means resulting from application of said new vector.

3. The apparatus of claim 1. wherein said synchronization means includes means for establishing either one of said first and second control means as a master and the other as a slave.

4. The apparatus of claim 3, wherein one of said first and _ second control means is situated physically closer to a source of clock signals than the other said control means, and wherein said one control means is selected to be said master.

5. The apparatus of claim 1, wherein said first and second control means include: clocking means, for deriving derived clock signals; and, wherein said synchronization means includes: means for establishing said first control means as a master; means for establishing said second control means as a slave to said master; means for transmitting synchronization signals from said master to said slave; and equal delay means for delaying said synchronization signals an equal number of time delays in both said master and said slave prior to said synchronization signals reaching said clocking means.

6. A hardware modeling system, comprising in combination: model circuit means containing a model circuit for use in modeling operation of the model circuit, said model circuit including a plurality of input pins divided _ into first and second sets of pins; a source of clock signals; first pin memory means for storing a first sequence of vectors to be applied to said first set of pins of said model circuit; second pin memory means for storing a second sequence of vectors to be applied to said second set of pins of said model circuit; first control means for applying said first sequence of vectors to said first set of pins of said model circuit; second control means for applying said second sequence of vectors to said second set of pins of said model circuit; said first control means being situated physically closer to said source of clock signals than said second control means; said first and second control means including clocking means, for deriving derived clock signals from said source of clock signals; synchronization means for synchronizing operation of said first and second control means so that said first and second control means apply said first and second sequence of vectors to said first and second set of pins in synchronization; circuit simulation means for calling said first and second control means and transmitting a new vector respectively thereto for application to said first and second sets of pins of said model circuit means, and for receiving an output from said first and second control means indicative of the respective states of said model circuit means resulting from application of said new vector, said synchronization means including: means for establishing said first control means as a master; means for establishing said second control means as a slave to said master; means for transmitting synchronization signals from said master to said slave; and equal delay means for delaying said synchronization signals an equal number of time delays in both said master and said slave prior to said synchronization signals reaching said clocking means.

7. A hardware modeling system for performing a simulation of a circuit, comprising in combination: a first model circuit means containing a first model circuit for use in modeling operation of the first model _ circuit; a second model circuit means containing a second model circuit for use in modeling operation of the second model circuit; first pin memory means for storing a first sequence of vectors to be applied to said first model circuit means; second pin memory means for storing a second sequence of vectors to be applied to said second model circuit means; first control means for applying said first sequence of vectors to said first model circuit means; and second control means for applying said second sequence of vectors to said second model circuit means while said first control means is simultaneously and independently applying said first sequence of vectors to said first model circuit means.

8. The apparatus of claim 7, further comprising circuit simulation means for calling said first and second control means and transmitting a first and second new vector respectively thereto for application to said first and second model circuit means, and for receiving an output from said first and second control means indicative of the respective states of said first and second model circuit means resulting from application of said first and second new vector.

9. The apparatus of claim 7, further comprising memory managing means for appending a portion of said second pin memory means to said first pin memory means to provide more pin memory to said first model circuit means.

10. The apparatus of claim 7, further comprising virtual memory means for storing the contents of said pin memory to a persistent storage media when said pin memory approaches its capacity.

11. The apparatus of claim 10, wherein said persistent storage media comprises a hard disk drive.

12. The apparatus of claim 9, further comprising virtual memory means for storing the contents of said pin memory to a persistent storage media when said pin memory approaches its capacity.

13. The apparatus of claim 12, wherein said persistent storage media comprises a hard disk drive.

14. The apparatus of claim 7, further comprising means for coupling said hardware modeling system to a local area network.

15. The apparatus of claim 14, wherein said first and second model circuit means, said first and second pin memory means and said first and second control means are coupled to a single node of a local area network to provide multiple user access to said hardware modeling system.

12. A hardware modeling system for use in circuit simulation, comprising in combination: a first model circuit means containing a first model circuit for use in modeling operation of the first model _ circuit; a second model circuit means containing a second model circuit for use in modeling operation of the second model circuit; first pin memory means for storing a first sequence of vectors to be applied to said first model circuit means; second pin memory means for storing a second sequence of vectors to be applied to said second model circuit means; first control means for applying said first sequence of vectors to said first model circuit means; and second control means for applying said second sequence of vectors to said second model circuit means while said first control means is applying said first sequence of vectors to said first model circuit means; circuit simulation means for calling said first and second control means and transmitting a first and second new vector respectively thereto for application to said first and second model circuit means, and for receiving an output from said first and second control means indicative of the respective states of said first and second model circuit means resulting from application of said first and second new vector; memory managing means for appending a portion of said second pin memory means to said first pin memory means to provide more pin memory to said first model circuit means; virtual memory means for storing the contents of said pin memory to a disk drive when said pin memory approaches its capacity.

17. A hardware modeling system for use in circuit simulation; comprising in combination: first model cartridge receiving means; a second model cartridge receiving means; jϊ first pin memory means for storing a first sequence of vectors to be applied to a cartridge installed in said first model cartridge receiving means; second pin memory means for storing a second sequence of vectors to be applied to a cartridge 0 installed in said second cartridge receiving means; first control means for applying said first sequence of vectors to said first model cartridge receiving means; second control means for applying said second sequence of vectors to said second model cartridge 5 receiving means; and means for configuring said modeling system for providing a plurality of operational modes including: a first operational mode wherein f„ *st and second model cartridges are installed in said first 0 and second model cartridge receiving means, and said first and second sequence of vectors are applied to said first and second cartridges simultaneously and independently; and a second operational mode wherein a double 5 height model cartridge is installed in said first and second model cartridge receiving means, and said first and second sequence of vectors comprise a double wide sequence of vectors applied by said first and second control means in synchronization 0 to said double height cartridge.

18. The apparatus of claim 17, wherein said configuring means provides a third operational in which a first model cartridge is installed in said first model cartridge receiving means, and said first and second control means are linked together so _ that said first and second sequence of vectors are sequentially applied to said first model cartridge.

19. The apparatus of claim 17, further comprising: third a model cartridge receiving means; third pin memory means for storing a third sequence of vectors to be applied to a cartridge installed in said third model cartridge receiving means; third control means for applying said third sequence of vectors to said third model cartridge receiving means; wherein said configuration means provides a third operational mode in which a triple height model cartridge is installed in said first, second and third model cartridge receiving means, and said first, second and third sequence of vectors comprise a triple wide sequence of vectors applied by said first, second and third control means in synchronization to said triple height cartridge.

20. A hardware modeling system for use in circuit simulation; comprising in combination: first model cartridge receiving means; a second model cartridge receiving means; first pin memory means for storing a first sequence of vectors to be applied to a cartridge installed in said first model cartridge receiving means; second pin memory means for storing a second sequence of vectors to be applied to a cartridge installed in said second cartridge receiving means; first control means for applying said first sequence of vectors to said first model cartridge receiving means; second control means for applying said second sequence of vectors to said second model cartridge receiving means; and means for configuring said modeling system for providing a plurality of operational modes including: a first operational mode wherein first and second model cartridges are installed in said first and second model cartridge receiving means, and said first and second sequence of vectors are applied to said first and second cartridges simultaneously and independently; and a second operational mode in which a first model cartridge is installed in said first model cartridge receiving means, and said first and second control means are linked together so that said first and second sequence of vectors are sequentially applied to said first model cartridge.

21. A hardware modeling system for use in circuit simulation, comprising in combination: a first circuit bank including a first plurality of model circuit cartridges; _ a second circuit bank including a second plurality of model circuit cartridges; first pin memory means for storing a first sequence of vectors to be applied to one of said first model circuit cartridges; second pin memory means for storing a second sequence of vectors to be applied to one of said second model circuit cartridges; first control means for applying said first sequence of vectors to said one of said first model circuit cartridges; and second control means for applying said second sequence of vectors to said one of said second model circuit cartridges while said first control means is applying said first sequence of vectors to said one of said first model circuit cartridges.

22. The apparatus of claim 21, further comprising circuit simulation means for calling said first and second control means and transmitting a first and second new vector respectively thereto for application to said ones of said first and second model circuit cartridges, and for receiving an output from said first and second control means indicative of the respective states of said ones of said first and second model circuit cartridges resulting from application of said first and second new vector.

23. The apparatus of claim 21, further comprising: a double height cartridge coupled across said first and second circuit banks with a first set of pins connected to said first circuit bank and a second set of _ pins connected to said second circuit bank; and synchronization means for synchronizing operation of said first and second control means so that said first and second control means apply said first and second sequence of vectors to said first and second set of pins in synchronization.

24. The apparatus of claim 23 further comprising circuit simulation means for calling said first and second control means and transmitting a new vector respectively thereto for application to said first and second sets of pins, and for receiving an output from said first and second control means indicative of the response of said double height cartridge resulting from application of said new vector.

25. The apparatus of claim 23. wherein said synchronization means includes means for establishing either one of said first and second control means as a master and the other as a slave.

26. The apparatus of claim 25, wherein one of said first and second control means is situated physically closer to a source of clock signals than the other said control means, and wherein said one control means is selected to be said master.

27. The apparatus of claim 23, wherein said first and second control means include: clocking means, for deriving derived clock signals; and, wherein said synchronization means includes: _ means for establishing said first control means as a master; means for establishing said second control means as a slave to said master; means for transmitting synchronization signals from said master to said slave; and equal delay means for delaying said synchronization signals an equal number of time delays in both said master and said slave prior to said synchronization signals reaching said clocking means.

28. A method for programming a model cartridge of a hardware modeler, said model cartridge including a device to be simulated, comprising the steps of: reading the contents of a memory situated on said _ cartridge; assigning either a driver or a sensor or both or neither to each pin on said device to be simulated based upon a pin configuration map stored in said memory; and establishing reference signal levels to represent the possible states of pins on said device to be simulated.

29. The method of claim 28, wherein said establishing step comprises the step of setting reference voltage levels for a window comparator.

30. A model cartridge for a hardware modeler, comprising in combination: a device to be simulated, said device having a plurality of pins including an input pin and an output j> pin; memory means for storing pin configuration information for said device; driving means for driving said input pin with input signals; 0 sensing means for sensing output signals from said output pin; and switching means for assigning said driving means to said input pin and said sensing means to said output pin in accordance with the pin configuration information stored in said memory means.

31. The apparatus of claim 30, wherein said sensing means comprises a window comparator, and further comprising means for establishing reference voltages for said window comparator in accordance with reference values stored in said memory means.

32. The apparatus of claim 30, further comprising means for receiving external programming signals, generated in accordance with values stored in said memory means, and for controlling said switching means.

33. A circuit simulation system using multiple hardware modelers, comprising in combination: a Local Area Network (LAN); a first hardware modeler residing on said LAN; f> a second hardware modeler residing on said LAN; transmitting means for transmitting a first packet containing a request to execute a hardware instance to said first hardware modeler and for transmitting a second packet containing a request to execute a hardware 0 instance to said second hardware modeler immediately after transmitting said first packet and prior to receiving a response to said first packet.

34. The apparatus of claim 33, wherein said first packet includes a plurality of requests for executing a plurality of 5 hardware instances.

35. The apparatus of claim 33, wherein said second packet includes a plurality of requests for executing a plurality of hardware instances.