WO1992017836A1 - Electronic floppy disk emulation system - Google Patents

Abstract

An electronic memory apparatus for emulating a magnetic disk for being interconnected with a magnetic disk drive system having a magnetic head is described. The memory means (52) stores signals representative of digital information (10) including sector header information having a format substantially identical to that of the sector header information (10) on a magnetic disk and the system includes a magnetic transducer (74) connected in circuit with the electronic memory (52) for forming a magnetically coupled circuit with a magnetic head (76) to provide for information transfer between the electronic memory (52) and the magnetic disk drive system (42).

Description

ELECTRONIC FLOPPY DISK EMULATION SYSTEM

FIELD OF INVENTION

This invention relates to an electronic floppy disk emulation system for interfacing with a floppy disk drive, and more particularly to such a system which functions both as a removable part of system memory in a portable computer and emulates a floppy disk to communicate with other computers through their floppy disk ports.

BACKGROUND OF INVENTION

The market direction for personal computers is towards smaller, lighter, portable systems that operate on battery power. Most manufacturers are designing notebook size computers that are small enough to fit into a brief case and large enough for desktop displays and keyboards. A limiting factor in reducing size, weight and power is the rotating magnetic memory. A floppy disk drive (FDD) is necessary so that the portable computer can easily communicate with other computers by simply swapping floppy disks. But FDDs are relatively large, heavy and consume significant power. Elimination of the FDD from portable computers would alleviate the problem but then communication would have to occur through a direct transfer through the serial or parallel port, which is inconvenient, time consuming, and generally unattractive to users. SUMMARY OF INVENTION

This invention features an electronic floppy disk emulation system for interfacing to a floppy disk drive system. There is an electronic memory for storing data and a magnetic transducer which when juxtaposed to the floppy disk drive magnetic head forms a magnetically coupled circuit with the magnetic head. Electronic means generates a serial data stream which when connected to the magnetic transducer simulates a data stream generated by a rotating floppy disk.

In a preferred embodiment the serial data stream may include a sector header. The sector header may include an identification field required by the floppy disk drive system to complete a sector search. The sector header identification field may include an identification address mark, cylinder number, side number, sector number, sector size, identification field CRC bytes, read/write transition gap, and synchronization fields. The sector header and side numbers correspond to the location of the magnetic transducer. Data from the electronic memory may be included in the serial data stream following the sector header. The serial data stream may be equivalent in size to a sector of data of a formatted floppy disk. The data address mark may be included in the serial data stream immediately before the data from the electronic memory. The CRC bytes for data checking may be included in the serial data stream immediately after the data from electronic memory. The electronic means may include means for computing the CRC bytes on the same basis that the floppy disk drive system computes CRC bytes. The electronic means may include means for converting data signals transmitted from the floppy disk drive system through the magnetic transducer to a data stream representing the data signals. The data signals from the floppy disk drive system may be normal data signals written to a floppy disk during a sector write. A data address mark may precede the data signals. The serial data stream may include data spaces and each sector header may have a different identification field preceding the sector data spaces in the serial data stream. The electronic memory may be organized in groups of bytes equivalent in size to a sector of floppy disk formatted data space. The memory groupings may have addresses and may be read from or written to. The electronic means may also include means to store data from the data stream in the memory grouping. The electronic means may include a read-only memory for generation of the sector headers and may include a counter and decoder for addressing the read-only memory in sequence a word at a time. The electronic means may also include a shift register that can be parallel-loaded with data words for conversion to a serial data stream, and may also include an encoder for coding the serial data stream in FM or MFM. The electronic means may also include a write amplifier for interfacing the magnetic transducer to the coded serial data stream, and may include a shift register and means for computing the polynomial x¹⁶+x¹²+χ5+i for providing a 16-bit check sum. The electronic means may also include a read amplifier for converting the FM or MFM coded signals from the magnetic transducer to a serial data stream, and a clock oscillator that can be synchronized with the serial data stream. The electronic means may also include a means for address mark recognition and a shift register for converting a serial data word to a parallel data word, as well as means for storing a word from the shift register in the electronic memory and means for programming the lengths of the data words.

DISCLOSURE OF PREFERRED EMBODIMENT

Other objects, features and advantages will occur to those skilled in the art from the following description of a preferred embodiment and the accompanying drawings, in which:

Fig. 1 is a schematic diagram of a sector header employed by this invention;

Fig. 2 is a block diagram of a computer having a floppy disk drive for receiving an electronic floppy disk emulation system according to this invention;

Fig. 3 is a block diagram of a portable computer which utilizes the electronic floppy disk emulation system of this invention as a portion of its RAM;

Fig. 4 is an isometric diagram showing the electronic floppy disk emulation system according to this invention as a daughter board plugged into a mother board of the portable computer of Fig. 3; Fig. 5 is a more detailed block diagram of the floppy disk drive magnetic head and the magnetic transducer of the electronic floppy disk emulation system, magnetically coupled. Fig. 6 is a flow diagram of the software for implementing the electronic floppy disk emulation system according to this invention;

Fig. 7 is a schematic block diagram of the system between the data bus and address bus according to this invention;

Fig. 8 is a schematic diagram similar to Fig. 7 showing operation in the host computer;

Fig. 9 is a view similar to Figs. 7 and 8 for operation in the floppy disk drive unit;

Fig. 10 is a schematic block diagram of the controller for the system according to this invention;

Fig. 11 is an enlarged detailed drawing of the read-write logic of Fig. 10; Fig. 12 illustrates a timing diagram showing the waveforms occurring in the read amplifier;

Fig. 13 is an illustration of a timing diagram of the waveforms for the MFM encoder;

Fig. 14 is an enlarged detailed view of the cycle control of Fig. 10;

Fig. 15 is an enlarged detailed view of the ROM control circuit of Fig. 10;

Fig. 16 is an enlarged detailed view of the address control circuit of Fig. 10; Fig. 17 is a timing diagram showing the waveforms for the address storage;

Fig. 18 is an enlarged detailed schematic of the data I/O control of Fig. 10;

Fig. 19 is a timing diagram illustrating waveforms of th" read/write circuit;

Fig. 2ϋ is an enlarged detailed view of the CRC generator of Fig. 10;

Fig. 21 is a flow chart of the read cycle according to this invention; and Fig. 22 is a flow chart of the write cycle according to this invention.

Since the invention is intricately involved in the operation of the FDD, a brief explanation of that environment is offered. A read/write head of an FDD includes a magnetic circuit consisting of a coil, and a ferrous core with a small gap that is used for switching the magnetic state of a ferrous film along the gap. Th3 ferrous film is the surface of a floppy disk. In the write mode current pulses representing ones and zeroes of the data code are converted to magnetic flux by the read/write coil. The flux is directed to the gap by the core where the low reluctance floppy disk surface is intimately juxtaposed. The flux is diverted to the floppy disk and molecules on the surface of the film align themselves with the direction of the flux lines. When the flux field is removed the molecules remain in their aligned state. The disk is rotating and each binary 1 and 0 occupies a bit cell on the surface. In the read mode the changes in the magnetic field of the bit cells as the disk passes under the head induces a voltage in the read coil. The signal induced is typically a few millivolts in amplitude, which is enough to distinguish the signal from extraneous noise. Since the floppy disk emulation involves the disk operating system (DOS) , an understanding of how DOS organizes the disk and how the FDD operates is useful. To understand how DOS moves information to and from the disk drive, it is necessary to look at how DOS formats a diskette, how files are organized on the diskette, and how the floppy disk controller (FDC) finds a file. The disk drives and operating systems of a computer establish the capacity of the disks used, but the disk's structure is essentially the same, regardless of the setup. Data is always recorded on the disk surface in a series of concentric circles called tracks. Each track is further divided into segments called sectors. The amount of data that can be stored on each side of the disk depends on the number of tracks (its density), the number of sectors, and the size of the sectors.

The locations of each track and the number of usable sides are set by the hardware characteristics of the disk and the disk drive, and as such, they are fixed and unchangeable. However, the size, location and number of the sectors within a track are under software control. This is why disks are known as soft sectored. The characteristics of the disk sectors (their size and the number per track) are set when each track is formatted. DOS formats a disk into tracks and sectors, which are simply groupings of bytes on the physical medium. The disk sides, tracks and sectors are identified numerically and certain sectors are always reserved for special programs and indexes that use DOS to manage disk operations. The two sides of a double sided disk are numbered 0 and 1, corresponding to the two heads in the disk drive.

DOS organizes all the sectors on a disk into four sections, for different uses. The sections, in the order that they are stored, are the boot record, the file allocation table (FAT), the directory and the data space. The boot record is always located at sector 1 of track 0, side 0. A short program to start up the operating system is put in this record if necessary. All diskettes are formatted with a boot record, but the contents can vary depending on the formatting procedure. The file allocation table (FAT) follows the Boot Record, usually starting at sector 2, track 0, side 0. The FAT contains the official record of the disk format and maps out the location of the sectors used by the disk files. It can vary from two to four sectors in size. The File Directory is the next item on the disk. It is used as a table of contents identifying each file with a directory entry that contains several pieces of information including name and size. One part of the entry is a number that points to the first group of sectors used by the file (this number is also the first entry for this file in the FAT). The Data space, which occupies the bulk of the disk, is used to store data, while the other three sections are used to support data. The Directory and FAT always occupy track 0 and when the disk is accessed for the first time, the FDD head goes directly to track 0. The directory and file table information are read and stored in the computer main memory, making it unnecessary for the head to return to track 0 each time a file is accessed. When a file is addressed by a program or keyboard entry, the file name (usually limited to eight characters) is compared to the directory and file table and information is sent to the FDC directing the head to a track and sector where the file information is stored. Since tracks on a floppy disk are physically separated by <.010", the FDC must position the head with excellent mechanical accuracy. The FDC is responsible for converting high level disk commands (normally issued by software executing on the system processor) into disk drive commands. There are four functions: (1) Track selection: the controller issues a timed sequence of step pulses to move the head from its current location to the proper disk cylinder from which data is to be read or written. The controller also manages the head select signal to select the correct side of the floppy disk. (2) Sector selection: the controller monitors the data on a track until the requested sector is sensed. (3) Data separation: the actual signal recorded on a track is a combination of timing (clock) and data. The data stream read by the FDD must be converted into two signal streams, clock and data. (4) Error checking: information stored on a floppy disk is subject to both hard and soft errors. Hard (permanent) errors are caused by defects in the disk and soft errors are caused by mechanical interference or electromagnetic interference. A standard error check called Cyclic Redundancy Check (CRC) is used by the FDC.

As data is written on the disk, a 16-bit CRC code is computed by the FDC and stored on the disk. When the recorded data is read by the FDC, CRC is again computed by the FDC and the resultant 16-bit code is compared to the CRC recorded on the disk. If the two CRCs are different an error flag is generated, There are two standard techniques used to combine clcck and data storage on a floppy. The single density technique is referred to as FM recording and the double density technique is referred to as MFM (modified FM) recording. FM recording uses up to two clock pulses per bit cell. The first clock pulse always occurs at the start of a bit cell. If a binary 1 is recorded a second clock pulse is recorded in the center of the cell. If a binary 0 is recorded no clock pulse is recorded in the center of the cell.

In MFM encoding the data bits are again written in the center of the cell. However, a clock bit is written in the leading edge of the bit cell only if a zero bit was written in the previous cell and a zero data bit is to be written in the present bit cell.

Soft sectored floppy disks divide each track into a number of data sectors. Typically, sector sizes of 128, 256, 512 and 1024 data bytes are permitted. The sector size is specified when the track is initially formatted. Each of the sectors of a track is composed of four fields, as illustrated in sector header 10, Fig. 1. (1) Sector ID Field 12: this field is written only when the track is formatted. The ID field provides the sector identification that is used by the controller when a sector must be read or written. The first three bytes of the field is the ID address mark 14 which is a unique code with missing clock transitions that indicates the beginning of the ID field. This is followed by a byte 16 which identifies the upcoming data field as ID, followed by four bytes of ID 18. The four bytes indicate cylinder number, side number, sector number and sector size. Following the ID are two bytes of CRC. The FDC supplies the ID address mark and CRC, and the processor supplies the sector ID. (2) Post ID Field Gap 22: referred to as Gap 2, it is written during formatting. On subsequent write operations the drive's write circuitry is enabled during this gap and the trailing bytes of the gap are rewritten each time the sector is written. During read operations the trailing bytes, synch field 24, are used to synchronize the data separation logic with the upcoming data field. (3) Data Field 26: the first three bytes of the data field are the data address mark 28, a unique code with missing clock transitions that the FDC recognizes. This is followed by byte 30 which identifies the upcoming data field as data, which is followed by the data stream. The last two bytes of the data field are CRC 34. (4) Post Data Field Gap 36: the post data field gap (Gap 3) is written when the track is formatted and separates the preceding data field from the next ID field on the track. The gap length is program selectable. Following a sector write operation the FDD write amplifier is disconnected during this gap. A synch field 38 follows Gap 3.

In addition to the sector information a track also contains three additional fields. They are: (1) Preindex gap (written when the track is formatted. It contains 80 bytes of hex 4E followed by a synch field of 12 bytes of hex 00.); (2) Index address mark (one index mark is written during format and is a unique code that indicates the beginning of a track); and (3) Post index gap (GAP 1) (written when the disk is formatted, the field is used to handle the discontinuity that occurs when write logic is enabled for write track commands). There is shown in Fig. 2 a conventional computer system 40 such as an IBM PC, a Mclntosh, or any other computer which includes a floppy disk drive 42 including a floppy disk controller (FDC) and in the usual fashion may include a display 44, hard disk 46, keyboard 48, and CPU and memory 50. The electronic floppy disk emulation system 52 according to this invention is formed as a cartridge 54 so that it is conveniently received by a conventional floppy disk port 56 and floppy disk drive 42. This same cartridge containing the electronic floppy disk emulation system 52 according to this invention also fits directly into a portable computer 60, Fig. 3, which may conventionally include a display 62 and keyboard 64, CPU and memory 66, RAM 68 and mass memory 70. In this case, however, the electronic floppy disk emulation system 52 and the cartridge 54 are plugged in as a daughter board directly into RAM 68 at the mother board receptacle 72, Fig. 4, in computer 60.

Read/write amplifier 88, Fig. 5, is powered by a three-volt battery 84 and its coil 74 magnetically couples with magnetic read/write head 76 in floppy disk drive 42. Read/write head 76 includes the usual erase amplifier 92 and read/write amplifier 78, which generate the fields which will couple with coil 74 and gap 80. Coil 74 resides in the area normally occupied by floppy disk 82 along the axis of travel of read/write head 76. The electronic floppy disk emulation system according to this invention replaces the floppy disk surface with coil 74 physically located along the head 76 proximate gap 80, thereby creating a transformer. A coil placed anywhere along the magnetic core 75 of head 76 would be effective, but the best coupling occurs along the gap side because this is the side purposely left exposed to magnetic fields. Coil 74 is stationary and the emulation operating software described hereinafter, loaded in computer 40, positions the FDD 42 read/write head 76 over coil 74 so that the core of read/write head 76 is in contact with the core of coil 74. With FDD 42 in the write mode and electronic floppy disk emulator system (EFDES) 52 in the read mode, the current pulses representing the ones and zeroes in the data code are converted to magnetic flux by read/write coil 86 of FDD 42. Some of the flux is diverted to the EFDES coil 74 where a voltage, whose magnitude is dependent on the number of turns in the coil, is induced. In a practical circuit the voltage induced in coil 74 is typically a few volts in amplitude. This high amplitude allows for reliable noise-free operation with simple electronic circuitry. With EFDES in the write mode (FDD in the read mode), current pulses representing the ones and zeroes of the data code stored in the EFDES are converted to magnetic flux by coil 74. The flux lines are coupled to the core 75 of the FDD read/write head 76 and induce a voltage in read/write coil 86. The voltage induced must be within a range of the voltage that would be induced if a floppy disk were being read: that is, a few millivolts. The voltage is set by adjusting the level of current pulse sent to coil 74. Practical levels of current are less than 500μA. This current level allows a simple write amplifier design using small-geometry CMOS transistors. In addition, the low write current required allows for a low-capacity battery for powering the EFDES for sustained periods.

To actually transfer data via the magnetic circuit established by read/write head 76 and coil 74 a serial data stream must be generated by the EFDES that contains the data fields of sector header 10 for each sector of data transmitted. If sector header 10 was not present the floppy disk controller would terminate a read or write command. In addition to sector header 10 the floppy disk controller requires that a sector search be completed within two track times or it will terminate a read or write command. This limits the amount of data that can be transferred to a single tracks worth unless a system that includes special software for computer 40 is used.

Such a system that uses two sector addresses on the same track for transferring a single sector's data to or from memory and special software for computer 40 is part of the preferred embodiment of this invention.

To derive the two sector/cycle format when DOS requests a sector of data, a software device driver must be made part of the system. A DOS device driver is a program that provides a standard interface between EFDES and the operating system. The device driver is loaded at system boot time, based upon information in the Config.Sys. file, and essentially becomes part of the operating system. The device driver will translate DOS data block requests from EFDES to the two sector format required by EFDES.

When the FDD is accessed DOS assumes a floppy disk is in the drive and attempts a sector request. If EFDES is in the drive a sector not found error will be generated. The system then tries the unique two sector format. To a user it will appear that a standard floppy were in the drive. In addition to the software device driver special hardware in EFDES (generates the sector headers required to satisfy the floppy disk controller as well as controlling the actual transmission of data between FDD 42 and memory of EFDES.

To explain how the two sector format allows unlimited amounts of data to be transferred between FDD 42 and EFDES memory refer to Figure 6 which is a flow chart of the system when operating in FDD 42. A request for a data transfer is initialized by the operating system of computer 40 (DOS sector request 90) . If the sector is found the data transfers occur under normal DOS control (Sector found 92? Yes, continue in DOS 94). If a sector is not found within the two track times allowed by the floppy disk controller the EFDES device driver 96 is initialized. The device driver converts the DOS sector request into the two sector format that provides a EFDES memory sector request 98 which also includes a data bit indicating whether memory is to be read or written. The first part of the cycle, controlling the data transfer, requests sector 1.(100) and sector l's ID is stored in the floppy disk controller. EFDES transmits the sector 1 header from ROM to FDD 42 continuously until the floppy disk controller responds by sending a data address mark to EFDES or until a predetermined time has elapsed that is sufficient for the FDC to receive the header but less than two track times. A time of 150ms is allotted (sector 1 found in 150ms?) (102). If sector 1 is not found a sector not found flag 104 is set and the system returns to DOS control 100. If a data address mark is received by EFDES, data corresponding to the EFDES memory address and whether data is to read or written to the addressed memory is transmitted 104. This address is stored in a register within EFDES. The second half of the cycle commences by a request for sector 2(110) and sector 2 ID field is stored in the FDC. A sector 2 header is transmitted by the EFDES from ROM to the FDD 42. Upon receipt of the header by the FDC data is read from, or written to, EFDES memory addressed on the first half of the cycle 114. The cycle repeats itself for each sector of memory requested. (116) If the FDC misses the sector 2 header the cycle is repeated starting with a request for sector 1.(100)

The two sector system allows for a fixed read/write head position defined by the track number used in the sector ID field. In the preferred embodiment track 0 is used because DOS directs the read/write head to track 0 when a disk is entered into a FDD and, write precompensation is generally not used on track 0 data. The EFDES coil (74) is physically placed at the location that track 0 would occupy directly under the head 76 so that the cores of both the head and the coil contact. The two sector system allows an unlimited number of memory addresses and, in the preferred embodiment, the address is two bytes (2¹⁶). If each address corresponded to a block of memory 512 bytes in size (typical sector size) then the system allows access to 2¹⁶ (512) bytes of memory. The two sector system described used the same sector size for both sector 1 and sector 2. Sector 1, however, has only three bytes of data (two bytes for address and one byte to define a read or write) . The sector 1 size can be set to three bytes by setting the special sector size parameter to three bytes in the FDC. This will reduce the cycle time by 509 bytes in a system using 512 byte sectors.

The hardware required to implement the system (EFDES) consists of two major building blocks. They are the memory and the EFDES controller. EFDES's primary use is for transporting files from a portable system to desktop PC via the FDD (and vice versa) and need only have a storage capacity slightly greater than the maximum file length that would be exchanged between the computers. A capacity of one megabyte would allow transfer of most programs stored on floppies.

The EFDES memory is organized so that it is fully addressable, on a word basis, when operating in the portable computer and is therefore part of the computer's system RAM. This is an extremely important point. A significant savings in size, weight, power, and cost is realized since EFDES adds little additional system cost and eliminates the need for a floppy disk drive and a floppy disk controller. When a file is loaded in memory, for future transport to a desktop PC, the portable operating system stores data in EFDES in groups of bytes called sectors. The sector size can be 128, 256, 512 or 1024 bytes and, in this regard, is similar to a floppy.

The portable operating system (POS) uses predetermined sectors to store file allocation and file directory tables just as DOF does for floppies. A file that is loaded ir. EFDES from a FDD uses this sector organization and, when EFDES is connected to the portable computer, the stored data is down-loaded into the hard disk memory under control of the POS. This action clears data from EFDES's memory so that it is free to operate as system RAM. Figure 7 shows the block diagram of EFDES operating from a 32 bit data bus and a 20 bit address bus.

The EFDES memory 120, for this example, is organized into 512 rows by 512 columns x 32 bit words which corresponds to more than one megabyte of memory. To address this memory 18 bit addresses are required (124). The 18 bit words are decoded by the row and column decoders 122 so that any 32 bit word can be addressed. The memory address can come from the POS, when operating in its portable computer, or from the EFDES controller, when operating in a FDD. The addressed word is sent to the 32 bit data bus, when reading memory, or when writing to memory, the data on the data bus is written into the addressed memory location. When operating in a FDD the EFDES controller 118 directs data to the address bus 124 for transmission between memory 120 and the FDD.

The system operates from a 3V battery which is charged when EFDES is in the host computer, Figure 8 shows the equivalent block diagram of EFDES when operating in the host. The EFDES Controller is essentially disconnected from the system by connecting the Chip Enable (CE) to logic 0. What is left is RAM organized for system use.

Figure 9 shows the block diagram for EFDES when operating in the FDD. The EFDES controller 118 supplies the 18 bit address it received during the first half of the two sector cycle to the row and column decoders. If RDM (read memory) is true the selected word from memory 120 is sent to controller 118 via the 32 bit bus 126. The word is loaded into a shift register where it is serialized into the data stream sent to FDD 42, via coil 74 and head 76, during the second half of the two sector cycle. If WRM (write to memory) is true then a data word transmitted by the FDD and shifted into the shift register of controller 118, is sent to memory 120, via data bus 126, where it is written to the addressed memory location.

The EFDES controller 118 contains the read only memory and logic for sector 1 and sector 2 header generation, logic for memory 120 address control, memory data input/output control, logic for controlling the two sector cycle, CRC generation and the read and write amplifiers and associated logic. The overall block diagram of EFDES Controller 118 is shown in Figure 10. The major parts of this block diagram are shown in Figure 11, 14, 15, 16, 18 and 20 and are used to explain the controllers operation. Figure 11 shows the read/write logic for EFDES. The main component blocks are the clock generator 152, read amplifier 136, write amplifier 148 and the MFM encoder 150 for the write amplifier. The clock oscillator 120 must have enough accuracy to be within the capture range of the FDD 42 voltage controlled oscillator (typically +/- 5%). Additionally the oscillator accuracy must be good enough to accurately strobe data when synchronized by a 101 data stream. Data changes of 101 produce the maximum spacing between synch pulses for the clock phasing logic. The clock is phase corrected to 1 part in 8 on each transition of the read data. This is accomplished by dividing the clock oscillator by 8 and presetting the divide by 8 counter 130 to (2) on each transition of read data. The read data transition triggers FF 132 to the zero state which presets the counter to (2). The AND gate 134 output is true when the counter is at (2), setting FF 132 back to the one state.

The (4) output of counter 130 is used as the clock output and the output will go positive in two oscillator cycles after a read data transition. The system allows clock to data phasing error of +25% and -50%. The digital phase lock produces 12% error (1 part in 8) which allows for a maximum frequency error of 62%. A 101 data field does not produce a data transition for four clock periods. The frequency error accumulates during the four clock periods and can be a total of 62%. The frequency error allowed, therefore, is 62 / 4 = 16% +/- 8%.

The read amplifier 136 must convert the read data transitions from the FDD head to a data stream that can be clocked into the 32 bit shift register. Figure 12 shows the timing diagram of the read amplifier. The Schmitt Trigger 138 converts the coil 74 output to the recorded signal. The MFM 144 output triggers FF 132 which correctly phases the clock. On the next positive clock transition, flip flops FF 140 and FF 142 toggle. The FF 142 output clocks the MFM 144 output into the 32 bit shift register 174. The FF 140 output changes state which forces the MFM 144 output signal to zero.

The MFM output is generated by gates 220, 222 and 224 under control of FF 140 and the Schmitt trigger 138 output. The logic structure produces a positive pulse, one or two oscillator cycles wide for each transition of the Scmitt Trigger output 138. And gate 222 transmits positive transitions from Schmitt trigger 138 when FF 140 is in the logic zero state. NOR gate 220 transmits negative transitions when FF 140 is in the logic 1 state. The first positive transition is coupled to MFM 144 which synchronizes the clock. One or two oscillator cycles later the clock output goes positive. The output of AND gate 226 goes positive which triggers FF 140. This disables AND gate 222 which forces the MFM 140 to zero. Gate 220 is enabled so that when the output of Schmitt 138 goes to zero a positive transition of MFM 144 occurs. The data stream in Figure 12 is shown synchronized to the data from the FDD. The synchronization is accomplished with the synch gate which is true during the synch fields generated by the FDD. Since the synch field is a stream of O's, FF 142 is forced to a zero state by the MFM output, which correctly phases the FF 142 output. When writing to the FDD, the output of the shift register 174 must be converted to MFM. This is accomplished by the MFM encoder. The timing diagram for the MFM encoder is shown in Figure 13. The logic satisfies the algorithm for MFM that a clock bit is written if the last bit was zero and the present bit is zero.

A 32 bit word is parallel loaded in shift register 174. The word is serialized by shifting it out of the register by SCLK (shift clock). The frequency of SCLK is one half the clock frequency and is derived from FF142. One cycle of SCLK corresponds to a bit cell time. The algorithm for MFM states that a clock bit is written in the beginning of a bit cell if the present bit is zero and the previous bit was zero. To satisfy this statement an additional shift register stage 176 is required. Gates 230, 232 and 234 are used to implement the logic. Figure 13 shows a data pattern of 0101001 for B32, and B33 shows the same data pattern delayed in time one bit cell. B33 also shows that the previous bit, before the first zero of the B32 data pattern, was a zero. NOR gate 234 goes to the logic 1 state when B32, B33, SCLK and AM are low. AM is assumed to be low for this discussion. The output of gate 232 is in logic 1 state when B33 and SCLK are high. The logic produces an MFM code that is delayed 1/2 a bit time from the B32 output. The logic also generates a zero bit in the first half of the bit cell and a one bit in the second half of the bit cell. The gating arrangement can produce unwanted spikes at the output of gate 230 when the signals change state. FF154 iε used to remove any spike by using the inverted clock to strobe the data from gate 230 into it. The output of FF 154 is now delayed 3/4 of a bit cell time from Bit 32. The delay in the MFM bit stream is of no consequence since this data is sent to FDD 42 via the write amplifier.

The write logic 148 consists of FF 156 and gates 236 and 238 which are used to drive FET's 158. The write logic must produce a change in the polarity of the write current for each MFM pulse. FF 156 changes state on each positive transition of the MFM data and causes a current reversal in coil 74 if WE (write enable) is true. When WE is low both FET's are cut off allowing signals induced in coil 74 to be sensed by the read logic. The cycle control logic identifies which portion of the cycle is being executed; Figure 14 shows the block diagram of the cycle control logic. Each sector of the EFDES two sector has two parts. The first part is the transmission of the sector header from EFDES ROM and the second part is the data portion. FF 164 identifies the two parts as SRC (sector ROM control) and SDC (sector data control). Each of the two sectors are identified by FF 168 as ADD (address sector) and DAT (data sector) . The DAT signal is derived from FF 164 and FF 168 through AND gate 240. DAT identifies the data portion of the data sector. FF 164 changes state when the address counter of 162 of Figure 16 overflows. FF 164 also changes state when R counter 160 Figure 15 overflows if FF 168 is in the DAT state or if RFD (read floppy data) is true. Gates 242, 244 and 246 perform the logic.

FF 164 will lock in the SRC mode if FF 168 is in the ADD mode. RFD must go to its 1 state to advance the cycle. The system will continually send the sector one header to the FDD until the FDD responds by sending a data address mark to EFDES. Upon receipt of the data address mark RFD is set to its 1 state allowing the cycle to progress.

Figure 15 shows the block diagram of the ROM control. The ROM is organized into 32, 32 bit words which form the sector header information required by the FDC. The table below lists the ROM words. TABLE I

WORD NUMBER WORD HEX CODE DESCRIPTION

2 bytes 00, 2 bytes 4E CRC & GAP 3

1 thru 16 4 bytes 4E GAP 3 17 thru 19 4 bytes 00 Synch Field 20 3 bytes Al, 1 byte FE ID Address MARK 10 21 1 byte 00, 1 byte 01 Track & Side 1 byte 01/02 Sectorl/Sector2

1 byte 02 512 byte Sector Size

22 2 bytes CRC ID CRC

2 bytes 4E GAP 2

15 23 thru 27 4 bytes 4E GAP 2 28 thru 30 4 bytes 00 Synch Field 31 3 bytes Al, 1 Byte 4B Data Address MARK

20 Words 20 and 31 are the ID and data address marks, and words 29 and 30 are part of the 12 byte synch field that begins with word 28. The tri state output of the ROM is disabled when data is read from the FDD (RFD) or when in the data portion of a sector. 5 Gates 258 and 260 control OE (output enable) . The ROM output is disabled when CE (chip enable) is zero or when SDC is true or RFD is true.

In the ADD portion of the cycle ROM words 21 (ID Field) and 22 (CRC) are set to the sector one

30 address. ADD is used to change a bit in the sector byte and to change the CRC bytes. In the DAT portion of the cycle words 21 and 22 are set to the sector two address and CRC. A clock pulse must be eliminated from the first three bytes of the address marks. The missing pulse occurs on bit 5 of each byte. Or gate 250 gates the address for words 20 and 31 (address marks) to AND gate 252. Bit counter 180 is used to time each bit of the 32 bit word and is incremented by SCLK. When the bit counter is 1010 (5) and addresses 20 or 31 are true gate 252 produces a logic 1 for AM 178. The output is true for one clock time during bit 5. Referring to Figure 11, gate 234 is used to remove the zero pulse.

An overflow of the bit counter 180 indexes the R Counter 160 during the ROM header portion of a sector (SRC) . The R Counter 160 allows 32 words in ROM 166 to be addressed. The matrix decoder 182 decodes the 5 bit binary to the 32 addresses.

Certain addresses generated by decoder 182 are used for control. When the FDD 42 sends data to EFDES it first sends a synch field of 12 bytes of hex 00 followed by a data address mark. If perfect synchronization between EFDES and the FDC occurred then the synch field would coincide with words 28, 29 and 30. Perfect synch is not likely but it is certain, however, that FDD 42 will be sending a synch field of hex 00 during word time 29. Address 29 is used to enable gate 228 Figure 11 which allows MFM pulses to synchronize SCLK to its proper phase.

The data address mark that follows the synch field from FDD 42 must occur sometime during word times 30 or 31. OR gate 254 enables AND gate 256 during word times 30 and 31 and the MFM 144 data stream is gated to the output of gate 256. The gated output is labelled SDS (serial data stream) and is used as the data input to shift register 174.

SDS is connected to the D input of FF 184 which is clocked by SCLK. The first "1" bit of SDS will force FF 184 to its "1" state on the positive edge of SCLK. The one output of FF 184 is connected to the D input of FF 186 which is clocked by clock. One half a clock cycle later FF 186 goes to the "1" state which forces FF 184 to the 0 state. The circuit remains in this state until reset by address 29. The circuit produces a system reset pulse (SRST) that is one half a clock cycle wide. The pulse is the 1 output of FF 184. Since the data address mark is 3 bytes of hex Al followed by one byte of hex 4B, SRST must occur at the first bit time of this 4 byte word. SRST _esets bit counter 180 to a count of one. SRST resets R counter 160 to a count of 30. Two word timas later counter 160 overflows changing the state of FF 164 from SRC to SDC; . The two word times allows the first data word following the address mark to be shifted into shift register 174. Figure 16 shows the logic for address control of main memory 120. FF 192 and FF 194 generate a strobe pulse ST once every 32 bit times when SRC is true and every word time when SDC is true. A pulse at the output of gate 278 resets FF

192. One half a clock cycle later FF 194 is clocked to its 0 state by clock. The next clock pulse sets

FF 192 to the 1 state and FF 194 is reset to 1 by FF

192. The ST pulse generated is one half a clock cycle wide and is used to reliably strobe data in and out of registers. Strobe pulses are gated to the input enable (IE) of the 11 bit address register 170 through gate 202. SRST sets FF 198 to its 0 state and it remains in the 0 state until clocked to the 1 state by a pulse from inverter 280. The 0 output of FF 198 is labelled RFD (read floppy data) and is used to load the address register, inhibit ROM 166 and control the cycle logic.

When ADD is true ST pulses are gated to IE of register 170. Two word times after SRST, ST loads the first 11 bits of the first data word stored in shift register 174 into address register 170. The 11 bit address points to a memory block whose words are addressed by counter 162. At the end of two word times R counter 160 overflows putting the system in the SDC mode. Gate 276 is enabled and pulses representing either an 8 bit, 16 bit or 32 bit data word are sent to the address counter. The word length is programmable and gates 268, 270 and 272 decode the word select inputs. The three word lengths chosen are the most popular word lengths used in personal computers. It should be noted that words from ROM are always 32 bits long. Gates 264 and 266 are used to preset the address counter so overflow will occur when 512 bytes of memory have been addressed regardless of the word size selected. For example, if an 8 bit word is used 512 memory locations must be addressed. A 16 bit word has 256 memory locations and a 32 bit word has 128 memory locations. By setting bit 9 of the address counter to 1 the counter will overflow :,fter 512 pulses. If bits 8 and 9 are set to 1 the counter overflows after 128 pulses. One data word time after SDC is true address counter 162 is incremented by a pulse at the output of inverter 280. FF 198 is clocked to the 1 state and RFD goes to the logic 0 state disabling gate 202. Since the gate is disabled one half a clock cycle before ST the address register 170 holds its data. FF 200 is used to store the read/write bit that instructs the system during the DAT portion of the cycle. Write (WR) is the 1 output of FF 200 and read (RD) is the 0 output. Bit 16 from the data bus is connected to the D input of FF 200 and the output of gate 202 clocks the data in. As extra protection against unwanted writing to memory, FF 200 is set to the read mode just before strobing the data bit into FF 200. Gate 262 output is high when ADD is true and the R2⁵ output of R counter 160 is positive. When the R counter overflows R2⁵ goes to logic 0.

Figure 17 shows a timing diagram of what has been described.

Figure 18 shows the logic for converting serial data from the FDD to parallel data words and for converting parallel data words from memory to serial data. A 32 bit shift register 174 can be parallel loaded with 8, 16 or 32 bit words. The word select inputs 190 are connected to OR gates 282 and 284 and the gate outputs are connected to AND gates 286 and 288. The AND gates decode the word select inputs enabling 8, 16 or 32 bit inputs. When SRC is true the word select is over ridden and a 32 bit word input is selected. ST pulses strobe data from the data bus to the register 174 when ROE (ROM output enable) is true or when RD and DAT are true. Gates 194, 192 and 190 implement the logic. And gate 194 produces a read memory (RDM) signal. The signal enables a word from memory to be put on the data bus. SCLK shifts the data bits out of the shift register 174 through the 1 bit SR 176 and onto the MFM encoder for transmission to the FDD. The serial data stream created does not separate the data words. That is, the last bit of a word is followed by the first bit of another word which is the format used for floppy disks.

When writing to memory data from SDS is shifted into the shift register 174. The output of the shift register is enabled when WR, DAT and CE are true. Gate 298 performs this function. ST strobes data into memory when AND gate 298 output is true. The memory location that the data is stored in is set by the address register 170 and address counter 162. Gate 300 creates the WRM pulse. Switches 302 and 304 disconnect WRM and RDM from memory when CE is low.

The word length is programmed by connecting bits 25 through 32 to the bus for 8 bits, bits 17 thorough 32 for 16 bits and bit 1 though 32 for 32 bits. As discussed previously the first 32 bits of data are shifted into the register before the outputs of the register are enabled.

Figure 19 shows the timing diagram for a read and write to memory.

Floppy Disk Controllers use CRC 16 Check Sums for transmission error detection. The polynomial used for CRC 16 is: x¹⁶+x¹²+x⁵+l = (x+1) (x¹⁵+x¹⁴+x¹³+x¹²+x⁴+x³+x²+x+l)

and 2 bytes of CRC are generated. Figure 20 shows a hardware implementation for the polynomial. It consists of a 16 stage Shift Register 210 divided as shown. The exclusive OR gates 212, 214 and 216 function as adders without a carry.

When CRC 218 is true the circuit computes CRC continuously for the entire sector of data plus the data address mark. This happens because CRC is true from ROM word 30 thru the SDC portion of the cycle. When CRC 218 is low the data stored in the CRC 16 register 210 is gated to the bit stream sent to the MFM encoder 150. The CRC 16 register 210 is cleared after 16 clock pulses. The CRC bytes directly follow the last data byte and occur during ROM word 1. The first two bytes of ROM word 1 are zero and the last two bytes are hex 4E.

CRC 16 is computed only when reading a sector of memory. In this mode data is sent to the FDD 42 and the FDC must have a check sum (CRC 16) to compare against the CRC 16 result computed by the FDC, Figure 21 shows the flow diagram for EFDES in the read memory mode. Figure 22 is the flow diagram for the write mode.

EFDES is powered by a button cell. When operating in the portable system the battery is constantly charged and is drained only when operating in the FDD. Although power consumption of EFDES is very low, means of conserving power when EFDES iε removed from the portable computer assures long term retention of the data stored in EFDES. When data is not being transmitted to or received from the FDD EFDES will be put in a very low power stand by mode. The FDD motor drives a switch on the EFDES card, which connects the battery to EFDES's controller. When the FDD motor stops the switch retracts, turning power off to the EFDES controller, and EFDES returns to a low power standby state.

Although specific features of the invention are shown in some drawings and not others, this is for convenience only as each feature may be combined with any or all of the other features in accordance with the invention.

Other embodiments will occur to those skilled in the art and are within the following claims:

What is claimed is:

Claims

1. Electronic memory apparatus for emulating a magnetic disk, the apparatus being interconnectable with a magnetic disk drive system having a magnetic head, the apparatus comprising electronic memory means for storing signals representative of digital information, said digital information including sector header information having a format substantially identical to that of sector header information on a magnetic disk, and magnetic transducer means, in electrical circuit with said electronic memory means, for forming a magnetically coupled circuit with the magnetic head for information transfer between said electronic memory means and said magnetic disk drive system.

2. Apparatus according to claim 1, further comprising data conversion means, in electrical circuit with said electronic memory means and said magnetic transducer means, for converting data stored in said electronic memory means into a serial data stream and transmitting said data stream to said magnetic transducer means, so that data is transmitted in at least one direction between said electronic memory means and said magnetic disk drive system, wherein the data conversion means converts at least some of said data stored in said electronic memory means into a serial data stream emulating a sector header from a formatted magnetic disk.

3. Apparatus according to claim 2 wherein said sector header includes an identification field readable by the magnetic disk drive system to enable the magnetic disk drive system to complete a sector search.

4. Apparatus according to claim 3 wherein said sector header identification field includes any of an identification address mark, cylinder number, track number, side number, sector number, sector size, identification field, error checking code, read/write transition gaps or synchronization fields.

5. Apparatus according to claim 4 wherein said magnetic transducer means is adapted to be placed in proximity to a magnetic head in the magnetic disk drive system, and the sector header track and side numbers specify a magnetic head location corresponding to the location of the magnetic transducer means when said transducer means is placed in proximity to the magnetic head.

6. Apparatus according to claim 2 wherein said electronic memory means includes a data memory organized in groups of words equivalent in size to a sector of formatted magnetic disk data space.

7. Apparatus according to claim 6 wherein said groups of words in said data memory have associated addresses.

8. Apparatus according to claim 7 wherein said data conversion means includes means for converting signals stored in a memory group into a serial stream of data following said sector header.

9. Apparatus according to claim 8 wherein said data conversion means includes means for inserting a data address mark in the serial data stream ahead of the data obtained from said electronic memory group.

10. Apparatus according to claim 9 wherein said data conversion means includes error checking means for inserting error checking codes in said data stream.

11. Apparatus according to claim 10 wherein said error checking means inserts said error checking codes in said data stream following the data obtained from said electronic memory group so that the data stream emulates a sector of data from a formatted magnetic disk.

12. Apparatus according to claim 10 wherein said error checking is substantially identical to error checking by the magnetic disk drive system.

13. Apparatus according to claim 11 wherein said data conversion means includes means for emulating more than one sector of data from a formatted magnetic disk.

14. Apparatus according to claim 7, wherein said data conversion means includes means for converting a stream of serial data signals transmitted by the magnetic disk drive system through said magnetic transducer means into data signals storable in said data memory means.

15. Apparatus according to claim 3 wherein said data conversion means includes means for receiving, from said magnetic disk drive system, data signals corresponding to more than one magnetic disk sector.

16. Apparatus according to claim 13 wherein said data conversion means includes means for converting a stream of serial data signals transmitted by the magnetic disk drive system through said magnetic transducer means into data signals storable in said data memory means so that data can be transmitted between said memory means and said magnetic disk drive system.

17. Electronic memory apparatus for emulating a magnetic disk, the apparatus being interconnectable with a magnetic disk drive system including a magnetic head, the apparatus comprising electronic memory means for storing signals representative of sector headers and signals representative of data, said electronic memory means being organized in groups of data words equivalent in size to a sector of formatted magnetic disk data space, magnetic transducer means, in electrical circuit with said electronic memory means, for forming a magnetically coupled circuit with the magnetic head when placed in proximity with the magnetic head, so that data signals can be transmitted between said magnetic transducer means and the magnetic disk drive system, and data conversion means, in electrical circuit with said electronic memory means and said magnetic transducer means, for (i) converting data stored in said electronic memory means into a serial data stream and transmitting said data stream to said magnetic transducer means, and for (ii) converting serial data signals transmitted by the magnetic disk drive system through said magnetic transducer means into data signals storable in said memory means, so that data can be transmitted between said electronic memory means and said magnetic disk drive system, said data conversion means includes means for processing a first sector header followed by data from the disk drive system, corresponding to an electronic memory address and a read/write data signal, and a second sector header having a different identification field from said first sector header, followed by data read from, or to be written to, the memory group addressed by the data following the first sector header, depending upon the value of the read/write signal.

18. Apparatus according to claim 17 wherein said sector header includes an identification field readable by the magnetic disk drive system to enable the magnetic disk drive system to complete a sector search.

19. Apparatus according to claim 17 wherein said sector header identification field includes any of an identification address mark, cylinder number, track number, side number, sector number, sector size, identification field, error checking code, read/write transition gaps or synchronization fields.

20. Apparatus according to claim 17 wherein said magnetic transducer means is adapted to be placed in proximity to a magnetic head in the magnetic disk drive system, and the sector header track and side numbers specify a magnetic head location corresponding to the location of the magnetic transducer means when said transducer means is placed in proximity to the magnetic head.

21. Apparatus according to claim 17 wherein said electronic memory means includes a data memory organized in groups of words equivalent in size to a sector of formatted magnetic disk data space.

22. Apparatus according to claim 17 wherein said groups of words in said data memory have associated addresses.

23. Apparatus according to claim 17 wherein said data conversion means includes means for converting signals stored in a memory group into a serial stream of data following said sector header.

24. Apparatus according to claim 17 wherein said data conversion means includes means for inserting a data address mark in the serial data stream ahead of the data obtained from said electronic memory group.

25. Apparatus according to claim 17 wherein said data conversion means includes error checking means for inserting error checking codes in said data stream.

26. Apparatus according to claim 17 wherein said error checking means inserts said error checking codes in said data stream following the data obtained from said electronic memory group so that the data stream emulates a sector of data from a formatted magnetic disk.

27. Apparatus according to claim 17 wherein said error checking is substantially identical to error checking by the magnetic disk drive system.

28. Apparatus according to claim 17, wherein said data conversion means includes means for storing the data following the first sector header in a register reserved for address and read/write signal storage.

29. Apparatus according to claim 28 wherein said data conversion means includes an address counter for addressing words of an addressed memory group.

.

30. Apparatus according to claim 29 wherein said data conversion means includes means for selecting address counter word length.

31. Apparatus according to claim 17 wherein said memory means includes a read-only memory means for generating said sector headers.

32. Apparatus according to claim 31 wherein said read-only memory means stores data words of a selected width, and said data conversion means includes means for sequentially addressing the read-only memory means.

33. Apparatus according to claim 31 wherein said data conversion means includes shift register means, in electrical communication with said memory means, for being parallel loaded with data words from said memory means for conversion to a serial data stream.

34. Apparatus according to claim 17 wherein said data conversion means includes encoder means for coding the serial data stream in accordance with any of FM or MFM protocols.

35. Apparatus according to claim 34 wherein said data conversion means includes write amplifier means for interconnecting the magnetic transducer to the serial data stream.

36. Apparatus according to claim 17 wherein said data conversion means includes read amplifier means for converting signals from the magnetic transducer to a serial data stream.

37. Apparatus according to claim 17 wherein said data conversion means includes means for generating signals representative of a CRC 16 checksum.

38. Apparatus according to claim 17 wherein said data conversion means includes synchronizing means for synchronizing a clock oscillator with said serial data stream.

39. Apparatus according to claim 17 wherein said data conversion means includes means for receiving and recognizing address mark signals generated by the magnetic disk drive system.

40. Apparatus according to claim 17 wherein said data conversion means includes a shift register for converting a serial data word to a parallel data word.

41. Apparatus according to claim 40 wherein said data conversion means includes means for gating data words of selected length from said shift register to said electronic memory means.

42. Apparatus according to claim 41 wherein said data conversion means includes means for selecting the lengths of said data words.

43. Apparatus according to claim 40 wherein said data conversion means includes logic for timing and control of bus transfers between any of read-only memory, address register, shift register, and CRC circuit elements.

44. Apparatus according to claim 17, further comprising a battery connected to said memory means through a switch element that is closed by rotation of a floppy disk drive spindle.

45. Apparatus according to claim 17 wherein said data conversion means and said memory means are contained in a housing adapted to engage a 3 1/2 inch floppy disk drive.

46. Apparatus according to claim 2 further comprising external connector means, in electrical connection with said electronic memory means, for connecting external devices to said electronic memory means to randomly access memory word locations and to read or write data words to or from said memory word locations.

47. In a data processing system that includes a magnetic disk drive system and an operating system, the magnetic disk drive system having a magnetic head and a magnetic disk controller under the control of the operating system, the improvement comprising

A. a magnetic disk emulator including

(i) electronic memory means for storing data,

(ii) magnetic transducer means, in electrical circuit with said electronic memory means, for forming a magnetically coupled circuit with the magnetic head when placed in proximity with the magnetic head, so that data signals can be transmitted between said magnetic disk emulator and the magnetic disk drive system, and

(iii) data conversion means, in electrical circuit with said electronic memory means and said magnetic transducer means, for converting data stored in said electronic memory means into a serial data stream and transmitting said data stream to said magnetic transducer means, and for converting serial data signals transmitted by the magnetic disk drive system through said magnetic transducer means into data signals storable in said electronic memory means, so that data is transmitted between said electronic memory means and said magnetic disk drive system, and B. software means for enabling operation of said magnetic disk emulator.

48. A processing system according to claim 47 wherein said software means includes a device driver for generating a first sector identification field for transmission to the disk controller, followed by a block of data representing an electronic memory group address and a read/write signal, and a second sector identification field for transmission to the disk controller, followed by transmission of a block of data from the disk drive and disk controller to a selected memory group in the disk emulator, said memory group being addressed by the block of data following the first sector identification field if a READ signal was received, or by a block of data transmitted from the addressed memory group in the disk emulator to the disk drive system.

49. A processing system according to claim

48 wherein different memory groups are addressed by changing the address data following the first sector identification field.

50. A processing system according to claim

49 wherein data in said electronic memory means is organized into files, file directories and file allocation tables.

51. A processing system according to claim

50 wherein said software enables use of conventional magnetic disks.

52. A processing system according to claim 47 wherein said software means automatically enables operation of the magnetic disk emulator.