WO1992015177A1

WO1992015177A1 - Apparatus for two wire communication with memory device

Info

Publication number: WO1992015177A1
Application number: PCT/US1992/001304
Authority: WO
Inventors: William H. Wehrmacher
Original assignee: Datakey, Inc.
Priority date: 1991-02-15
Filing date: 1992-02-17
Publication date: 1992-09-03

Abstract

A circuit is provide which allows two wire communication between a key (Fig. 1) containing a memory device (18) and a key reader (Fig. 3). The power necessary to drive the circuit contained in the key (Fig. 1), as well as all command signals, address locations and data input/output are multiplexed over one wire (12) with the other wire (14) being used as a ground wire (Gnd). By multiplexing the power, commands and data in this fashion, the interconnect mechanism between the key portion of the circuit (Fig.1) and the key reader portion of the circuit (Fig. 3) has been greatly simplified.

Description

Apparatus For T p Wire rnmmunication With Memory Device

Background Of the Invention

1. Field Of The invention

This invention relates to two wire communication, and more particularly to two wire communication with a memory device in which the power and the input/output signals are multiplexed.

2. Description Of The Related Art

The art described in this section is not intended to constitute an admission that any patent, publication or other information referred to herein is "prior art" with respect to this invention, unless specifically designated as such. In addition, this section should not be construed to mean that a search has been made or that no other pertinent information as defined in 37 C.F.R. § 1.56(a) exists.

U.S. Patent No. 4,556,958 entitled "Device For Single Line Bidirectional Data Transmission Between An Intelligent Card's Microprocessor And A Second Processor", issued December 3, 1985 to Ugon, is directed to a device which requires three wires to communicate with a second device. One line is used as a ground, a second as a power supply and a third as a bidirectional signal line. One disadvantage of this device is that a separate line is required for supplying power to the portable data device, which is not required by applicant's invention. U.S. Patent No. 4,363,121 entitled "Method And System For

Simultaneous Bidirectional Transmission of Information", issued December 7, 1982 to Schlyter, is directed to two wire communication apparatus. However, power is supplied to each device from an independent source, unlike applicant's invention. Summary Of The Invention Applicant has provided an inventive circuit which allows two wire communication between a key containing a memory device, and a key reader. The power necessary to drive the circuit contained in the key, as well as all command signals and data input/output are multiplexed over one wire, with the other wire being used as a ground wire. By multiplexing the power, commands and data in this fashion, applicant has greatly simplified the interconnect mechanism between the key portion of the circuit and the key reader portion of the circuit. Brief Description Of The Drawings

Fig. 1 is a circuit schematic of the circuitry inside the mechanical key; Fig. 2 is a timing diagram showing waveforms A, B, and C at various points in the circuit of Figure 1; Fig. 3 is a circuit schematic of the driving circuit for the key reader;

Fig. 4 shows the timing diagram for a WRITE command; Fig. 5 shows the timing diagram for a READ command; Fig. 6 is an alternate embodiment of the circuit of Figure 1; Fig. 7 is an alternate embodiment of the circuit of Figure 3, and Fig. 8 is a second alternate embodiment of the circuit of Figure 3.

Description Of The Preferred Embodiments

While this invention may be embodied in many different forms, there are shown in the drawings and described in detail herein specific preferred embodiments of the invention. The present disclosure is an exemplification of the principles of the invention and is not intended to limit the invention to the particular embodiments illustrated.

Referring now to Figure 1, a schematic diagram of the circuitry inside the electronic key is shown in which diodes CR, through CR₄ act as the polarity adjust portion of this circuit, which is referred to generally at 10. This portion of the circuit is provided so that when the circuit is connected to the mechanical key, it may be built symmetrically about the pair of contacts allowing the device to be inserted into an appropriate receptacle in either direction. This provides ease of use for the holder of the device. If the mechanical portion of the key is provided with means for ensuring a single orientation of insertion then this portion of the circuit may not be necessary. The pair of contacts are shown at 12 and 14, with 12 carrying all signals, both input and output, as well as carrying the operating power for this circuit. Contact or wire 14 is used as a return or ground wire. By using this circuit design the input/output signals and the power are "multiplexed", thereby greatly reducing the interconnect mechanism between the mechanical key represented by Figure 1 and the key reader circuit discussed below with reference to Figure 3.

Power generation and control is provided by diode CR₅ and capacitor C_ which has a value of 1 microfarad in the preferred embodiment. This portion of the circuit is shown generally as 16. The waveform at the input of wire 12 is a square wave which changes between two values, with the "LOW" value being defined as a logical "0" and the "HIGH" value being defined as a logical "1". The incoming signal on wire 12 is used to charge capacitor C, through diode CR₅ when the voltage value on wire 12 is "HIGH" or a logical " 1 ". Capacitor C, is disconnected from the incoming signal by the diode as the signal voltage drops below the capacitor voltage. When the incoming signal on wire 12 is at a "LOW" value or at a logical "0", the capacitor then discharges through the remainder of the circuitry, thereby providing power with adequate control to the circuit during those periods when the circuit is not driven by the key reader portion of the circuit, discussed below with reference to Figure 3. The selection of the value of the capacitor C, depends on the power requirements of the remainder of the circuitry. Additional regulation of the power may be desired and is available through standard regulating circuits well known to those skilled in the art.

The memory utilized in the preferred embodiment is an industry standard 93C46 EEPROM which provides 1024 memory locations, shown as circuit element U2 at 18 in Figure 1. This memory utilizes serial communications, which simplifies the de-multiplexing of instructions, address locations, and data, although similar approaches could be used with any type of electronic memory. Other memories of various larger sizes could be utilized as well, although this would increase the number of address bits necessary to specify a particular address location in memory 18. The changes required to utilize these various memories are considered routine engineering. For operation, memory 18 requires power, approximately 5 volts, which is supplied through pin 8 as VCC, and 4 signal lines: Serial clock (SK) which is pin 4; Chip Select (CS) which is pin 3; Data Input (DI) which is pin 5, and Data Output (DO) which is pin 6. The timing requirements and use of these signals to generate the instructions to read and write data to specific address locations in memory 18 are detailed further below.

Memory 18 requires certain combinations of high and low voltage signals to be presented sequentially to the DI (data in) and CS (chip select) pins at times determined by the high and low level transitions present at the SK (Serial Clock) pin of the memory. The internal circuitry of the memory decodes this data into several commands such as read; write, erase and the like. The command set for this memory is publicly available and its use is well known by those skilled in the art and is therefore not detailed here. For memory 18, data presented to the DI pin is intended to change at the falling edge of the signal on the SK pin and must be valid at the rising edge of the same signal. In addition, the CS pin must be at a high level for the memory to act on the data presented to the DI pin. This memory also has an DO (data out) pin which presents output data during read modes and a ready/busy signal during write or erase modes. These modes are sent back to the key reader circuit as described below with reference to the signal recovery and conditioning portion of the circuit.

All the signals which are inputs to this circuit are provided by changes in the voltage at the input 12 from a predetermined "HIGH" value to a predetermined "LOW" value. The circuit represented by Figure 1 provides output to the key reader circuit (Figure 3) by alterations in the current consumed by the circuit.

The signal recovery and conditioning portion of the circuit is shown generally as 20, and is comprised of two retriggerable mono stable multivibrators, MSA and MSB, referred to as circuit element U1_A at 22 and circuit -element U1_B at 24, respectively. The timing components of MSA 22 consist of resistor R_A and capacitor C_A. The timing components of MSB 24 consist of resistor R_B and capacitor C_B.

Fixing the period of a multivibrator using resistors and capacitors is well known in the art. The periods of these are chosen such that MSB's period is much longer than MSA's period. A factor of ten between the period of MSA and MSB is used in the preferred embodiment, although many other factors could be used with minor engineering changes.

Figure 2 is a timing diagram of the input waveform 12 (waveform A) at point A, and the waveform at point B (the output of MSA, pin 4). The period of MSA is shown as r_A, and the period of MSB is shown as r_B. The output (pin 4) of MSA 22 is used to generate a SK signal, based on the output of the polarity adjust circuit 10, which is input to memory 18 via pin 4. The input signal 12 is normally approximately 6 volts ("HIGH") in the preferred embodiment, and periodically is reduced to 0 ("LOW") volts, as discussed above. The change of input signal 12 to its "LOW" state triggers both MSA and MSB to their quasi stable state, during which the output of MSA changes to a low level. At the end of its quasi stable state (determined via timing components R_A and 0, the output of MSA returns to a high level regardless of the state of the input of MSA. Figure 2 shows two cycles of the input (waveform A) of MSA, one of the cycles with a period longer and one cycle with a period shorter than the quasi stable state of MSA (T_A). If the output of MSA (pin 4) is used as the source for SK to memory device 18, and the input to MSA (point A in Figure 1) is used as the source for DI (data in, pin 5 on memory 18), then it can be seen by those skilled in the art that both "HIGH" and "LOW" signal levels can be sent to and interpreted by memory 18. With the ability to transfer both "HIGH" and "LOW" signal levels to the memory 18 at will, any command sequence may be sent to memory device 18, as well as address locations and data. Many other circuit arrangements, other than the one shown as the preferred embodiment, could accomplish the same purpose and adapting them to work in the disclosed circuit is considered routine engineering.

The same signal transition that triggers MSA will also trigger MSB. When MSB enters its quasi stable state its output goes to a high level (pin 5, Waveform C in Figure 2). Waveform C is applied to the CS pin of memory 18 (pin 3). MSB's time constant r_B is longer than the period expected between sequential data bits as decoded by the memory 18 and MSA 22. Therefore, it remains in its quasi stable state until signal transitions fail to appear for longer than its quasi stable period, at which time its output (waveform C) returns to a low level. This is necessary because several of the commands used to control the memory 18 require that the CS pin be low for initiation.

Figures 4 and 5 show the signals required by a write command followed by a read command with timing diagrams for signals at several points within the device (waveforms A, B and C corresponding to the waveforms seen at points A, B and C in Figure 1). The timing diagram shown in Figures 4 and 5 includes a signal for DO (data out). This signal is in a high impedance state during the majority of the write command. Following the temporary transition of CS (waveform C), which initiates the write command, the memory 18 drives the DO pin to a low level and keeps it low for the duration of the write process, as is well known and understood to those skilled in the art and familiar with the 93C46. As the DO pin is driven low, Q_! turns "on", which causes Qj and R₅ to consume current, shown at 30 and 32 respectively. The circuitry described below with reference to Figure 3 detects this increased drain in current and determines that the memory is busy completing the write command. Data output from the memory device 18 is similarly detected during a read command, as shown by Figure 5. At the end of the memory 18's internal write command, the DO pin is driven high, Qj is turned "off", and Qi and R₅ cease to consume current. The key reader circuit described with reference to Figure 3 senses this drop in current drawn by the key and determines that the next command may be sent. It should be understood that the use of O_Λ and R_s is not always necessary to consume the required signal current. In some embodiments, depending on the driving capability of the memory 18 used and the sensitivity of the particular driving circuitry, a simple connection of the DO pin to the output of the polarity adjust circuit 10, with or without a current limiting resistor R_x (reference numeral 34 discussed below) is adequate. The selection of the connection scheme and consequent output current level is a compromise between ease of detection and current capacity of the driving circuitry. Variations on the preferred embodiment are considered to be routine engineering. Resistor R_l5 shown at 34 is included to provide some minimal but predictable current consumption that can be sensed by the key reader circuitry. This allows that circuitry to determine that a device is present and that both connections are in place. The value of resistor Rj can be any value that is small with respect to the data current and large enough to be easily detected by the device driver circuitry. In the preferred embodiment, R_x draws approximately 5 milliamps and R₅ draws approximately 10 milliamps of current. The higher current draw of 10 milliamps is defined as logical "0" while the lower current draw of 5 milliamps is defined as a logical "1". The idle current of circuit elements of MSA, MSB and the 93C46 (22, 24 and 18, respectively) is at or below 1 milliamp. Therefore, the current drain will fluctuate between 5 and 6 milliamps, which the circuit will consider to be a logical "1". R] and R₅ can be chosen to be any value as long as the idle current of circuit elements 22, 24 and do not cause the circuit to sense an artificial "0". Diode Dj is provided to isolate R, and R₅ from capacitor . This prevents these resistors from draining the capacitor, and current is only drawn by these resistors when the input 12 is driven by the key reader circuit. Resistor Re, shown at 36 is included to provide some ESD (electrostatic discharge) protection, as is well known in the art.

Referring now to Figure 3, a schematic of the driving circuit is shown. Much of this circuit relates to the microprocessor, shown at 39, which drives the circuit. Operation and control of the microprocessor and related circuitry is well known to those skilled in the art, and will not be discussed in detail here. Only the portion of the circuit which supplies power and sends commands and data to the "key" or portable data device shown in Figure 1, as well as sensing changes in current drawn by that device, will be described here. Operational amplifier U1_A shown at 40; R₁₂ shown at 42; transistor Oj shown at 44, and resistors Rι₃, R,₄, R_n, R,, shown respectively at 46, 48, 50, and 52, form a current independent constant voltage supply circuit, as is well known in the art. This circuit can be adjusted to supply a particular output voltage V^, shown at 56. This output voltage is approximately 6.8 volts in the preferred embodiment. Transistors Q₄ and Qj, shown at 60 and 62 respectively, can be used to force V^ to zero volts. This reduction in V^ from 6.8 to 0 volts initiates the mono stable multivibrator's MSA 22 and MSB 24's quasi stable periods. Both Q and Qj are controlled by microprocessor 39, which is also responsible for the control of the length of pulses required by memory 18. The voltage across R₁₃, shown at 46, varies according to the current consumed by the "key" shown in Figure 1. Operational amplifier U1_B, shown at 70, samples those changes in voltage across R₁₃, and applies a ground referenced voltage which is proportional to the voltage across R₁₃, to the input of the voltage comparator U5_A, shown at 72. The output (pin 1) of this comparator 72 signals the changes in the current drawn by the circuitry shown in Figure 1. When the mechanical key is drawing 10 milliamps across R₅ (logical "0"), pin 1 will be high, and visa versa for a logical "1".

It can be readily seen and understood by those skilled in the art, that if only Q is turned "on", the output pin, shown at 56, will be held at approximately 6.8 volts DC by resistor R₁₄, shown at 48. If the key or portable data device represented by Figure 1 is connected to the interface point, the resistor R, (see Figure 1) forces the voltage at 56 to drop according to the relative values of R and R_t. This voltage is sensed by voltage comparator U5_B, shown at 74, whose output (pin 7) allows microprocessor 39 to detect whether a "key" or memory assembly is present. It does this while keeping the voltage across the "key" or memory assembly, represented by Figure 1, small enough to prevent undesired alteration of data within the memory. It is well known by those skilled in the art that connections are unstable while they are moving with respect to each other. This portion of the circuit allows microprocessor 39 to determine when the connection is stable, and to then allow normal operation voltage to be supplied to 56. This minimizes the possibility of alteration of data during device insertion. Zenor diode D₃ serves to limit undesirable ESD (electrostatic discharge energy) from entering the system. Any number of devices other than a zenor diode which are suitable for this purpose exist and could be utilized with minor engineering changes. Referring now to Figure 6. an alternate circuit for the mechanical key portion of the circuit (shown in Figure 1 ) is shown in which a microprocessor 76 replaces the two retriggerable mono stable multivibrators 22 and 24, and also handles the necessary timing required by the rest of the circuit. Referring now to Figure 7, a simpler alternate circuit to that shown in

Figure 3 is shown in which ground referenced current sampler R₁₀, shown at 78 is equivalent to R₁₂ (shown at 42) in Figure 3. Circuit element U₆, shown at 80 sets the constant voltage of 6.8 volts.

Referring now to Figure 8, an alternate embodiment of Figure 3 is shown which may be utilized in lower voltage applications, such as battery powered circuits. The constant output of this circuit is approximately 5.2 or 5.3 volts. R_1S, shown at 82 replaces R<₂ current sampler of Figure 3. Qj₀, shown at 84 regulates the voltage supplied to the rest of the circuit. Voltage switch Qs, shown at 86, replaces transistors Q* and Qs of Figure 3 (shown at 60 and 62, respectively). When Qs is "on" the voltage across the key is a constant value, between 5.2 and 5.3 volts. When Qs is "off" the voltage across the key is 0 volts.

The invention described above can be utilized in many applications. For example, the key reader circuit could be incorporated into vending machines. Then instead of giving the person emptying the machines many different keys, one for each machine, as is currently the practice, the person could be given one key with the proper data encoded into the memory 18 to allow that key to open the vending machines. In fact, the key could be easily programmed such that the vending machines had to be opened in a certain order. Also, the key could be programmed such that the machine could be opened only once with the key. This would prevent theft by misusing the key.

Another application would be to use the invention to provide a key to replace many keys which work in conventional locks. One key could be used to open all the locks in a building or a home, etc. Each individual would be given a key which would allow access to a predetermined selection of the total locks in the site. The key could also be used in connection with a key-pad personal identification number (PIN) system so that if the key were stolen, a code must also be input to allow the door to open. The invention could also be utilized in connection with safe deposit boxes, or postal boxes, etc. This completes the description of the preferred and alternate embodiments of the invention. Those skilled in the art may recognize other equivalents to the specific embodiment described herein which equivalents are intended to be encompassed by the claims attached hereto.

Claims

WHAT IS CLAIMED IS:

1. Apparatus for two wire communication with a memory device, comprising: a first electronic device for processing data including a microprocessor; a second electronic device including a memory; each electronic device further including a transmission means for transmitting a signal to the other electronic device and a receiving means for receiving a signal from the other electronic device; first and second signal lines coupling the first and second electronic devices together, the first signal line being used as a ground line and the second signal line being a bidirectional signal line over which bit serial form information is transmitted by variations of a signal on the line, a first signal state being defined as "LOW" and a second signal state being defined as "HIGH", the second signal line also providing power to the second electronic device; the first electronic device acting as a voltage source which has an output which is independent of the current drawn by the second electronic device; first circuit means included in the first electronic device for converting memory commands, address information and data supplied by the microprocessor into serial bit form for transmission to the second electronic device via the transmission means as variations of a signal on the second signal line; second circuit means included in the second electronic device and operatively connected to the memory means for receiving the serial bit signal variations and decoding it into the memory command, address information and data and inputing these to the memory means; third circuit means included in the second electronic device and operatively connected to the memory means for receiving ouφut from the memory means and converting it into serial bit form for transmission to the first electronic device via the transmission means as variations of a signal on the second signal line; fourth circuit means included in the first electronic device for converting the signal variations on the second line into digital data which is input to the microprocessor.

2. The apparatus of claim 1 wherein the signal variations on the second signal line transmitted to the first electronic device are voltage variations.

3. The apparatus of claim 2 wherein the signal variations on the second signal line transmitted to the second electronic device are current variations.

4. The apparatus of claim 2 wherein the second electronic device further includes a capacitor which charges when the second signal line is carrying a "HIGH" and discharges to power the circuitry of the second electronic device when the second signal line is carrying a "LOW".

5. The apparatus of claim 4 wherein the memory means is a serial communication IK EEPROM.

6. The apparatus of claim 1 wherein the second circuit means is comprised of two retriggerable mono stable multivibrators operatively connected to the memory means.

7. The apparatus of claim 1 wherein the second circuit means is comprised of a microprocessor.

8. The apparatus of claim 1 wherein the first electronic means is incorporated into a plurality of vending machines and the second electronic means is incorporated into a key wherein the memory means stores data corresponding to the plurality of vending machines thereby allowing a single key to open a plurality of vending machines.

9. The apparatus of claim 1 wherein the first electronic means is incorporated into a plurality of locks and the second electronic means is incorporated into a key wherein the memory means stores data corresponding to the plurality of locks thereby allowing a single key to open a plurality of locks.