WO1992011589A1

WO1992011589A1 - Programmable divider up/down counter with hysteresis

Info

Publication number: WO1992011589A1
Application number: PCT/US1991/009507
Authority: WO
Inventors: John Franklin Hamilton, Jr.
Original assignee: Eastman Kodak Company
Priority date: 1990-12-17
Filing date: 1991-12-13
Publication date: 1992-07-09

Abstract

A pulse frequency divider for two opposed pulse trains comprises an up/down counter and a comparator which tracks the net counts of the combined (and oppositely sensed) pulse trains. Means are provided for separating the counting loop positions from which the output (divided-down) pulses are generated for the two opposed pulse trains. This separation prevents the counter from sending bursts of output pulses in the presence of small oscillations such as those caused by mechanical vibration. The separation or hysteresis value corresponds to the threshold amplitude to which the counter will be sensitive. Both the hysteresis and the divisor values are programmable.

Description

PROGRAM ABLE DIVIDER UP/DOWN COUNTER WITH HYSTERESIS Technical Field of the Invention

This invention relates to high resolution positioning systems and, in particular, to those positioning systems using a high resolution incremental position encoder which is to be monitored by a small computer. Background of the Invention

In many applications it is desirable to have an up/down counter which divides the number of counts received by a divisor which is programmable. These counters are useful in electro-mechanical systems which need to coordinate the relative timing of electrical events with respect to mechanical events. Such counters are well known and have been disclosed, for example, in US Patent No. 4,713,832 to Hutson with an emphasis on anti-aliasing and asynchronous read/write features.

Often a high resolution incremental encoder is used as part of a servo mechanism for producing uniform motion or precise positioning of a mechanical component. US Patent No. 4,591,969 to Bloom et al discloses such an electromechanical system using a dc servomotor to position a document for printing. Also, US Patent No. 4,669,042 to Abe et al discloses a positioning control system for robot motion.

Often it is useful for another microprocessor or computer, other than the one involved directly in the servo loop, to use the output signals from the optical encoder for other purposes such as position reports and the initiation (or termination) of other associated electromechanical processes. While the encoder pulses must provide high resolution for the primary control loop, they need not be as highly resolved when used to initiate and terminate other processes. If the microprocessor is interrupt driven, it is undesirable to expose the microprocessor to highly resolved pulses as the interrupts could be unduly burdensome to the microprocessor. Accordingly, a divide-by-n counter is useful as a filter or buffer standing between a high frequency pulse generator (the optical encoder) and a low frequency event handler (the microprocessor) .

Problems can be encountered when a microprocessor is used to monitor (low frequency) position interrupts for a mechanical component which is susceptible to vibration. Because the encoder is a high resolution device, any vibration will generate a burst of pulses, first for motion in one direction, then for motion in the other direction, etc. Even though the up/down counter is adequate for counting these fluctuations correctly, its filtering ability is now impaired. Suppose the up/down counter were configured to divide by 100, and also that the vibration amplitude caused a maximum displacement corresponding to + 2 counts. If the event counter position were 49 when the vibration occurred, then the counter would fluctuate momentarily between 47 and 51 with no ill effects. If, however, the counter position were at 99, then the counter would fluctuate between 97 and 01 (by wrapping around) . Such a fluctuation would cause an interrupt to be issued on each 99-to-0 and each 0-to-99 transition, with the net effect of creating a burst of interrupts with a frequency twice that of the vibration. Under such circumstances, divide-by-n up/down counters provide inadequate protection against bursts of interrupts. SUMMARY OF THE INVENTION This invention provides a programmable up-down counter which accomplishes the divide-by-D function in a way which offers a programmable immunity to undesirable counter fluctuations such as those caused by mechanical vibration. The immunity level is defined by the largest counter fluctuation which will not cause a burst of interrupts. The immunity to fluctuation is accomplished by extending the counting loop length from D steps of D+H steps. Then, when counting up and step D+H is encountered, an interrupt (or "terminal count") is issued and the counter is reset to step H. When counting down and step 0 is encountered, an interrupt is issued and the counter is reset to step D. Thus, the steps from D to D+H and the steps from 0 to H represent the same state. The fact that the up-counting interrupts and the down-counting interrupts are given in different positions on the counting loop gives rise to the term "hysteresis". The positional inaccuracy associated with this hysteresis is H steps on the counter, but for the previously discussed low resolution application of a monitoring microprocessor, this error is insignificant. Brief Description of the Drawings

Fig. 1A is a state diagram of a bidirectional dividing counter that is well known in the prior art;

Fig. IB is a state diagram of the bidirectional dividing counter shown in Fig. 1A but with two additional states (A and D) ;

Fig. IC is a state diagram of a bidirectional dividing counter further simplified by separating the terminal count (TC) from the setting of the counter value;

Fig. ID illustrates a different type of schematic for the same state diagram shown in Fig. IC;

Fig. 2A is a state diagram of a bidirectional dividing counter having both interlock and hysteresis;

Figs. 2B-2C illustrate the forward and reverse paths lying between two TC-generatiπg transitions;

Fig. 2D illustrates a different type of schematic for the same state diagram shown in Fig. 2A; Fig. 3A illustrates a counter with a divisor of 9 and a hysteresis of 3;

Figs. 3B-3C illustrate the forward and reverse paths having intermediate counting states of 3; Fig. 3D illustrates a line or schematic for the same state diagram shown in Fig. 3A;

Figs. 4A-4D are examples of divide-by-seven counter with hysteresis values of 2, 4, 6 and 8 respectively; Fig. 5A is a schematic state diagram and timing diagrams of a bidirectional dividing counter shown in the prior art;

Figs. 5B-5C are schematic diagrams and timing diagrams of bidirectional dividing counters having hysteresis of 0 and 3 respectively;

Figs. 5D, 5E and 5F are schematic diagrams and timing diagrams of bidirectional dividing counters that encounter larger oscillations to allow comparison in performance; Figure 6A is a diagram of a programmable divider with hysteresis;

Figures 6B-6C illustrate the diagram of Figure 6A folder over at the mid-point so that the top shaded state (D«ll) is next to the bottom shaded state (A«0) with the addition of two special values V_Q and V_λ ;

Figure 6D shows a programmable divider with hysteresis and value of V_Q«H+1 and V-«5;

Figures 7A-7P illustrate the operational steps of a counter in operation, and the state of the counter is shown in a key next to each bubble drawing;

Figure 8 illustrates a block diagram for a programmable divider with hysteresis; Figure 9 is a block diagram of the contents of block 102 in Figure 8;

Figure 10 is a block diagram of logic control in block 208 in Figure 9;

Figure 11 is a flowchart for the multiplexer (mux) logic within block 301 in Figure 10;

Figure 12 is a flowchart for logic control of the low-to-high transition detector in block 302; Figure 13 is a block diagram of the up/down counter control in block 303 in Figure 10;

Figure 14 is a flowchart for logic control of the divided pulse generator within block 304 in Figure 10;

Figure 15 is a flowchart for the load enable logic within block 602 in Figure 13;

Figure 16 is a flowchart for the count enable logic with block 602 in Figure 13;

Figure 17 is a flowchart for the up/down control logic within block 603 in Figure 13; and Figure 18 is a flowchart for the forward/reverse control logic within block 604. Description of the Preferred Embodiment

With reference to Fig. 1A, there is shown a state diagram of a bidirectional dividing counter of the type known in the prior art. In the diagram shown, the divisor is 9 because the states repeat every nine counts in either direction. The counter is a conventional up/down counter with two special transitions (l→O and 7→8) which result in the generation of a terminal count (TC) signal whenever they occur.

These special transitions are incorporated into the state diagram in Fig. IB by the introduction of two additional states (A and D) from which the TC signals are generated. It is assumed in this instance that the duration of the TC is not important. This means that asserting a TC and deasserting the TC and moving to the next counter value, is the operational equivalent to asserting a TC while moving to the next counter value, holding it for the duration of that count, and deasserting the TC on the next count. It is also assumed that the clock rate for running this counter is at least twice the frequency of the events being counted so that the TC may be asserted and deasserted between events.

If the counter shown in Fig. IC is counting up (i.e. counting forward events), it will move through states 4, 5, 6, and 7. Once at the next count, the counter moves to state D, which immediately causes a TC to be emitted, and then moves directly to state 8. At that point, any further up counts would simply result in the counter moving through 0, 1, 2, etc. If the counter is counting down (i.e. counting reverse events), it will move through states 4, 3, 2, and 1. On the next down event, the counter moves to state A, which immediately generates a TC, and then moves directly to state 0. Further down counts result in the counter moving 8, 7, 6, etc.

As the figure illustrates, all state transitions are reversible except for (l→ A →O) and (9→ D →IO) each require two steps for completion. For example, the first transition (1 -»^■ A) results in the TC signal being generated or asserted, while the second transition (A •*^■ 0) deasserts the TC signal on the very next clock pulse. Once again, the clock frequency is assumed to be at least twice that of the events being counted, the TC-emitting transitions (l→ A →O) and (9→D →IO) each move to completion before another event can occur. It should also be noted that each of these transition pairs corresponds to just a single count, the divisor is still nine even though there are eleven distinct states. It is also important to note that an alternating sequence of forward and reverse events can trigger multiple (forward) TC signals without traversing the proper counting loop. For example, the sequence 7 •*^■ D -f 8 → 7 → D → 8 -» 7 would spuriously report (2 TC's x 9 - 18) 18 steps of motion in the forward direction.

Fig. ID illustrates another type of state diagram in the form of a linear arrangement. This type of diagram will be useful in describing the properties of interlock and hysteresis below. The schematic of Fig. ID is a linear arrangement of counter states instead of the circular arrangement shown in Fig. IC. Although the schematic in Fig. ID is somewhat more convenient, the two forms are equivalent representations of the same counter.

With reference to Fig. 2A, a state diagram of a bidirectional dividing counter is illustrated that has the properties of interlock and hysteresis. Interlock means that an alternating sequence of forward and reverse pulses, of the type that might be generated by a small vibration, will result in the generation of no TC's or the generation of an alternating sequence of forward and reverse TC's. Put another way, small vibrations cannot generate two consecutive TC's of the same type (i.e. forward or reverse). In Fig. 2B, once a vibration occurs and resulting in a 9→ D →l transition and a forward TC, that path cannot be repeated without first traversing a 1+ A +9 transition and a reverse TC being generated. Counting all the way around from 1 up to 9 does not constitute a small vibration. Upon the occurrance of a large vibration, any sequence of forward TC's would ultimately be balanced by an equal number of reverse TC's on the return or reverse path. It is important to note that because of this characteristic, vibrations cannot introduce spurious TC sequences which could be mistaken for actual travel in some given direction.

Hysteresis makes reference to the shape of the forward and reverse paths as shown in Fig. 2C. The degree of hysteresis refers to the number of intermediate counting states lying between the two TC-generating transitions 9→ D →l and l→ A →9 can follow each other indefinitely without traversing any intermediate counting states.

The linear version of this state diagram is shown in Fig. 2D. Fig. 3A illustrates a state diagram for a counter with a divisor of 9 and a hysteresis of 3. It can be seen from the state diagram that the TC-generating states 12 → D →4 and l→ A →9 cannot immediately follow one another. The only sequences that will allow the two counting states to follow one another are 12 → D → 4 -»- 3 → 2 -*^• 1 -»^■ A → 0 with intermediate counting states 3, 2, and 1 and 1 → A → 9 → 10 → 1 → 12 -»^■ D → 4 with intermediate counting states 10, 11 and 12. In either case, there are three intermediate states. The number of intermediate states is chosen to be the same in each direction to keep the divisor the same in each direction, although this need not be the case. Once again, Fig. 3C shows a state diagram of a counter having "hysteresis" but drawn in a linear fashion. One should note from the diagram that the total number of states required is always 2 more than the sum of the divisor (9), and the hysteresis, (3). Accordingly, in this instance, we have 9 + 3 + 2 ■ 14 states with A and D and the states 1 through 12.

Illustrated in Figs. 4A through 4D there are examples of a divide by 7 counter with hysteresis values of 2, 4, 6, and 8 respectively. It should be noted that the hysteresis value may exceed the divisor if desired.

Figure 5A shows a prior art divider without interlock or hysteresis which is being subjected to a series of small oscillations which is represented as an alternating sequence of forward and reverse pulses, to follow the logic traces using the timing diagrams in the lower portion of Fig. 5A. Starting at the top , the forward pulse train FPT and the reverse pulse train RPT provide the alternating pulse sequence. The forward flag FWD is asserted until time 7 at which point the reverse pulse is sensed and FWD is deasserted to indicate reverse motion. A second forward pulse is sensed at time 11 which asserts FWD until time 15. The counter was assumed to start with a value of 7 and counts up (or down) as FPT or RPT signals are sensed. Thus, on sensing the first forward pulse (time 3), the counter moves up from 7 to D. At this point, a TC is asserted, and the counter moves to 8, and the TC is deasserted (time 5). All this occurs before the next RPT pulse which moves the counter down to 7. This cycle is shown four times with the result being a sequence of spurious forward pulse train divided FPTD signals which would falsely indicate a forward motion corresponding to four full cycles of the counter. Clearly, one skilled in the art can easily see how this example can be modified to produce spurious RPTD signals as well.

Fig. 5B illustrates the same example used earlier but for a divider counter with an interlock and hysteresis of 0. Starting with a counter value of 9, the first forward pulse moves the counter to state D, a terminal count TC is generated and the state then changes to counter value ■ 1. As into he above example, the TC results in a FPTD pulse to be generated. However, in this instance, the reverse pulse moves the counter from 1 to state D which results in the generation of a TC and then moves the counter to 9. Thus, the FPTDS signal is balanced by an immediate RPTD signal. As the alternating sequence of FPT and RPT pulses come in, an alternating sequence of FPTD and RPTD pulses are sent out. In this way, the interlock property of this counter has avoided the spurious sequence of consecutive FPTD (and RPTD) signals. Fig. 5C illustrates the same example used earlier but for a divider counter with an interlock and hysteresis of 3. Beginning with a counter value of 12, the first forward pulse moves the counter to state D, a terminal count (TC) is generated, and the state then changes to a counter value ■ 4. Again, the TC results in the generation of a FPTD pulse. As the alternating sequence of FPT and RPT pulses come in, the counter simply moves back and forth between count values 3 and 4. Thus, no additional FPTD or RPTD pulses are sent out. The reason for this action is the hysteresis of 3 has separated the locations of the forward and reverse TC-generating states. The small oscillation of forward and reverse pulses is not sufficient to cause a large enough displacement to trigger both types of terminal counts. This scenario is the ideal or desired situation because the spurious (one-sided) output is avoided and so is the burst of balanced (two-sided) output.

In Figs. 5D, 5E and 5F a larger oscillation is shown. In this example, the amplitude is three pulses rather than one.

The counter in Fig. 5D is shown avoiding the spurious count problem, but still results in the paired generation of FPTD and RPTD pulses. The counter shown in Fig. 5E has an interlock and hysteresis of zero and is shown to behave in a similar fashion. Thus in both cases, it is possible for the output pulses to overload the monitoring microprocessor. In Fig. 5F, it illustrates a counter having interlock and a hysteresis of three, in accordance with the preferred embodiment, is capable of suppressing the undesirable burst of paired FPTD and RPTD output pulses. Accordingly, it should be noted that the hysteresis value is mqrammable so that if the larger oscillations were expected or likely to occur such that 4 FPT signals followed by 4RPT signals followed by 4FPT signals and so on, the hysteresis could be set at 4. This would mean that the separation between states A and D would increase by one in both directions. This being the case, oscillations of amplitude 4 or less could not generate a burst of interrupts and thus, would not overload the monitoring computer or microprocessor. Programmable Divider with Hysteresis

Figures 6A-6D illustrates how the values of the state variables correspond to diagram of states, for a programmable divider with hysteresis will be set with a divisor of 8 and a hysteresis of 2. After initialization, the device is shown for an event sequence of 8 forward, 3 reverse, 1 forward, and 1 reverse. In Figure 6A, a diagram of a programmable divider with the hysteresis is shown. This diagram can then be folded over as illustrated in Figure 6B, at the mid-point, until the top shaded state (D«ll) is adjacent the bottom shaded state (A-0). In this form (Figure 6C) , it can be seen that, in addition to zero there are two special values V_Q and V... V- is the value to load into the counter when the terminal value of zero is reached, and V. is the value which the counter will never exceed. As shown in Figure 6D, the value of V_Q is H+l and V-, is the integer part of (H+D/2). Hence, in this example V_«3 and V..-5. Because H+D is even the low order bit is 0, the value of odd indicating that there are two distinct states at the counter value of V- . The variables FWD and UP are used to determine which bubble corresponds to a given counter value.

For example, if the counter value is 4, FWD is ASSERTED, and UP is ASSERTED, then the bubble is at 4 on the lefthand column as shown in Figure 7B. However, if UP were DEASSERTED, but FWD is still ASSERTED, then the bubble would be in the righthand column as shown in Figure 7E.

Forward events occur between Figures 7B and Fig. 7C and 7E; Fig. 7E and 7F; Fig. 7F and 7G; Fig. 7G and 7H; and Fig. 7H and 71—between Fig. 71 and Fig. 7J is the next clock cycle—reverse events occur between Fig. 7J and Fig. 7K a clock cycle occurs between Fig. 7M and Fig. 7N then between Fig. 7N and Fig. 70 is forward event between Fig. 70 and Fig. 7P is a reverse event.

Fig. 7A shows the counter at initialization with the values of load_enable (LD_UP) and (LD_FWD) are arbitrarily ASSERTED while (LD_CNTR) is DEASSERTED. This means that the counter is initialized as counting up, signifying forward motion, and storing V-.-3. The compare bit (CMP), terminal count (TC) , and load (LD) variables are DEASSERTED indicating that the present count value is not ₁ that the count values is not 0 (the terminal count), and that the counter is not about to have a new value loaded into it. As the next two forward events (FE) are received, the count rises to 5. Notice that the compare bit is now ASSERTED indicating that V.«5 has been reached. The next forward event moves the bubble in the diagram, but does not change the count value (Fig. 7C and Fig. 7D) . The only change in the state variables is that UP is DEASSERTED. Four more forward events move the count value from 5 down to 1 as shown in Figure 7H. After the next forward event (Fig. 71), the count value reaches 0 which ASSERTS the terminal count and the counter load_enable ( D) . Note that on the following clock cycle (Fig. 7J) , the counter is loaded with the new value (V «3) which DEASSERTS both the terminal count and the load_enable. A reverse event is now received in (Fig. 7K) which lowers the counter value to 2, and DEASSERTS both the forward (FWD) and up (UP) state variables indicating that the motion is now reversed and the counter is counting down. Two more reverse events (Figs. 7L and M) move the counter value to 0 which again ASSERTS both the terminal count and the load enable. On the following clock cycle (Fig. 7N) , V. is again loaded into the counter, UP is ASSERTED, and both TC and LD are DEASSERTED. A forward event is now received in Fig. 70, which lowers the counter value to 2, ASSERTS FWD, and DEASSERTS UP, because of the change in direction of motion. Finally in Fig. 7P, a reverse event raises the counter to 3, DEASSERTS FWD and ASSERTS UP again, as the direction of motion has again changed. Description of Block Diagram With reference to Figure 8, there is shown a block diagram illustrating a typical application of a programmable divider with hysteresis. A high resolution position encoder 101 is used as part of the motion control system. The forward pulse train (FPT) signals 104 provide edges in proportion to the forward motion displacement, while the reverse pulse train (RPT) signals 105 do the same for reverse motion displacement. A programmable divider with hysteresis 102 generates the forward pulse train divided signals (FPTD) 106 and the reverse pulse train divided signals (RPTD) 107 as outputs. These outputs are sent to a monitoring microprocessor 103 which has two outputs, a data line 109 and a command line 110 goes from microprocessor 103 to programmable divider 102 to provide for its initialization and control.

Figure 9 illustrates a block diagram of the contents of programmable divider 102 shown in Figure 8. Latches 201 and 202 are used to synchronize the external data lines 104 and 105 (which are FPT and RPT respectively) to the local clock (not shown) . Once synchronized, these signals appear on lines 210 and 212 which are labeled forward train (FT) and reverse train (RT) respectively. Parameter registers 203 and 204 are used to hold the values V_ and V., respectively. The value V_Q is H+l, where H is the desired hysteresis value, and the value V. is the integer part of (H+D)/2, where D is the desired divisor. Multiplexer (Mux) 205 allows either V_Q or V. to be the initial value loaded into up/down counter 206. Comparator 207 compares the value V. with the value presently in up/down counter 206. Control logic 208 contains the logic for running up/down counter 206 and producing the output signals forward pulse train divided (FPTD) and reverse pulse train divided (RPTD) on lines 106 and 107 respectively. Command line 110 is comprised of 7 lines, two of these 7 lines go to V_ register 203 and v., register 204 respectively. The two command lines that go to the corresponding V_ and -_j^ registers 203 and 204 are simply the load_enable lines which are used to initialize the values stored in those registers. The remaining 5 command lines 110 are: RESET; a load_counter (LD_CNTR) indicator as to which of V_n and V₁ should be the initial value for the counter; the initial up/down setting for the counter (LD_UP); the initial forward/reverse setting for the motion direction (LD__FWD) ; and whether (H+D) is odd or even (ODD) . Other lines in programmable divider 102 are: the load_select (LD_SEL) line 215 for multiplexer (Mux) 205; the compare bit (CMP) line 216 from the comparator 207 and the terminal_count (TC) line 217 from the counter 206. There are three internal control lines 213 going to up.down counter 206 from control logic 208; these lines are: the load_enable line (LD); the count_enable (COUNT); and the count direction (UP) .

With reference to Figure 10, there is a block diagram of the contents of control logic 208 shown in Figure 9 which is comprised of four logic modules. Multiplexer (Mux) control module 301 sets either V_ or v., as the initial value of up/down counter 206. Multiplexer (Mux) control module 301 has two inputs as lines 305 which are RESET and LD CNTR and one output line 306 (LD__SEL) .

Figure 11 provides a flowchart of the logic with multiplexer (Mux) control module 301. Module 301 does one of two things; if the system is being held at RESET (which is the yes path from decision block 401 in Figure 11) then the load_select (LD SEL) output line is set to be the same as the load counter (LD_CNTR) input line shown in block 402 (Fig. 11). As a result, the command line LD_CNTR determines whether V_Q or V, is the initial value loaded into up/down counter 206 (Fig. 9). In the event the system is taken out of RESET (this is represented by the "No" path from block 401, Figure 11) , then LD_SEL is DEASSERTED as shown in block 403 (Fig. 11). Accordingly, this means that once the divider is operating only V. will ever be loaded directly into the up/flown counter 206.

Returning to Figure 10, it can be seen that low-to-high transition detector 302 converts the rising edge on line 210 (FT) to a single pulse of one clock cycle duration referred to as a forward event (FE) . Similarly, it converts RT to a reverse event (RE). In addition, if it should happen that a forward pulse and a reverse pulse should have been synchronized in the same clock cycle, the low-to-high transition detector 302 cancels them out and no forward or reverse event pulses are generated.

Figure 12 illustrates a flowchart which specifies the logic for low-to-high transition detector 302. Block 501 (Fig. 12) tests to see if FT is ASSERTED and if the previous value of FT, old forward train (OFT), is DEASSERTED. If these conditions are met, then a rising edge on FT has been detected. Moving on the "Yes" path to block

502, there is an identical test for a rising edge on RT. Block 504 is reached only if a rising edge has been detected on both FT and RT. Because these signals represent two motions which cancel, FE and RE are both DEASSERTED. Block 505 is reached only if a rising edge was detect on FT but not on RT. In this case, the FE line is ASSERTED and the RE is not. Block 503 is identical to block 502 except that it lies on the "No" path from block 501. Thus, block 506 can be reached only if a rising edge was detected on RT but not on FT. Accordingly, RE is ASSERTED and FE is not. Block 507 can be reached only if no rising edges are detected, in which case both FE and RE would be DEASSERTED. Block 508 puts the current values of FT and RT into OFT and ORT respectively in preparation for the next clock cycle.

Up/down counter control 303 is the most complex of the four logic modules in control logic 208. Figure 13 illustrates further details of control logic module 303. Load enable control 601 determines when a value is to be loaded into the counter. There are only two circumstances in which the load_enable (LD) line should be asserted: the first is when the system is held in RESET, and the second is when a terminal count (TC) is asserted. The count__enable control 602 determines when the counter should be allowed to increment (or decrement) . Because the counter load_enable control 6Q2 is always ASSERTED during RESET, count_enable is masked until RESET is DEASSERTED. At that time, the counter should count when either FE or RE is ASSERTED, if UP is ASSERTED, the compare bit (CMP) is ASSERTED, and ODD is DEASSERTED. This latter condition corresponds to the situation in which the counter has counted up to V₁ and on the next count needs to stay at V., and DEASSERT UP in preparation for counting down. Up/down control 603 determines whether the counter increments or decrements. The forward/reverse control 604 determines whether the counter is currently tracking forward motion or not. Flowcharts for each of the count components 601, 602, 603 and 604 that make up up/down control 303 are illustrated in Figures 15-18, respectively. Divided pulse generator 304 controls when a pulse is to be generated on either the line 106 or 107 in the form of FPTD or RPTD respectively.

With reference to Figure 14, a flowchart is shown which contains the logic for divided pulse generator 304. In the first decision, block 701 tests the condition of both RESET anrt TC. If the system is held in RESET or if TC is DEASSERTED, then following the "Yes" path to block 702 FPTD and RPTD are both DEASSERTED. If the ystem is not in RESET and TC is ASSERTED, then a pulse must be generated. Following the "No" path, the test in block 703 determines if FWD is ASSERTED or not. If "Yes", the block 704 sets FPTD to be ASSERTED (with RPTD still DEASSERTED), and if "No" then block 705 sets RPTD to be ASSERTED (with FPTD still DEASSERTED).

Figure 15 shows a flowchart for the load enable control logic 601. Decision block 801 tests to determine if either RESET or TC is ASSERTED. If yes then LD is ASSERTED as shown in block 802. If not, then LD is DEASSERTED as shown in block 803. A flowchart for load__enable control logic 601 is shown in Figure 16. In the first block 901 test is made to determine if RESET is ASSERTED. If so, the "Yes" path leads to block 904 where COUNT is ASSERTED. If the test in block 901 is "No" the path goes directly to block 905 in which COUNT is DEASSERTED. However, if either FEW or RE is ASSERTED, then the "Yes" path lead to block 903 in which a final test is made. The results of this test will be to ASSERT COUNT (block 904) unless it should happen that UP is ASSERTED, and CMP is ASSERTED, and ODD is DEASSERTED, in which case COUNT must be DEASSERTED (block 905). The reason for this somewhat complicated test is to account for the case in which the up/down counter has moved up to its maximum count (V₁) and must now begin counting down again. When the number of counts is even, the counter must "turn around" (i.e. UP becomes DEASSERTED but the count itself must remain unchanged). Thus, the value of the counter stays the same for two counts in a row This is accomplished by keeping COUNT as DEASSERTED.

A flowchart is shown in Figure 17 for up/down logic 603 in Figiπ«• 13. Block 1001 tests to see if RESET is to be ASSERTED if "Yes" the UP is set to be LDJϋp as shown in block 1009. If the system is not in RESET, then block 1002 tests to see if TC is ASSERTED. If it is, then a new value is loaded into the counter, and the next count direction expected for UP is ASSERTED which is set in block 1010. If TC is DEASSERTED, then the next test is to see if CMP is ASSERTED, as shown in block 1003. If this is true, then the counter is at the top of its count (i.e. it equals V_j), and the question then becomes whether the counter reached V-. on this clock cycle; or if it had reached it on an earlier clock cycle. Block 1004 tests for UP being ASSERTED. If it is not, then UP remains DEASSERTED as shown in block 1011. If UP is ASSERTED then the "Yes" path leads to block 1006 in which both event variables (FE and RE) are checked for inactivity. If this is the case, then UP remains ASSERTED as shown in block 1010.. If either event variable was ASSERTED, then the counter has just reached the top and UP must be DEASSERTED.

Returning to block 1003, if CMP is DEASSERTED, then the only reason to change the UP variable is if there is a change of motion direction on this clock cycle. Block 1005 checks the current setting of FWD. If FWD is ASSERTED, then block 1007 tests to determine if RE is ASSERTED. If this is correct, then a direction change has occurred and the value of UP must be toggled as shown in block 1012. If there is no RE event, then UP remains unchanged as shown in block 1013. Returning to block 1005, if FWD was DEASSERTED, this would indicate reverse motion, the block 1008 tests to see if FE is ASSERTED. Once again, if this were the case, a direction change has occurred and the value of UP must be toggled in block 1012. If there is no FE event, UP remains unchanged in accordance with the instructions in block 1013.

Figure 18 illustrates a flowchart for the forward/reverse control logic 604 in Figure 13. If the test in block 1101 indicates the RESET to be ASSERTED, then FWD is set to be LD_FWD as shown in block 1104. If the system is not in RESET, then block 1102 makes the determination of whether FE is ASSERTED. If this is the case, then a forward event has just been sensed and FWD must be ASSERTED as shown in block 1105. If FE is DEASSERTED, the block 1103 tests to see if FWD is already ASSERTED with no reverse event on this clock cycle; without RE being DEASSERTED. If this is the case, then FWD is unchanged in block 1105. If it is not. the case, then there has been a change of direction and FWD must be DEASSERTED as called for in block 1106. Programming and Use of Divider Counter with Hysteresis There are seven command lines which enable a user to perform all necessary initialization and control functions on the divider counter. These command lines are: Reset: causes each component of the divider to come to a known

(quiescent) state.

V_n Load Enable: causes the V- register to load whatever value is currently on the data lines. 11589

-22-

V__j Load Enable: cause the V, register to load whatever value is currently on the data lines.

Odd: is set to one or zero indicating that (H+D) is odd or even, respectively.

Load Up: is set to one or zero causing the counter to be initialized to count up or down, respectively.

Load Fwd: is set to one or zero causing the counter to expect forward or reverse motion, respectively.

Load Counter: is set to one or zero initializing the counter to the value stored in V. or V_, respectively.

The first step in using the divider is to assert the Reset line. The user then selects the desired values of D (the divisor) and H (the hysteresis). The value (H+l) is computed and presented to the data lines running to the divider. The V_ Load Enable line is asserted, and then deasserted, which loads the data value into the V_ register. Next the integer part of (H+D)/2 is computed and presented to the data lines. The V₁ Load Enable line is asserted, and then deasserted, which loads the data value into the V. register. At this point both register, V and V. , are initialized. Their load enable lines and the data lines will not be needed any further.

The Odd command line is then set to a one or zero indicating whether the value of (H+D) is odd or even. This line is set once, and must remain set as is for the duration of the session. The Load Up command line is set to a one or zero to indicate how the user wants the count direction initially set, up or down respectively. Likewise, the Load FWD command line is set to indicate which direction of motion should correspond to the initial count direction just specified. A one or zero indicates forward or reverse, respectively. Finally, the Load Counter command line determines which register, V- or V., provides the initial count value for the counter. A one or zero indicates V. or V_ respectively. The choice allows the user to receive terminal counts every cycle on the half-cycle (V.) or just every cycle at the cycle boundary (V_Q). At this point the divider is fully initialized and may be activated at any time by deasserting the Reset command line. Advantages and Industrial Applications

The advantage of this forward/reverse pulse divider is that it protects the monitoring computer from bursts of interrupts from undesirable counter fluctuations such as those caused by mechanical vibrations. Such interrupt bursts can unduly burden a monitoring computer.

Protection is also provided for near-simultaneous interrupt pairs such as those generated by a simple reversal of direction. Such interrupt pairs would be separated by a time proportional to the chosen hysteresis value.

Claims

WHAT IS CLAIMED IS:

1. In an up/down counter capable of tracking the position of a drive means using grating transitions for all conditions of mechanical vibration, characterized by: emitter means being coupled to s id drive means for generating direction signals indicative of the movement of said drive means in a given direction; said bidirectional displacement count being connected to said emitter means for counting said first displacement pulses and generating a terminal count pulse by counting a predetermined number of said first displacement pulses; control means including a microprocessor operation to perform a sequence of drive control operation in response to said terminal count pulses to operate said drive means; said bidirectional displacement counter is adapted to make and hold a predetermine d pulse count in a counting loop in response to error movement in either a forward or reverse direction of said drive means; and when said bidirectional displacement counter is about to generate a terminal count, said direction signals for one direction are counted at a different position in said counting loop than the signals from the opposite direction, so as to introduce hysteresis in that portion of said counting loop.

2. In the up/down counter as set forth in Claim 1 wherein said hysteresis value is programmable such that the counter may be adjusted to filter bursts of opposed pulses of a given size without the generation of terminal count pulses resulting from said bursts.

3. A bidirectional counter with count up and count down inputs and having programmable hysteresis characterized by: an up/down counter for counting up or down in response to count up or count down signals applied respectively to count up or count down inputs; a programmable divisor for the pulse frequency division based on the number of divisions in a counting loop of the combined pulse trains; and means for introducing hysteresis such t hat the divided down output pulses corresponding to one pulse train, are generated at a different position in the counting loop than the output of the opposed pulse train.

4. A programmable up/down counter having count up and count down inputs, said counter having programmable hysteresis within the counting loop characterized by: an up/down counter for counting up or down in response to count up or count down signals applied respectively to count up or count down inputs; a programmable divide-by-D function based on the number of divisions in the counting loop D for the pulse frequency division on the combined pulse trains; and means for introducing hysteresis by extending the counting loop length from D divisions to D+H divisions so that when counting up and the D+H division is reached and an interrupt signal is generated with the counter being reset to division H and when counting down an interrupt signal is generated when the 0 division is reached and the counter is reset to H.

5. The programmable up/down counter as set forth in claim 4 wherein the divisions from D to D+H and the divisions from 0 to H represent the same state.

6. The programmable up/down counter as set forth in Claim 5 wherein D+H/2 indicates that D+H is even if the remainder is 0 and a remainder of 1 means D+H is odd.

7. A divide down counter for use in a servo system, characterized by: a) means for receiving an input pulse train including up and down counts; b) means for dividing the input pulse train by a predetermined divisor D to produce a divided output pulse train having up and down counts; and c) means for providing hysteresis between the input pulse train and the output pulse train.

8. The divide down counter as set forth in

Claim 7 wherein said means for providing hysteresis is further characterized by: a counting loop having D divisions for the pulse frequency division of the combined pulse train; and means for extending the counting loop length to D+H divisions so that when counting up and the D+H division is reached, an output pulse is generated with the counter being reset to division H and when counting down an output signal is generated when the 0 division is reached and the counter is reset to division H.

9. The division down counter as set forth in Claim 8 wherein the divisions from D to D+H and the divisions from 0 to H represent the same state.