WO1991011796A1

WO1991011796A1 - Interleaved display selection scanner

Info

Publication number: WO1991011796A1
Application number: PCT/US1990/007118
Authority: WO
Inventors: Roger Green Stewart
Original assignee: David Sarnoff Research Center, Inc.
Priority date: 1990-01-29
Filing date: 1990-12-10
Publication date: 1991-08-08

Abstract

An array of pixel rows in a display is divided into a plurality of groups of pixel rows. Each group of rows is coupled to a signal generator which sequentially selects the rows of the group. The rows may be interleaved to provide an interlaced display pattern. In one arrangement each row of pixels is coupled to a line having two ends. A signal generator coupled to one end of the lines of a pixel group sequentially selects the pixel rows of the group. Another signal generator is coupled to the other ends of the pixel row lines to select the pixel rows of the group. In the event that one signal generator is defective, the other signal generator provides the pixel row scanning.

Description

INTERLEAVED DISPLAY SELECTION SCANNER

This invention was made with Government support under Contract No. F33615-88-C-1825. The Government has certain rights in the invention.

Field of the Invention The invention relates to display device and more particularly to arrangements for scanning the pixels of the display.

Background of the Invention A display device such as a liquid crystal display (LCD) generally comprises a set of active picture elements or pixels arranged in an orthogonal array of rows and columns. The pixels are scanned row by row and the individual pixels of the row being scanned are charged to voltages corresponding to the brightness to be displayed. Color television and other high quality displays typically include 1440 columns and there may be 800 rows. The rows are selected in sequence at a fixed rate.

One known arrangement for sequentially scanning the rows of an LCD employs a multistage, e.g., a 800 stage shift register, clocked at the display rate. The output of each shift register stage provides a select signal to the select line of one row of pixels. A single pulse is applied to the shift register input so that the rows are selected in sequence as the pulse is transferred from one stage to the next. The select scanner shift register as well as other circuits associated with the LCD may employ thin film elements deposited on the same substrate or wafer as the display pixels. As is well known in the art, the characteristics of thin film elements which are distributed over a large display area are more difficult to control than corresponding bulk type devices. Any defect in the select scanner shift register renders the display inoperative. Consequently, the probability of a single defect in an 800 stage thin film transistor shift register of an LCD display adversely affects the display wafer yield.

Another known display scanner arrangement employs redundancy to improve yield. A pair of 800 stage shift registers are deposited on the display substrate. Each stage of one shift register has its output connected to one end of a pixel row. The other shift register has its corresponding stage output connected to the other end of same pixel row. Both shift registers supply row select signals. In the event that one shift register is defective, it is disabled. The other shift register still provides the needed row select signals. It is necessary to have two defects in the display scan arrangement to render the wafer useless. Display yield is thereby improved through the addition of an alternative shift register. The improvement, however, still requires that one of the 800 stage shift registers be defect free.

It is desirable to significantly increase the display yield of an LCD without significantly increasing the complexity of the select scanner shift register which forms a portion thereof.

Summary of the Invention The invention is directed to display circuit that scans a rectangular array of pixels arranged in a plurality of row groups. A plurality of sequential row selection signal generators are coupled to the pixel row groups. Each sequential signal generator is coupled to a different pixel row group.

In accordance with one aspect of the invention, the plurality of pixel row groups are interleaved to provide an interlaced display. In accordance with another aspect of the invention, the pixel rows are divided into at least first and second sets. A row line having first and second ends is coupled to each pixel row. One signal generator coupled to the first ends of the row lines of the first set sequentially selects the row lines of the first set and another signal generator coupled to the second ends of the row lines of the first set sequentially selects the rows of the first set. In the event that one signal generator is defective, it is disconnected from the first set of pixel row lines.

In accordance with yet another aspect of the invention, the pixel rows are divided into at least first and second sets. A row line having first and second ends is coupled to each pixel row. One signal generator coupled to the first ends of the row lines of the second set of pixel rows sequentially selects the row lines of the second set and another signal generator coupled to the second ends of the row lines of the second set of pixel rows sequentially selects the row lines of the second set. In the event that one signal generator is defective, it is disconnected from the second set of pixel row lines.

Viewed from one aspect the invention is directed to a display circuit comprising ah array of pixels on a substrate arranged in rows and means on the substrate for scanning the pixel rows of the array. The pixel rows are divided into a plurality of groups and the rows of at least one pixel row group are interleaved with the rows of at least one other pixel row group. The scanning means comprises a plurality of means each for generating a sequence of row selection signals for a predetermined one of the groups of pixel rows, and means for coupling each sequential row selection signal generating means to the rows of the predetermined pixel group.

The invention will be better understood from the following more detailed description taken with the accompanying drawings and claims.

Brief Description of the Drawing FIG. 1 is a schematic and block diagram of a prior art display scanner arrangement;

FIG. 2 is a schematic and block diagram of another prior art display scanner arrangement using redundancy;

FIG. 3 is a schematic and block diagram of a display scanner arrangement in accordance with the present invention; and

FIG. 4 is a schematic and block diagram illustrates of the interconnection blocks employed in the display scanner arrangement of FIG. 3.

Detailed Description Referring now to FIG. 1, there is shown a schematic and block diagram of a prior art display scanner arrangement 100. Display scanner arrangement 100 comprises a scan signal generator 101, a clock terminal 130, a shift register 105 and a pixel display 108 (shown within a dashed line rectangle). The shift register 105 comprises shift register stages 105-1 through 105-N. Pixel display 108 comprises row lines 110-1 through 110- N, column lines 115-1 through 115-M, n-channel field effect transistors 120-11 through 120-NM and pixel capacitive elements 125-11 through 125-NM. The transistors are typically metal- oxide-semiconductor (MOS) field effect transistors (FETs) which may be denoted as MOSFETS. In an illustrative embodiment the transistors are thin film transistors.

In display scanner arrangement 100, the output of scan signal generator 101 is coupled to the input of stage 105-1 in shift register 105 and to a node 132. A clock terminal 130 is coupled to a clock input of shift register 105 and therefrom to the clock inputs of stages 105-1 through 105-N. One output of shift register stage 105-1 is coupled to the input of shift register stage 105-2. The other output of shift register 105-1 is coupled to row line 110-1. One output of shift register stage 105-2 is coupled through intermediate shift register stages 105-3 through 105-n-l (not shown) to the input of shift register stage 105-n. The other output of shift register stage 105-2 is coupled to row line 110-2. One output of shift register stage 105-n is coupled through intermediate stages 105-n+l through 105-N-l (not shown) to the input of shift register stage 105-N. The other output of shift register stage 105-n is coupled to row line 110-n and the output of shift register stage 105-N is coupled to row line 110-N.

In pixel display 108, row line 110-1 is coupled to the gate electrodes of transistors 120-11 through 120-1M. Row line 110-2 is coupled to the gate electrodes of transistors 120-21 through 120-2M. Row line 110-n is coupled to the gate electrodes of transistors 120-nl through 120-nM. Row line 110-N is coupled to the gate electrodes of transistors 120-N1 through 120-NM. Column line 115-1 is coupled to the drain electrodes of transistors 120-11 through 120-N1. Column line 115-2 is coupled to the drain electrodes of transistors 120-12 through 120-N2. Column line 115-M is coupled to the drain electrodes of transistors 120- 1M through 120-NM. One end of pixel capacitive elements 125- 11 through 125-NM are coupled to the source electrodes of transistors 120-11 through 120-NM, respectively. The other ends of pixel capacitive elements 120-11 through 120-NM are connected to ground potential. In operation, scan generator 101 produces a scan pulse SP at the start of every frame to be displayed on the rectangular array of pixel capacitive elements 120-11 through 120-NM. A line clock signal LCL at the beginning of each line scan in the frame is supplied to each stage 105-1 through 105-N as is well known in the art. Scan pulse SP is coupled to the input of shift register 105- 1 which is set to a high voltage level, i.e. a logical one, in response to the SP pulse and line clock signal LCL applied to terminal 130. The logical one in shift register stage 105-1 is coupled to the gate electrodes of transistors 120-11 through 120-1M through row line 110-1 for the duration of the line scan and transistors 120-11 through 120-1M are enabled (turned on). Pixel brightness signals are applied to pixel capacitive elements 125-11 through 125-1M through column lines 115-1 through 115-M and transistors 120- 11 through 120-1M, respectively, and the pixel capacitance elements are charged in accordance with the pixel brightness signals. U. S. Patent 4,742,346 (issued to Glynn G. Gillette et al on May 3, 1988) describes one arrangement for applying brightness signals to column lines 115-1 through 115-M. The next line clock signal LCL resets shift register stage 105-

1 and sets shift register stage 105-2. As a result, a low voltage level signal, i.e. logical zero, is coupled to row line 110-1 to disable transistors 110-1 through 110-M and a logical one signal is coupled to the gate electrodes of transistors 110-21 through 110- 2M from shift register stage 105-2 through line 110-2. Subsequent line clock signals sequentially set the successive stages of shift register 105 so that the rows of pixel capacitive elements are sequentially selected and charged in accordance with display information from column lines 115-1 through 115-M. After the pixel capacitive elements 125-N1 through 125-NM have been charged in response to the setting of shift register stage 105- N, scan generator 101 produces another scan pulse SP to initiate the sequential scan of row lines 110-1 through 110-N for the next frame. In a typical LCD display, there may be 800 pixel rows. A single defect in 800 stage shift register 105 renders the display inoperative.

Display wafer yield may, as is well known in the art, be improved by using redundancy. One known redundancy arrangement that uses a pair of shift registers for display scanning is shown in FIG. 2.

Referring now to FIG. 2, there is shown a prior art display scan circuit 200. Display scan circuit 200 comprises scan signal generator 201, clock terminal 230 , shift registers 205 and 207, and pixel display 208. Shift register 205 comprises shift register stages 205-1 through 205 -N. Shift register 207 comprises shift register stages 207-1 through 207-N. Pixel display 208 comprises row lines 210-1 through 210-N, column lines 215-1 through 215- M, n-channel field effect transistors 220-11 through 220-NM and pixel capacitive elements 225-11 through 225-NM. The transistors are typically metal-oxide-semiconductor (MOS) field effect transistors (FETs) which may be denoted as MOSFETS. In an illustrative embodiment the transistors are thin film transistors. In display scanner arrangement 200, an output of scan signal generator 201 is coupled to the input of stage 205-1 in shift register 205, to the input of stage 207-1 in shift register 207 and to a node 235. Clock terminal 230 is coupled to the clock inputs of stages 205-1 through 205-N and to the clock inputs of stages 207- 1 through 207 -N. One output of shift register stage 205-1 is coupled to the input of shift register stage 205-2. The other output of shift register 205-1 is coupled to row line 210-1. One output of shift register stage 205-2 is coupled through intermediate shift register stages 205-3 through 205-n-l (not shown) to the input of shift register stage 205-n. The other output of shift register stage 205-2 is coupled to row line 210-2. One output of shift register stage 205-n is coupled through intermediate stages 205-n+l through 205-N-l (not shown) to the input of shift register stage 205-N. The other output of shift register stage 205-n is coupled to row line 210-n and the output of shift register stage 205-N is coupled to row line 210-N. One output of shift register stage 207-1 is coupled to the input of shift register stage 207-2. The other output of shift register 207- 1 is coupled to row line 210-1. One output of shift register stage 207-2 is coupled through intermediate shift register stages 207-3 through 207-n-l (not shown) to the input of shift register stage 207-n. The other output of shift register stage 207-2 is coupled to row line 210-2. One output of shift register stage 207 -n is coupled through intermediate stages 207-n+l through 207 -N-l (not shown) to the input of shift register stage 207 -N. The other output of shift register stage 207 -n is coupled to row line 110-n and the output of shift register stage 207-N is coupled to row line 210-N.

In pixel display 208, row line 210-1 is coupled to the gate electrodes of transistors 220-11 through 220-1M. Row line 210-2 is coupled to the gate electrodes of transistors 220-21 through

220-2M. Row line 210-n is coupled to the gate electrodes of transistors 220-nl through 220-nM. Row line 210-N is coupled to the gate electrodes of transistors 220-N1 through 220-NM.

Column line 215-1 is coupled to the drain electrodes of transistors

220-11 through 220-N1. Column line 215-2 is coupled to the drain electrodes of transistors 220-12 through 220-N2. Column line 215-M is coupled to the drain electrodes of transistors 220-

1M through 220-NM. One end of pixel capacitive elements 225-

11 through 225-NM are coupled to the source electrodes of transistors 220-11 through 220-NM, respectively. The other ends of pixel capacitive elements 220-11 through 220-NM are connected to ground potential.

In operation, scan generator 201 produces a scan pulse SP at the start of every frame to be displayed on the rectangular array including pixel capacitive elements 225-11 through 225-NM. A line clock signal LCL1 at the beginning of each line scan in the frame is supplied to each stage 205-1 through 205-N as is well known in the art. Scan pulse SP is coupled to the input of shift register 205-1 which is set to a high voltage level, i.e. a logical one, in response to the SP pulse and line clock signal LCL1 applied to terminal 230. The logical one in shift register stage 205-1 is coupled to the gate electrodes of transistors 220-11 through 220- 1M through row line 210-1 for the duration of the line scan and transistors 220-11 through 220-1M are enabled. Pixel brightness signals are applied to pixel capacitive elements 225-11 through 225-1M through column lines 215-1 through 215-M and transistors 220-11 through 220-1M, respectively, and the pixel capacitance elements are charged in accordance with the pixel brightness signals. The next line clock signal LCL1 resets shift register stage 205-1 and sets shift register stage 205-2 As a result, a logical zero is coupled to row line 210-1 to disable transistors 210-1 through 210-M and a logical one signal is coupled to the gate electrodes of transistors 210-21 through 210-2M from shift register stage 205-2 through line 210-2. Subsequent line clock signals LCL1 sequentially set the successive stages of shift register 205 so that the rows of pixel capacitive elements are sequentially selected and charged in accordance with display information signals from column lines 215-1 through 215-M. After the pixel capacitive elements 225 -Nl through 225-NM have been charged in response to the setting of shift register stage 205 -N, scan generator 201 produces another scan pulse SP to initiate the sequential scan of row lines 210-1 through 210-N for the next frame.

Shift register 207 has the same number of stages as shift register 205. Shift register 207 operates in substantially the same manner as shift register 205 and in iso-synchronism shift register 205. The line clock signal LCL1 at the beginning of each line scan in the frame is supplied to each stage 207-1 through 207 -N as is well known in the art. Scan pulse SP is coupled to the input of shift register 207-1 which is set to a logical one in response to the SP pulse and line clock signal LCL1 applied to terminal 230-2. The logical one in shift register stage 207-1 is coupled to the gate electrodes of transistors 220-11 through 220-1M through row line 210-1 for the duration of the line scan. Transistors 220-11 through 220-1M are enabled by the logical one from shift register stage 205-1 or 207-1 or both. Pixel brightness signals are applied to pixel capacitive elements 227-11 through 227-1M through column lines 215-1 through 215-M and transistors 220-11 through 220- 1M, respectively, and the pixel capacitance elements are charged in accordance with the pixel brightness signals.

The next line clock signal LCL1 resets shift register stage 207-1 and sets shift register stage 207-2 As a result, a low voltage level signal (i.e., logical zero) is coupled to row line 210-1 to disable transistors 210-11 through 210-1M. A logical one signal is coupled to the gate electrodes of transistors 210-21 through 210-2M from shift register stage 207-2 through line 210- 2 by the logical one from either shift register stage 205-2 or 207- 2 or both. Subsequent line clock signals LCLl sequentially set the successive stages of shift register 205 so that the rows of pixel capacitive elements are sequentially selected and charged in accordance with display information from column lines 215-1 through 215-M. After the pixel capacitive elements 225-N1 through 225 -NM have been charged in response to the setting of shift register stage 205-N or 207-N, scan generator 201 produces another scan pulse SP to initiate the sequential scan of row lines 210-1 through 210-N for the next frame.

As aforementioned, a single defect in 800 stage shift register 105 in FIG. 1 renders the display 108 inoperative. In the display scanner circuit 200 of FIG. 2, both shift registers 205 and 207 must have defects to render display 208 inoperative so that display wafer yield is improved. The probability of a single defect in an 800 stage shift register, however, is relatively high. In accordance with the present invention, a plurality of smaller shift registers have interleaved connections to the pixel display row lines. In this way, the number of stages in each shift register is reduced without affecting the number of pixel rows that are scanned.

Referring now to FIG. 3, there is shown a schematic and block diagram of a display scanner circuit 300 in accordance with the present invention. The display scanner circuit 300 comprises scan signal generator 301, a clock terminal 340, shift registers

305, 307, 311 and 318, connection blocks 330-1 through 330-8,

335-1 through 335-8, and 342-1 through 342-4 and pixel display

308 shown in part. Shift register 305 comprises shift register stages 305-1, 305-3, 305-5 and 305-7. Shift register 307 comprises shift register stages 307-1, 307-3, 307-5 and 307-7.

Shift register 311 comprises shift register stages 311-2, 311-4,

311-6 and 311-8. Shift register 318 comprises shift register stages 318-2, 318-4, 318-6 and 318-8. Pixel display 308 comprises row lines 310-1 through 310-8, column lines 315-1 through 315-M, n-channel field effect transistors 320-11 through

320-8M and pixel capacitive elements 325-11 through 325-8M.

The transistors are typically metal-oxide-semiconductor (MOS) field effect transistors (FETs) which may be denoted as MOSFETS. In an illustrative embodiment the transistors are thin film transistors.

In display scanner arrangement 300, an output of scan signal generator 301 is coupled to an input of stage 305-1 in shift register 305 through connection block 342-1 and to an input of stage 307-1 in shift register 307 through connection block 342-4. Clock terminal 340 is coupled to clock inputs of stages 305-1, 305- 3, 305-5 and 305-7 of shift register 305. A first output of shift register stage 305-1 is coupled to the input of shift register stage 305-3. A second output of shift register 305-1 is coupled to row line 310-1 through connection block 330-1. A first output of shift register stage 305-3 is coupled to the input of shift register stage 305-5. A second output of shift register stage 305-3 is coupled to row line 310-3 through connection block 330-3. A first output of shift register stage 305-5 is coupled to an input of shift register stage 305-7. A second output of shift register stage 305-5 is coupled to row line 310-5 through connection block 330-5. An output of shift register stage 305-7 is coupled to row line 310-7 through connection block 330-7. An output of scan signal generator 301 is coupled to an input of stage 311-2 in shift register 311 through connection block 342-2 and to an input of stage 318-2 in shift register 318. The clock terminal 340 is coupled to the clock input of shift register 311 and therefrom to the clock inputs of stages 311-2, 311-4, 311-6 and 311-8. A first output of shift register stage 311-2 is coupled to the input of shift register stage 311-4. A second output of shift register 311-2 is coupled to row line 310-2 through connection block 330-2. A first output of shift register stage 311-4 is coupled to an input of the shift register stage 311- 6. A second output of shift register stage 311-4 is coupled to row line 310-4 through connection block 330-4. A first output of shift register stage 311-6 is coupled to an input of shift register stage 311-8. A second output of shift register stage 311-6 is coupled to row line 310-6 through connection block 330-6 and an output of shift register stage 311-8 is coupled to row line 310-8 through connection block 330-8.

The clock terminal 340 is coupled to the clock input of shift register 307 and therefrom to the clock inputs of stages 307-1, 307-3, 307-5 and 307-7. A first output of shift register stage 307-1 is coupled to the input of shift register stage 307-3. A second output of shift register 307-1 is coupled to row line 310-1 through connection block 335-1. A first output of shift register stage 307-3 is coupled to an input of the shift register stage 307- 5. A second output of shift register stage 307-3 is coupled to row line 310-3 through connection block 335-3. A first output of shift register stage 307-5 is coupled to the input of shift register stage 307-7. A second output of shift register stage 307-5 is coupled to row line 310-5 through connection block 335-5. An output of shift register stage 307-7 is coupled to row line 310-7 through connection block 335-7.

The clock terminal 340 is coupled to clock inputs of stages

318-2, 318-4, 318-6 and 318-8 of the shift register 318. A first output of shift register stage 318-2 is coupled to the input of shift register stage 318-4. A second output of shift register 318-2 is coupled to row line 310-2 through connection block 335-2. A first output of shift register stage 318-4 is coupled to the input of shift register stage 318-6. A second output of shift register stage 318- 4 is coupled to row line 310-4 through connection block 335-4. A first output of shift register stage 318-6 is coupled to the input of shift register stage 318-8. A second output of shift register stage

318-6 is coupled to row line 310-6 through connection block 335-

6 and the output of shift register stage 318-8 is coupled to row line 310-8 through connection block 335-8.

In pixel display 308, row line 310-1 is coupled to the gate electrodes of transistors 320-11 through 320-1M. Row line 310-2 is coupled to the gate electrodes of transistors 320-21 through 320-2M. Row line 310-3 is coupled to the gate electrodes of transistors 320-31 through 320-3M. Row line 310-4 is coupled to the gate electrodes of transistors 320-41 through 320-4M. Row line 310-5 is coupled to the gate electrodes of transistors 320-51 through 320-5M. Row line 310-6 is coupled to the gate electrodes of transistors 320-61 through 320-6M. Row line 310-7 is coupled to the gate electrodes of transistors- 320-71 through 320-7M. Row line 310-8 is coupled to the gate electrodes of transistors 320-81 through 320-8M. Column line 315-1 is coupled to the drain electrodes of transistors 320-11 through 320-81. Column line 315-2 is coupled to the drain electrodes of transistors 320-12 through 320-82. Column line 315-M is coupled to the drain electrodes of transistors 320-1M through 320-8M. Pixel capacitive elements 325-11 through 325-8M are coupled between the source electrodes of transistors 320-11 through 320-8M, respectively, and ground potential.

Each shift register in display scanner circuit 300 supplies scan select signals to a prescribed set of row lines. The stages of shift register 305 are coupled to the left side of the odd row lines 310-1, 310-3, 310-5, and 310-7 while the stages of shift register 311 are coupled to the left side of the even row lines 310-2, 310- 4, 310-6, and 310-8. The stages of shift register 307 are coupled to the right side of the odd row lines 310-1, 310-3, 310-5, and 310-7 and the stages of shift register 318 are coupled to the right side of the even row lines 310-2, 310-4, 310-6, and 310-8. The number of stages in each shift register is thereby reduced. If, for example, there are 800 stages in each shift register 205 and 207 of the display scanner 200 in FIG. 2, each shift register of display scanner 330 of FIG. 3 requires only 400 stages. In the event of a failure of shift register 305 or 307, the other shift register may be substituted. Similarly, if there is a failure of shift register 311 or 318, the other shift register may be substituted. Since the probability of a single defect is lower for a 400 stage shift register than for an 800 stage shift register, the display wafer yield is further improved by the display scanner arrangement of FIG. 3.

Display scanner 300 operates to provide an interleaved scan of the pixel rows in display 308 in which each frame is divided into first and second fields. In each field, the row lines of pixel display 308 are scanned in a sequence of scan line. In a preferred arrangement, pairs of rows are selected in each field scan. During the first field scan, rows 310-1 and 310-2 are selected in the first scan line. Row lines 310-3 and 310-4 are selected in the second scan line. Rows 310-5 and 310-6 are selected in the third scan line and row lines 310-7 and 310-8 are selected in the fourth line scan. Successive pairs of row lines (not shown) are then selected in the succeeding scan lines of the first field. In the second field scan, row 310-1 is selected in the first scan line. Rows 310-2 and 310-3 are selected in the second scan line. Row lines 310-4 and 310-5 are selected in the third scan line. Row lines 310-6 and 310-7 are selected in the fourth scan line and rows 310-8 and 310-9 (not shown) are selected in the fifth scan line. Successive pairs of rows (not shown) are then selected in the succeeding scan lines of the second field. In this way, an interlaced scan, such as employed in television displays, is obtained.

At the start of the first field, scan generator 301 produces scan pulses SP11 and SP12. Scan pulse SP11 is coupled to the input of shift register stage 305-1 through connection block 342-1 and to the input of shift register stage 307-1 through connection block 342-4. Scan pulse SP12 is coupled to the input of shift register stage 311-2 through connection block 342-2 and to the input of shift register stage 318-2 through connection block 342- 3. A line clock signal LCL2 is applied to shift registers 305, 307, 311 and 318 at the beginning of each scan line. Shift register stages 305-1, 307-1 311-2 and 318-2 are set to their logical one states in response to the scan pulses applied to their inputs and the line clock signal at their clock inputs. Transistors 320-11 through 320-1M are enabled by the logical one signal at their gate electrodes coupled from shift register stage 305-1 through connection block 330-1 and the logical one signal coupled from shift register 307-1 through connection block 335-1. Transistors 320-21 through 320-2M are enabled by the logical one signal at their gate electrodes coupled from shift register stage 311-2 through connection block 330-2 and the logical one signal coupled from shift register 318-2 through connection block 335-2.

The next line clock signal LCL2 initiates the second scan line by resetting shift register stages 305-1, 307-1 311-2 and 318-2 to their logical zero states and setting shift register stages 305-3, 307-3, 311-4 and 318-4 to their logical one states. Transistors 320-31 through 320-3M are enabled by the logical one signal at their gate electrodes coupled from shift register stage 305-3 through connection block 330-3 and the logical one signal coupled from shift register stage 307-3 through connection block 335-3. Transistors 320-41 through 320-4M are enabled by the logical one signal at their gate electrodes coupled from shift register stage 311-4 through connection block 330-4 and the logical one signal coupled from shift register stage 318-4 through connection block 335-4.

At the beginning of the third scan line, the next line clock signal LCL2 resets shift register stages 305-3, 307-3, 311-4 and 318-4 to their logical zero states and sets shift register stages 305-5, 307-5, 311-6 and 318-6 to their logical one states. Transistors 320-51 through 320-5M are enabled by the logical one signal at their gate electrodes coupled from shift register stage 305-5 through connection block 330-5 and the logical one signal coupled from shift register stage 307-5 through connection block 335-5. Transistors 320-61 through 320-6M are enabled by the logical one signal at their gate electrodes coupled from shift register stage 311-6 through connection block 330-6 and the logical one signal coupled from shift register stage 318-6 through connection block 335-6.

In the fourth scan line, the next line clock signal LCL2 resets shift register stages 305-5, 307-5, 311-6 and 318-6 to their logical zero states and sets shift register stages 305-7, 307-7, 311- 8 and 318-8 to their logical one states. Transistors 320-71 through 320-7M are enabled by the logical one signal at their gate electrodes coupled from shift register stage 305-7 through connection block 330-7 and the logical one signal coupled from shift register stage 307-7 through connection block 335-7. Transistors 320-81 through 320-8M are enabled by the logical one signal at their gate electrodes coupled from shift register stage 311-8 through connection block 330-8 and the logical one signal coupled from shift register stage 318-8 through connection block 335-8. The remaining row lines 310-9 through 310-N (not shown) of display 308 are selected in pairs in successive scan lines substantially as described with respect to the first through fourth scan lines of the first field.

After the last scan line of the first field in which row lines 310-N-l and 310-N are selected, the first scan line of the second field is initiated by scan pulse SC11 coupled from scan pulse generator 301 to the input of stage 305-1 of shift register 305 and to the input of stage 307-1 of shift register 307. Upon the occurrence of the next scan clock pulse LCL2, shift register stages 305-1 and 307-1 are set to the logical one states. Transistors 320-11 through 320-1M on row line 310-1 are enabled by the logical one signal at their gate electrodes coupled from shift register stage 305-1 through connection block 330-1 and the logical one signal coupled from shift register 307-1 through connection block 335-1.

When the first scan line selection terminates, scan pulse generator 301 applies a scan pulse SC12 to the input of stage 311-

2 of shift register 311 and to the input of stage 318-2 of shift register 318. Shift register stages 311-2, 318-2, 305-3 and 307-3 are then are set to their logical one states and shift register stages

305-1 and 307-1 are reset by the next line clock signal LCL2 which initiates the second scan line selection. Transistors 320-21 through 320-2M are enabled by the logical one signal at their gate electrodes coupled from shift register stage 311-2 through connection block 330-2 and the logical one coupled from shift register 318-2 through connection block 335-2. Transistors 320-

31 through 320-3M are enabled by the logical one signal at their gate electrodes coupled from shift register stage 305-3 through connection block 330-2 and the logical one signal coupled from shift register 307-3 through connection block 335-3.

In the third scan line selection, shift register stages 311-2, 318-2, 305-3 and 307-3 are reset and shift register stages 311-4, 318-4, 305-5 and 307-5 are set by the next line clock signal LCL2. As a result, transistors 320-41 through 320-4M are enabled by the logical one signal at their gate electrodes coupled from shift register stage 311-4 through connection block 330-4 and the logical one coupled from shift register 318-4 through connection block 335-4. Transistors 320-51 through 320-5M are enabled by the logical one signal at their gate electrodes coupled from shift register stage 305-5 through connection block 330-5 and the logical one signal coupled from shift register 307-5 through connection block 335-5.

The fourth line scan is started by the next line clock signal LCL2 which resets shift register stages 311-4, 318-4, 305-5 and 307-5 and sets shift register stages 311-6, 318-6, 305-7 and 307- 7. Transistors 320-61 through 320-6M are then enabled by the logical one signal at their gate electrodes coupled from shift register stage 311-6 through connection block 330-6 and the logical one signal coupled from shift register 318-6 through connection block 335-6. Transistors 320-71 through 320-7M are also enabled by the logical one signal at their gate electrodes coupled from shift register stage 305-7 through connection block 330-7 and the logical one signal coupled from shift register 307-7 through connection block 335-7. When the fourth scan line selection terminates, shift register stages 311-6, 318-6, 305-7 and 307-7 are reset and shift register stages 311-8, 318-8, 305-9 (not shown) and 307-9 (not shown) are set by the next line clock signal to start the fifth scan line selection. Transistors 320-81 through 320-8M which have their gate electrodes coupled to row line 310-8 receive a logical one from shift register stage 308-8 through connection block 330-8 and from shift register stage 318- 8 through connection block 335-8. The line scan selection continues through the remaining pixel rows (not shown) of display 308 until the termination of the Nth scan line selection in which the Nth row line 310-N is selected. One of the other well known types of scan line selection may also be used. For example, the odd rows of display 308 (e.g., 310-1, 310-3, 310-5, 310-7) may be sequentially selected through the successive enabling of the stages of shift registers 305 and 307 during the first field scan. Then, the even rows of display 308 (e.g., 310-2, 310-4, 310-6, 310-8) may be sequentially selected in the second field scan of the frame. Referring to FIG. 4, there is shown a schematic diagram of an embodiment 400 of a circuit that may be used as an connection block, e.g. 330-1, in FIG. 3. The connection block embodiment 400 comprises input terminal 401, a transmission gate 410, transmission gate control terminals 405 and 407, a laser link 420 and an output terminal 425. The input terminal 401 is connected to a signal input (a first input/output) of transmission gate 410. A signal output terminal (a second input/output terminal) of transmission gate 410 is coupled to one end of laser link 420 and to a terminal 402. The other end of laser link 420 is coupled to the output terminal 425. Control terminal 405 is connected to the direct clock input of transmission gate 410 and control terminal 407 is connected to the complement clock input of transmission gate 410. In operation, transmission gate 400 is normally closed (a short or low impedance) by a logical one applied to control terminal 405 and a logical zero applied to control terminal 407. Laser link 420 normally provides a conductive path between the output (terminal 402) of transmission gate 410 and the output terminal 425.

When used as connection block 330-1, for example, input terminal 401 is coupled to A first output of shift register stage

305-1 and output terminal 425 is coupled to row line 310-1.

When shift register 305 is defect free, connection block 330-1 couples shift register stage 305-1 to row line 310-1. If shift register 305 is defective, laser link 420 is severed so that shift register stage 305-1 is disconnected from row line 310-1. Control signal MC3 is coupled to control terminals 405 and 407 so that transmission gate 410 is normally closed. Control signal MC3 can be reversed to open transmission gate 410 for test purposes. Each of connection blocks 330-1 through 330-8, 335-1 through 335-8 has a control signal coupled thereto for testing purposes and a laser link for disconnect. Similarly, connection block 342-1 through 342-4 also have control signals coupled thereto and laser links for disconnect.

Referring again to FIG. 3, when all of shift register 305, 307,

309 and 311 are defect free, the display scanner operates as previously described. In the event that shift register 305 is defective, it may be disconnected from the row lines of pixel display 308 by severing the laser links in connection blocks 330-

1, 330-3, 330-5, 330-7 and others not shown. Shift register 307 then provides the scan select signals to the odd row lines in the pixel display. If shift register 307 is defective, shift register 305 may provide the needed scan select signals to the odd rows of the pixel display. Similarly, shift register 318 provides the scan select signals to the even rows of the pixel display 308 when shift register 311 is disconnected from the even row lines and shift register 311 provides the needed scan select signals to the even row lines when shift register 318 is disconnected. Each of Shift registers 305, 307, 311 and 318 may be disconnected by means of the laser links connected between the stage outputs thereof and the row lines of pixel display 308. Alternatively, the laser link in the connection block between the scan signal generator and the shift register may be severed so that the shift register does not receive any input therefrom or power may be removed to disable the shift register.

It is to be understood that the specific embodiments described herein are intended merely to be illustrative of the spirit and scope of the invention. Modifications can readily be made by those skilled in the art consistent with the principles of this invention. For example, the number of shift registers may be further increased so that the number of stages in each shift register can be further reduced whereby the probability of defective shift registers is even further reduced.

Claims

What Is Claimed Is:

1. A display circuit comprising: an array of pixels on a substrate arranged in rows, the pixel rows being divided into a plurality of groups and the rows of at least one pixel row group being interleaved with the rows of at least one other pixel row group; and means on the substrate for scanning the pixel rows of the array comprising: a plurality of means each for generating a sequence of row selection signals for a predetermined one of the groups of pixel rows; and means for coupling each sequential row selection signal generating means to the rows of the predetermined pixel group.

2. The display circuit of claim 1 wherein the plurality of pixel row groups comprises first and second pixel row groups and the rows of the first pixel group alternate with the rows of the second pixel row group.

3. The display circuit of claim 1 wherein the means for coupling each means for generating a sequence of row selection signals to its predetermined pixel group comprises gating means for selectively connecting the means for generating a sequence of row selection signals to the predetermined pixel group to the rows of the predetermined pixel group.

4. The display circuit of claim 3 wherein the gating means comprises a transmission gate coupled between the means for generating a sequence of row selection signals and each row of the predetermined pixel group.

5. The display circuit of claim 4 wherein the gating means further comprises a laser link in series with the transmission gate between the means for generating a sequence of row selection signals and each row of the predetermined pixel group.

6. The display circuit of claim 1 wherein the means for coupling each means for generating a sequence of row selection signals to its predetermined pixel group comprises a laser link connected between the means for generating a sequence of row selection signals and each row of its predetermined pixel group.

7. The display circuit of claim 1 wherein: each means for generating a sequence of row selection signals comprises a plurality of sequential row selection signal producing means; and the means for coupling each sequential row selection signal generating means to the rows of the predetermined pixel group comprises means for coupling each of the plurality of sequential row selection signal producing means to the rows of the same predetermined pixel group.

8. The display circuit of claim 7 wherein the means for coupling each sequential row selection signal producing means to the rows of the same predetermined pixel group comprises gating means for selectively connecting the sequential row selection signal producing means to the same predetermined pixel group.

9. The circuit of claim 8 wherein the gating means comprises a transmission gate coupled between each one of the sequential row selection signal producing means and each row of the same predetermined pixel group.

10. The circuit of claim 9 wherein the gating means further comprises a laser link connected in series with the transmission between each one of the sequential row selection signal producing means and each row of the same predetermined pixel group.

11. The circuit of claim 1 wherein each means for generating a sequence of row selection signals comprises a multistage shift register, and each multistage shift register comprising a plurality of serially coupled stages; and the means for coupling each sequential row selection signal generating means to the rows of its predetermined pixel group comprises means for coupling the outputs of the serially coupled shift register stages to the rows of the predetermined pixel group.

12. A display circuit comprising: an array of pixels arranged in rows, the pixel rows being divided into at least first and second interleaved sets; and means for scanning the pixel rows of the array comprising: means for sequentially addressing the first set of the pixel rows; and means for sequentially addressing the second set of pixel rows; the first pixel row addressing means comprising: a plurality of row lines each having a first end and a second end, each row line being coupled to a different one of the first pixel rows; means coupled to the first ends of the row lines of the first set of pixel rows for sequentially selecting the rows of the first set of pixel rows; and means coupled to the second ends of the row lines of the first set of pixel rows for sequentially selecting the rows of the first set of pixel rows; and the second pixel row addressing means comprising: a plurality of row lines each having a first end and a second end, each row line being coupled to a different one of the second pixel rows; means coupled to the first end of the row lines of the second set of pixel rows for sequentially selecting the rows of the second set of pixel rows; and means coupled to the second ends of the row lines of the second set of pixel rows for sequentially selecting the rows of the second set of pixel rows.

13. The display circuit of claim 12 wherein: the means coupled to the first ends of the row lines of the first set of pixel rows comprises: first means for generating a sequence of row line select signals; and means for applying the row line select signals from the first row line select signal generating means to the first ends of the row lines of the first set of pixel rows in sequence; and the means coupled to the second ends of the row lines of the first set of pixel rows for sequentially selecting the rows of the first set of pixel rows comprises; second means for generating a sequence of row line select signals; and means for applying the row line select signals from second row line select signal generating means to the first ends of the row lines of the first set of pixel rows in sequence.

14. The display circuit of claim 12 wherein: the means coupled to the first ends of the row lines of the second set of pixel rows comprises; third means for generating a sequence of row line select signals; and means for applying the row line select signals from the third row line select signal generating means to the first ends of the row lines of the second set of pixel rows in sequence; and the means coupled to the second ends of the row lines of the second set of pixel rows for sequentially selecting the rows of the second set of pixel rows comprises: fourth means for generating a sequence of row line select signals; and means for applying the row line select signals from fourth row line select signal generating means to the second ends of the row lines of the second set of pixel rows in sequence.

15. A display circuit comprising: an array of pixels arranged in successive rows, the pixel rows being divided into first and second sets, the first set comprising odd pixel rows of the array and the second set comprising even pixel rows of the array; means for sequentially scanning the rows of the array comprising: first and second shift registers each having a plurality of successive stages; means for coupling each stage of one of the first and second shift registers to a different one of the odd pixel rows; and means for coupling each stage of the other of the first and second shift registers to a different one of the even pixel rows.

16. The display circuit of claim 15 further comprising: means for generating first and second signals; means for applying the first signal to the first shift register; means for successively shifting the first signal through the stages of the first shift register; means for applying the second signal to the second shift register; and means for successively shifting the second signal through the stages of the second shift register.

17. A display circuit comprising: an array of pixels arranged in rows, the pixel rows being divided into first and second sets, the first set comprising odd pixel rows of the array and the second set comprising even pixel rows of the array; means for sequentially scanning the rows of the first set of the pixel rows comprising: a plurality of row lines each having a first end and a second end, each row line being coupled to a different one of the first pixel rows; first shift register means comprising a plurality of stages and first means for coupling the successive stages of the first shift register means to the first ends of the successive row lines of the first set of pixel rows to sequentially select the rows of the first set of pixel rows; and second shift register means comprising a plurality of stages and second means for coupling the successive stages of the second shift register means to the second ends of the successive row lines of the first set of pixel rows to sequentially select the rows of the first set of pixel rows; and means for sequentially scanning the rows of the second set of the pixel rows comprising: a plurality of row lines each having a first end and a second end, each row line being coupled to a different one of the pixel rows of the second set; third shift register means comprising a plurality of stages and third means for coupling the successive stages of the third shift register means to the first ends of the successive row lines of the second set of pixel rows to sequentially select the rows of the second set of pixel rows; and fourth shift register means comprising a plurality of stages and fourth means for coupling the successive stages of the fourth shift register means to the second ends of the successive row lines of the second set of pixel rows to sequentially select the rows of the second set of pixel rows.

18. The display circuit of claim 17 further comprising: means for generating first and second signals; means for applying the first signal to the first and second shift register means to successively shift the first signal through the stages of the first and second shift register means; and means for applying the second signal to the third and fourth shift register means to successively shift the second signal through the stages of the third and fourth shift register means.

19. The display circuit of claim 17 wherein: the first coupling means comprises a plurality of first gating means each connected between one of the first shift register means stages and one of the first ends of the row lines of the first set of pixel rows; the second coupling means comprises a plurality of second gating means each connected between one of the second shift register means stages and one of the second ends of the row lines of the first set of pixel rows; the third coupling means comprises a plurality of third gating means each connected between one of the third shift register means stages and one of the first ends of the row lines of the first set of pixel rows; and the fourth coupling means comprises a plurality of fourth gating means each connected between one of the fourth shift register means stages and one of the second ends of the row lines of the first set of pixel rows.

20. The display circuit of claim 19 wherein: each of the first gating means comprises a transmission gate for selectively coupling one of the stages of the first shift register means to one of the first ends of the row lines of the first set pixel rows; each of the second gating means comprises a transmission gate for selectively coupling one of the stages of the second shift register means to one of the second ends of the row lines of the first set pixel rows; each of the third gating means comprises a transmission gate for selectively coupling one of the stages of the third shift register means to one of the first ends of the row lines of the second set pixel rows; and each of the fourth gating means comprises a transmission gate for selectively coupling one of the stages of the fourth shift register means to one of the second ends of the row lines of the second set pixel rows.

21. The display circuit of claim 19 wherein: each of the first gating means comprises a laser link for selectively connecting one of the stages of the first shift register means to one of the first ends of the row lines of the first set pixel rows; each of the second gating means comprises a laser link for selectively connecting one of the stages of the second shift register means to one of the second ends of the row lines of the first set pixel rows; each of the third gating means comprises a laser line for selectively connecting one of the stages of the third shift register means to one of the first ends of the row lines of the second set pixel rows; and each of the fourth gating means comprises a laser link for selectively connecting one of the stages of the fourth shift register means to one of the second ends of the row lines of the second set pixel rows.