WO1991010108A1

WO1991010108A1 - Electronic real-time time fuse

Info

Publication number: WO1991010108A1
Application number: PCT/EP1990/002255
Authority: WO
Inventors: Ulrich Steiner; Peter RÖHE; Jürgen Zimmermann
Original assignee: Dynamit Nobel Aktiengesellschaft
Priority date: 1989-12-23
Filing date: 1990-12-19
Publication date: 1991-07-11
Also published as: CS656290A3; ZA9010344B; AU6917591A; DE3942842A1

Abstract

An electronic real-time time fuse with high-precision timing, a broad spectrum of time stages and of a size comparable with that of conventional non-electric fuses, has a delay mechanism comprising a time-comparison element (6, 18, 19) in which the target time specific to the fuse can be set by means of a programmable semiconductor memory (19). In a preferred embodiment, the fuse is manufactured by low-voltage MOS technology with a PROM or an EEPROM as the semiconductor memory (19), and the fuse can also be programmed on site.

Description

Electronic real-time delay detonator

The invention is directed to an electronic detonator with a signal input stage, a control part, a delay device, a charging capacitor and an ignition means, and to the use of the detonator in an ignition system in which the detonators can be connected in series or in parallel to a control unit .

In the case of civilian blasting technology, it is crucial that individual charges are detonated in a specific, time-tight order. Studies clearly show that a very precise time delay of the individual ignitions is necessary for optimal blasting results with regard to both the shocks and the crushing of the rock.

The required high precision is achieved by an electronic control with a central triggering of a control unit and ignition-specific delays. The electrical energy for the electronics and the ignitions must be removable from the detonator itself, because the electrical connection of the detonators to the control unit could be interrupted during the time sequence of the detonations, as a result of which the detonators would fail due to lack of energy.

Batteries in detonators are undesirable, among other things, for safety reasons. The energy storage device of a detonator is usually a capacitor that has to be charged by the central control device before the ignition. As long as the capacitor is not charged, there is no energy level that could trigger an ignition.

Since the necessary current for the electronics is drawn from the capacitor during the time delay, must for a long time Delay times of the capacitor have a high storage capacity, so that enough energy remains for ignition after the delay time has expired.

A circuit of a delay detonator is described in US 4,445,435. A delay time can be preselected with five microswitches. Although this means that only a limited amount of time is possible, the diameter of such a delay detonator is more than twice as large as that of conventional detonators.

In the case of a programmable electronic detonator according to EP 0 142 509 B1, the values of the delay time are entered via a control panel. The facility is designed for one floor only. It is not possible to install such a control panel in an igniter with a diameter of less than one centimeter.

EP 0 183 933 A2 encodes the time stages by bonding a chip which is integrated on the control part with the delay device. Such a detonator can be housed in a relatively slim housing. A disadvantage is that the coding can no longer be changed after the chip has been installed.

The object of the invention is an electronic real-time delay detonator which, with the greatest possible variety of times, has the smallest possible dimensions so that it fits into a conventional detonator sleeve (outside diameter less than 10 mm); both relative, d. H. with regard to the adjustability of the ignition times to one another and absolutely, the time accuracy should be very high.

The object is achieved by a delay detonator, which is characterized in that the delay device is a Has time comparator and the target time can be predetermined by means of a programmable semiconductor memory. Further advantageous configurations are specified in the subclaims.

Preference is given to a programmable semiconductor memory (PROM) and the design of the circuits, including the memories using MOS technology, and a tuning fork quartz as frequency standard or clock generator in the timing element.

MOS technology is known for electronic circuits of detonators. In DE PS 2 104 422, metal oxide silicon field effect transistors are used as threshold switches for ignition elements. It is very particularly preferred to design the igniter according to the invention in low-voltage MOS technology, where the electronics are already operating at operating voltages around or below 2 volts. The electronic circuit has a very low energy consumption, so that longer delay times can advantageously be realized with the same capacity of the memory.

The invention also relates to the use of the detonator in an ignition system in which the detonators can be connected in series or in parallel to a control unit, from which all the detonators connected can be started by a signal sequence and then autonomously in each detonator, ie. H. only by energy consumption from the ignition capacitor's own after a ignition-specific delay time has elapsed, by which the ignition capacitor can be triggered by the discharge of the charging capacitor.

The delay detonator according to the invention ideally combines properties with a size that have never before been able to be realized in a conventional detonator housing, that is to say a cylinder of approximately 7 mm outside diameter. Igniters with delay times in the order of 1 ms to 8 000 ms can be formed, the stages tests can be in the range of 250 μs and the largest possible errors are in the range of 20 ppm. Delay detonators with this variety of times and this accuracy are hitherto unknown. The delay detonators can be operated with supply voltages around or below 2 volts. They can be combined with all known safety and control devices in the detonator.

Semiconductor memories are known in many variants from computer technology; A programmable semiconductor memory (PROM) is preferred for the detonator according to the invention. A PROM based on field effect transistors is very particularly preferred because such a memory can easily be integrated on a chip together with MOS logic.

The memory contains a single address. With a data word length of 18 bits, for example, 262 144 different delay times can be set. The area that such a memory additionally occupies on the chip area is negligible. This eliminates all switches and bonds.

In order to keep the number of programming connections to the igniter as small as possible for reasons of space, serial programming of the memory is preferred. The desired data are read in via a shift register, programmed in the memory and then preferably also read out again to ensure that the value to be programmed is actually contained in the memory.

In most cases, the delay time is set during the manufacture of the detonator and not at the manufacturer of the electronics. However, in the igniter according to the invention it is also advantageously possible for the user to enter the special delay times in the igniter To make place. All that is required is for the lines of the programming device to be led out at the igniter so that the target time can be entered into the semiconductor memory on site using a suitable programming device.

In the case of known electronic delay detonators, the time standard is determined by RC elements. According to an advantageous development of the invention, the time comparison device is assigned a tuning fork quartz as frequency standard or clock generator. This is very small, can work with low voltage and is inexpensive.

The advantages of the detonator according to the invention are particularly clear when interacting with several detonators in the event of an explosion, in which time precision and safety are the decisive criteria.

The invention is illustrated by way of example in the drawing and further explained below. Show it

1 is a block diagram of an electronic real-time delay detonator with analog and digital part,

2 shows a data protocol when programming and reading the memory,

Fig. 3 is a flowchart of the programming and reading process and

Fig. 4 is an operating diagram of the ignition process.

1 shows an embodiment of an igniter in the block diagram. The circuit consists of two main groups, an analog part 1 and a digital part 2. A limiter 3 in the analog part 1 is used for safety; it is intended to reduce overvoltages at signal input 4, so that the subsequent circuit functions is not affected. A signal decoupling 5 filters the pulses for a central control unit 6 (CPU) from the input signal and adjusts the level to the low-voltage MOS digital part 2. A rectifier 7 feeds a voltage regulator 8 and this in turn supplies a capacitor 9. The voltage regulator 8 is designed as a two-stage voltage regulator so that a no-fire energy level and an all-fire energy level can be set on the capacitor 9. To set the all-fire energy level, the controller 8 needs an unlocking signal 10 from the central control unit 6, which is only set if a corresponding unlocking code is passed to the central control unit 6 via the input 4, the limiter 3 and the signal output 5 and is recognized as correct. Otherwise, the no-fire energy level is always set on the capacitor 9. In addition, the voltage regulator 8 supplies a RESET signal 11, which produces a basic state in the digital part 2 during commissioning.

By operating a power switch 12, the charge flows out of the capacitor 9 through an ignition means 13, preferably a squib, as soon as an ignition signal 14 is set by the central control unit 6. An ignition can only take place if the all-fire energy level on the capacitor 9 has previously been set. A voltage regulator 15 regulates the fixed voltage for the low-voltage MOS digital part 2.

A quartz 16 together with a driver and divider 17 in the digital part 2 supplies a clock sequence to the central control unit 6. An up counter 18 can be started with this clock by the central control unit 6 and set to zero. The counter reading is stored in the programmable semiconductor memory 19, in which an ignition signal 14 is set by the central control unit 6 if the counter reading from the counter 18 matches this. Data is exchanged with the programmable semiconductor memory 19 via a data interface 20. Depending on the data protocol, the programmable semiconductor memory 19 can be programmed or read.

FIG. 2 shows an example of a data protocol “programming” (above) and “reading” (below) which is coordinated with the system according to FIG. 1. In connection with a clock or clock line 21, all data are clocked in via a serial data line 22 by means of an external programming device. The serial data line 22 works bidirectionally, i. H. it can both receive and send (tri-state). The signal sequence during programming and reading is shown in each of FIGS. 2a and 2b, reference numbers 21 and 22 indicating over which line in FIG. 1 the pulses run.

At the beginning of each communication, a start condition in time segment 23 (note: hereinafter - as in other cases - briefly referred to as "start condition 23", the number always standing for the respective time segment) must be fulfilled. In the exemplary embodiment described here, it is provided that a level LOW is supplied from the signals in the data line 22 in the time segment 23 and an edge from HIGH to LOW is supplied in the clock line 21. After these start signals, an identifier 24 is clocked in in the subsequent time segment. In the example shown, the identifier is 10101 as a bit sequence. One bit is clocked in with each HIGH state in the clock line 21. The next bit in the time segment 25 decides whether the memory 19 should be programmed or read. If this bit 25 - as shown in FIG. 2 a - is LOW, this means programming. If, on the other hand, it is in the HIGH state according to FIG. 2b, this is called reading.

After successful transmission of the identifier 24 and the programming or read bit 25, the data interface 20 reacts in connection with the memory 19 with a first acknowledgment bit 26 from the LOW state as confirmation of the correct function. For this purpose, the data interface 20 goes to send and the external programming device to receive. After this first acknowledgment bit 26, the data interface 20 then goes on the data line 22 in the case of programming to receive and in the case of reading to send. A counted amount of data bits 27, for example 18 bits, can then be input (programming) or clocked out (reading) via the data interface 20.

Once the counted amount of data bits has been reached in the time segment 27, the memory 19 reacts with a second acknowledgment bit 28 from the LOW state in the data line 22. With the following stop condition 29, the communication between the programming device and the data interface 20 with the memory 19 is completed. For this purpose, a level LOW is supplied in data line 22 in time segment 29 and an edge from LOW to HIGH is supplied in clock line 21.

It is possible at any time to read and check the content of the memory 19, preferably a PROM, as long as the corresponding connections are accessible in order to select incorrectly programmed detonators. The memory 19 can also be implemented as an electronically readable memory (EEPROM), e.g. to be able to adapt the programming for changed operating conditions. In this case, the stored content of the EEPROM can be changed at any time via the data line 22 and the clock line 21, as long as these lines are accessible. Examples of the organization of such EEPROMs are given in the data sheets from Eurosil, Munich, Germany, or XICOR, Milpitasch, California, USA.

The programming or reading process will be explained in more detail with the aid of the flow chart shown in FIG. 3. The data interface 20 is started by supplying a signal from the LOW state in the data line 22 (abbreviated as DATA) as the start condition 23 and in the same time period in the de Clock line 21 (abbreviated as CLOCK) a change from HIGH to LOW is made. The identifier 24, here five bits, is then clocked in via the data line 22. Provided that the bit 25 subsequently clocked in is of the LOW state, the data interface 20 then goes on the data line 22 to program the memory 19 after receiving the correct transmission of the identifier 24 by the acknowledgment bit 26 from the state LOW has confirmed over the data line 22.

After the programming process has ended, the data interface 20 reacts with the further acknowledgment bit 28 from the LOW state as confirmation of the correct receipt of the data. The function of the data interface 20 is then ended by clocking a stop bit 29 from the LOW state via the data line 22 and changing from LOW to HIGH in the clock line 21 in the same time period.

If, after programming, additional reading of the memory content is desired, after the above-described input of the identifier 24, a bit 25 of the HIGH state is clocked in, so that the data interface 20 goes to transmit in order to read the content of the memory 19 . The further sequence corresponds to that during programming.

4, curve 30 shows the typical voltage curve at input 4 of an igniter according to the invention. There is first a DC voltage, ie in time segment 31, the polarity being arbitrary. Curve 37 shows the counter readings of counter 18 as a function of time. Curve 32 shows the time profile of the voltage across capacitor 9. Dashed line 33 represents a no-fire level of ignition means 13. In principle, when the igniter is started up, voltage of capacitor 9 is removed from voltage regulator 8 during time periods 31 and 34 set to a voltage below the no-fire level. Only after successful securing on line 4 (see FIG. 1) in time segment 34 is capacitor 9 charged to the full voltage, identified by line 35. The unlocking signal on line 4 consists of four voltage changes of a defined time sequence. The signal decoupling 5 is designed such that a change in current or voltage when the polarity changes sign is evaluated as a pulse in time segment 34. The circuit is constructed in such a way that unlocking is successful if the first and second voltage changes take place within a certain time t ^ and the time between the second and fourth changes is just as long. The time t ^ is evaluated via the counters 36 of the counter 18, as will be explained in more detail below.

In the time period 38, the capacitor 9 is charged to the full voltage 35. The charging process of the capacitor 9 is triggered after successful unlocking with the logic signal 10 on the voltage regulator 8 (see FIG. 1).

The ignition command, which here consists of four successive voltage changes, takes place in time segment 39. After the fourth change at time 40, counter 18 is started. It counts up until the preprogrammed counter state 41 of the memory 19 is reached. At this point in time 42, the capacitor 9, triggered by the ignition signal 14, is short-circuited via the ignition means 13. The voltage 32 at the capacitor 9 drops to zero.

In the voltage curve 30 at the input 4 of the analog part 1 of the igniter, after the four voltage changes of the ignition command during the period 39, two further voltage changes in the period 43 are shown. They serve as security in the event that the signal transmission is disturbed in a voltage change. The digital part 2 is designed so that all detonators start their counters 18 together with the receipt of the ignition command. The time-delayed ignition then takes place individually in accordance with the preprogrammed counter reading in the memory 19 of the respective detonator. The function of the detonator according to the invention is explained in more detail below: The central control unit 6 embodies all the logic circuit parts which are necessary for controlling the memory 19 and the counter 18. The central control unit 6 is able, according to the control commands, via the signal input 4, the limiter 3 and the signal decoupling 5 to set the counter 18 to zero (RESET), to start it to count up, to stop it and to evaluate its counter reading. These digital functions are explained in more detail with reference to FIGS. 1 and 4. In period 31, the igniter is put into operation by applying a voltage 30 to the signal input 4. The counter 18 is started by the central control unit 6 during the first voltage change, ie during the transition from the time segment 31 to the time segment 34. During the second voltage change in the time segment 34, ie after the time t ^, the counter 18 is stopped. Its counter reading 36 is compared and evaluated with a counter reading stored in the hardware. Then the counter 18 is started again immediately. After the fourth voltage change, the central control unit 6 stops the counter 18 and evaluates its counter reading 36 again. If both counter readings 36 are within a predefined tolerance compared to the stored counter reading, the unlocking is released by the unlocking line 10 changing its logical state, that is to say setting an unlocking signal. The meter readings relevant for the unlocking are stored in the hardware; they are not part of the memory of the memory 19. In the time segment 38, the capacitor 9, ie the ignition and operating capacitor, is charged to its full voltage. After another four voltage changes in time period 39, counter 18 is restarted at time 40. Now the central control unit 6 constantly compares the counter reading of the counter 18 with the counter reading 41 stored in the memory 19. If the counter readings are identical, the ignition is triggered.

Claims

Expectations:

1. Electronic detonator with a signal input stage (3, 4, 5), a control part (6), a delay device, a charging capacitor (9) and an ignition means (13), characterized in that the delay device has a time comparison element (6, 18, 19) and the target time can be predefined by means of a programmable semiconductor memory (19).

2. detonator according to claim 1, characterized in that the circuits including the memory are carried out in MOS technology.

3. detonator according to claim 2, characterized in that the circuits including the memory are designed in low-voltage MOS technology.

4. detonator according to one of claims 1 to 3, characterized in that the semiconductor memory (19) is designed as a one-time programmable memory (PROM).

5. detonator according to claim 4, characterized in that the one-time programmable memory (19) via a data (22) and a clock line (21) is programmable.

6. detonator according to one of claims 1 to 5, characterized in that the memory (19) is integrated in a chip which contains the other control functions.

7. detonator according to one of claims 1 to 6, characterized in that an externally accessible signal input (21, 22) is provided on the igniter housing, via which the semiconductor memory (19) is programmable on site.

8. detonator according to one of claims 1 to 7, characterized in that the clock of the digital part (2) is a tuning fork quartz (16).

9. Use of detonators according to one or more of claims 1 to 8 in an ignition system in which the detonators can be connected in series or in parallel to a control unit from which all the detonators connected can be started by a signal sequence and then automatically in each detonator , d. H. only by energy consumption from the igniter's own charging capacitor after a ignition-specific delay time has elapsed, by the discharge of the charging capacitor the ignition means can be triggered.