WO1991007778A1 - Bipolar junction transistors - Google Patents

Bipolar junction transistors Download PDF

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Publication number
WO1991007778A1
WO1991007778A1 PCT/GB1990/001779 GB9001779W WO9107778A1 WO 1991007778 A1 WO1991007778 A1 WO 1991007778A1 GB 9001779 W GB9001779 W GB 9001779W WO 9107778 A1 WO9107778 A1 WO 9107778A1
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WO
WIPO (PCT)
Prior art keywords
emitter
lightly doped
region
doped base
transistor
Prior art date
Application number
PCT/GB1990/001779
Other languages
French (fr)
Inventor
Sion Christopher Quinlan
Original Assignee
Lsi Logic Europe Plc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lsi Logic Europe Plc filed Critical Lsi Logic Europe Plc
Publication of WO1991007778A1 publication Critical patent/WO1991007778A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors

Definitions

  • This invention relates generally to bipolar junction transistors and to methods of manufacture thereof, and is particularly concerned with improving the emitter-base performance of self-aligned bipolar junction transistors.
  • the spacing X of the heavily doped base contact from the emitter region is a crucial parameter in the operation of the device. An understanding of the importance of this spacing X can be most readily understood if one examines the performance of the device in the limiting case where the distance X is reduced to zero.
  • any junction formed by diffusion of a dopant into a plane area, will produce a surface where this diffused junction meets the background doping of the semiconductor, where this surface consists of two distinct portions.
  • the first portion is a flat interface called the "area term” and the second portion is a curved interface known as the "periphery term" or "sidewall term". Because of this, one can consider the operation of the bipolar junction transistor as the combination of two devices, one consisting of the area term of the emitter-base junction interacting with the lightly doped base region, and the other consisting of the side wall and the region between this and the the side wall and the region between this and the heavily doped base contact.
  • the periphery transistor Since current gain is related to the ratio of the doping between the emitter diffusion and the doping in the base region which is in contact with the emitter diffusion, then the periphery transistor would have a reduced current gain as compared to the area transistor, due to the lower ratio between the emitter periphery doping and the highly doped base contact diffusion.
  • the periphery of a junction can dominate the characteristics of the device. For example, for a (2 ⁇ m) ⁇ device, the area is
  • the periphery is 8 ⁇ m. This represents a ratio of periphery to area of 2 to 1.
  • the ratio of periphery to area determines the operation of the transistor. High ratios indicate transistor behaviour which is dominated by the periphery transistor (low current gain and high Early Voltage) and low ratios indicate operation dominated by the area transistor
  • the transition frequency is defined as that frequency where the small signal AC gain has become unity.
  • the main contribution to controlling the time constants associated with the transition frequency is the emitter-base capacitance.
  • the capacitance of the emitter-base can be determined from the two components of the junction in parallel. Hence, any increase in the periphery term would result in an increase in the total emitter-base capacitance and subsequently in a decrease in the transition frequency. If X is zero, then the capacitance of the system is maximised and the transition frequency is at a minimum.
  • the separation X of the periphery of the emitter from the heavily doped base contact is controlled by three distances. These are the width L ⁇ of the deposited spacer, the distance L 3 that the heavily doped base contact moves under the deposited spacer due to lateral diffusion, and the distance L5 which represents the lateral outward diffusion of the emitter beneath the spacer.
  • the width dimension L4 of the deposited spacer should be of the order of
  • a bipolar junction transistor comprising a substrate, a lightly doped base region on the substrate, a heavily doped base contact region around the lightly doped base region, and an emitter positioned above the lightly doped base region, wherein the junction between the emitter and the lightly doped base region is a planar junction.
  • the emitter has a vertical peripheral wall.
  • the periphery of the emitter and a portion of the lightly doped region are etched away to provide a peripheral step in the lightly doped region.
  • a method of manufacturing a bipolar transistor which comprises the steps of forming, on a substrate, a lightly doped base region, a heavily doped base contact region around the lightly doped base region, and an emitter positioned above the lightly doped base region, and removing a peripheral portion of the emitter thereby to create a planar junction between the emitter and the lightly doped base region.
  • said removal is effected by etching.
  • Fig. 1 is a schematic sectional view through a known bipolar junction transistor; and, Fig. 2 is a similar schematic sectional view through the bipolar jurction transistor in accordance with the invention.
  • the bipolar junction transistor which can be considered as a self-aligned mesa etch transistor, comprises a substrate 10, a lightly doped base region 12, a heavily doped base contact 14, a polysilicon emitter 16, and a spacer 18 deposited around the emitter. It differs from the conventional transistoi shown in Fig. 1 in that the silicon is etched, for example using conventional etching techniques, to a depth indicated as L
  • the etching process can be effected by using the polysilicon and silicon nitride deposited on the polysilicon (or any other material to contact the transistor emitter) as a self- aligning mask.
  • the spacer 18 is then deposited to the width and depth shown, so that it i ⁇ contiguous with the periphery of the emitter, the recess in the base region 12, and the diffusion area of the base contact, indicated at 24.
  • the depth of the etch i.e. the depth L ⁇ + Y, is such that the emitter-base junction which is now a planar junction 25, is contained within the region where the etch depth is less than the total distance 1-2, This results in the following advantages: a) the emitter-base breakdown, which in the conventional structure shown in Fig.

Abstract

A bipolar junction transistor comprises a substrate (10), a lightly doped base region (12) on the substrate, a heavily doped base contact region (14) around the lightly doped base region, and an emitter (16) positioned above the lightly doped base region. By etching away the peripheral portion of the emitter (16), and desirably also a portion of the periphery of the lightly doped base region (12), one creates a planar junction (25) between emitter and base. This gives increased resistance to breakdown as compared with a curved junction and gives other benefits due to the increased separation (X' + Y) between the emitter (16) and the heavily doped base contact region (14).

Description

BIPOLAR JUNCTION TRANSISTORS
This invention relates generally to bipolar junction transistors and to methods of manufacture thereof, and is particularly concerned with improving the emitter-base performance of self-aligned bipolar junction transistors.
In the conventional self-aligned single polysilicon bipolar junction transistor, such as is shown for example in Fig. 1 of the accompanying drawings, the spacing X of the heavily doped base contact from the emitter region is a crucial parameter in the operation of the device. An understanding of the importance of this spacing X can be most readily understood if one examines the performance of the device in the limiting case where the distance X is reduced to zero.
If the distance X is reduced to zero, then there is a reduction in the emitter-base breakdown voltage due to the increased doping level which is present close to the emitter at the edge of the lightly doped base region.
Any junction, formed by diffusion of a dopant into a plane area, will produce a surface where this diffused junction meets the background doping of the semiconductor, where this surface consists of two distinct portions. The first portion is a flat interface called the "area term" and the second portion is a curved interface known as the "periphery term" or "sidewall term". Because of this, one can consider the operation of the bipolar junction transistor as the combination of two devices, one consisting of the area term of the emitter-base junction interacting with the lightly doped base region, and the other consisting of the side wall and the region between this and the the side wall and the region between this and the heavily doped base contact.
Since current gain is related to the ratio of the doping between the emitter diffusion and the doping in the base region which is in contact with the emitter diffusion, then the periphery transistor would have a reduced current gain as compared to the area transistor, due to the lower ratio between the emitter periphery doping and the highly doped base contact diffusion.
In small geometry processes, the periphery of a junction can dominate the characteristics of the device. For example, for a (2 μm)^device, the area is
4 μ~ τ and the periphery is 8 μm. This represents a ratio of periphery to area of 2 to 1. The ratio of periphery to area determines the operation of the transistor. High ratios indicate transistor behaviour which is dominated by the periphery transistor (low current gain and high Early Voltage) and low ratios indicate operation dominated by the area transistor
(high current gain and lower Early Voltage) . Since the difference in operation between the periphery transistor and the area transistor is so critical in determining the "scalability" of the process, the interaction between the heavily doped base contact on the one hand and the emitter periphery on the other hand is crucial.
When the spacing X is zero, the scalability of the process is reduced to a minimum because the periphery term will always dominate.
Also dependent upon the ratio of the area term and periphery term is the transition frequency fτ
The transition frequency is defined as that frequency where the small signal AC gain has become unity. In modern processes the main contribution to controlling the time constants associated with the transition frequency is the emitter-base capacitance. As with the transistor, the capacitance of the emitter-base can be determined from the two components of the junction in parallel. Hence, any increase in the periphery term would result in an increase in the total emitter-base capacitance and subsequently in a decrease in the transition frequency. If X is zero, then the capacitance of the system is maximised and the transition frequency is at a minimum.
The separation X of the periphery of the emitter from the heavily doped base contact is controlled by three distances. These are the width L^of the deposited spacer, the distance L3 that the heavily doped base contact moves under the deposited spacer due to lateral diffusion, and the distance L5 which represents the lateral outward diffusion of the emitter beneath the spacer.
It can be calculated that the width dimension L4 of the deposited spacer should be of the order of
0.35 to 0.4 μm, in order to take into account the combined effects of (1) the heavily doped base contact (0.2 to 0.3 μm) , (2) the spread of the emitter into the lightly doped base region (0.05 μm) and (3) a suitable stand-off distance between the heavily doped base contact region and the emitter diffusion (0.1 μm) . The formation of such a spacer is difficult and makes the bipolar device less compatible with MOS technology.
It is an object of the present invention to provide an improved self-aligned bipolar junction transistor which has an improved emitter-base performance as compared with the prior art device described above.
It is a further object of the present invention to provide an improved method of manufacture of self-aligned bipolar junction transistors.
In accordance with the present invention there is provided a bipolar junction transistor comprising a substrate, a lightly doped base region on the substrate, a heavily doped base contact region around the lightly doped base region, and an emitter positioned above the lightly doped base region, wherein the junction between the emitter and the lightly doped base region is a planar junction. Preferably the emitter has a vertical peripheral wall.
In a preferred embodiment, the periphery of the emitter and a portion of the lightly doped region are etched away to provide a peripheral step in the lightly doped region.
In accordance with another aspect of the present invention there is provided a method of manufacturing a bipolar transistor which comprises the steps of forming, on a substrate, a lightly doped base region, a heavily doped base contact region around the lightly doped base region, and an emitter positioned above the lightly doped base region, and removing a peripheral portion of the emitter thereby to create a planar junction between the emitter and the lightly doped base region.
Preferably, said removal is effected by etching.
In order that the invention may be fully understood, a preferred embodiment of bipolar junction transistor in accordance with the invention will now be described by way of example and with reference to the accompanying drawings, in which:
Fig. 1 is a schematic sectional view through a known bipolar junction transistor; and, Fig. 2 is a similar schematic sectional view through the bipolar jurction transistor in accordance with the invention.
As shown in Fig. 2, the bipolar junction transistor, which can be considered as a self-aligned mesa etch transistor, comprises a substrate 10, a lightly doped base region 12, a heavily doped base contact 14, a polysilicon emitter 16, and a spacer 18 deposited around the emitter. It differs from the conventional transistoi shown in Fig. 1 in that the silicon is etched, for example using conventional etching techniques, to a depth indicated as L| + Y. In other words, the periphery of the emitter is etched away and also a portion of the region 12. This results in a straight vertical side 20 for the emitter and also a rectangular cross-section step or recess 22 in the lightly doped base region 12. The etching process can be effected by using the polysilicon and silicon nitride deposited on the polysilicon (or any other material to contact the transistor emitter) as a self- aligning mask. The spacer 18 is then deposited to the width and depth shown, so that it i≤ contiguous with the periphery of the emitter, the recess in the base region 12, and the diffusion area of the base contact, indicated at 24. The depth of the etch, i.e. the depth L^ + Y, is such that the emitter-base junction which is now a planar junction 25, is contained within the region where the etch depth is less than the total distance 1-2, This results in the following advantages: a) the emitter-base breakdown, which in the conventional structure shown in Fig. 1 is adversely affected by both the curvature of the edge of the emitter and the proximity of the heavily doped base contact region, is in the mesa etch transistor now governed by the breakdown of a planar emitter-base junction 25 and the lightly doped base region,i.e. the portion 26-below the spacer 18 and the portion of depth Y. This results in increased resistance to breakdown and improved reliability. b) since the periphery term of the emitter- base junction has been removed by the etching process,the total capacitance of the emitter- base junction is reduced. This results in an increase in the transition frequency. c) since the periphery of the emitter has been removed by he etching process there will be no area-dependent gain effect. By the etching process in accordance with the invention the spacing X' between the heavily doped base
> contact region.14 and the emitter 16 has been increased as compared with the device shown in Fig. 1 by a distance equal to X* + Y-X. This results in the following advantages: a) because the heavily doped base contact region 14 is decoupled from the emitter 16, one can increase the doping in the heavily doped base contact region and the junction depth is no longer critical. The junction can move a further distance X' - X before any influence of this heavily doped base contact region will have an effect on the operation of the transistor. b) the improved "wrap-around" nature of the heavily doped base contact region will reduce the bias dependence of the base resistance which in turn will - improve the current handling capacity of the device and reduce the noise figure.
SUBSTITUTESHEET The actual method of effecting the etching according to the invention and the dimensions of the etched zone may be varied in accordance with particular required parameters for the device.

Claims

C AIMS :
1. A bipolar junction transistor comprising a substrate, a lightly doped base region on the substrate, a heavily doped base contact region around the lightly doped base region, and an emitter positioned above the lightly doped base region, wherein the junction between the emitter and the lightly doped base region is a planar junction.
2. A transistor as claimed in claim 1, wherein breakdown between the emitter and the heavily doped region is governed by breakdown of the planar junction between the emitter and the lightly doped base region and of a portion of the lightly doped region.
3. A transistor as claimed in claim 1 or 2, in which the emitter has a vertical peripheral wall.
4. A transistor as claimed in claim 3, in which the vertical peripheral wall of the emitter is continuous with a vertical edge surface of the lightly doped region.
5. A transistor as claimed in any preceding claim, which has the peripheral portion of the emitter removed by etching.
6. A transistor as claimed in any preceding claim, in which the periphery of the emitter and a portion of the lightly doped region are etched away to provide a peripheral step in the lightly doped region.
7. A transistor as claimed in any preceding claim, in which a spacer is deposited around the emitter and is contiguous with the periphery of the emitter and with the periphery of the lightly doped region.
8. A method of manufacturing a bipolar junction transistor which comprises the steps of forming, on a substrate, a lightly doped base region, a heavily doped base contact region around the lightly doped base region, and an emitter positioned above the lightly doped base region, and removing a peripheral portion of the emitter thereby to create a planar junction between the emitter and the lightly doped base region.
9. A method as claimed in claim 8, which includes removing also a portion of the lightly doped base region thereby to form a peripheral step in the lightly doped region.
10. A method as claimed in claim 8 or 9 , wherein said removal is effected by etching.
11. A method as claimed in claim 9, which includes depositing a spacer around the emitter and in contact with the periphery of the emitter and with the step in the lightly doped region.
PCT/GB1990/001779 1989-11-18 1990-11-19 Bipolar junction transistors WO1991007778A1 (en)

Applications Claiming Priority (2)

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GB898926414A GB8926414D0 (en) 1989-11-18 1989-11-18 Bipolar junction transistors
GB8926414.7 1989-11-18

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2700418A1 (en) * 1993-01-12 1994-07-13 France Telecom Electronic component capable of negative dynamic resistance and corresponding manufacturing process.
US6329675B2 (en) * 1999-08-06 2001-12-11 Cree, Inc. Self-aligned bipolar junction silicon carbide transistors
WO2002049115A1 (en) * 2000-12-11 2002-06-20 Cree, Inc. Method of fabricating a self-aligned bipolar junction transistor in silicon carbide and resulting devices
CN102664190A (en) * 2012-05-16 2012-09-12 清华大学 Embedded epitaxial external base region bipolar transistor and manufacturing method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2618733A1 (en) * 1975-04-30 1976-11-11 Sony Corp SEMICONDUCTOR COMPONENT WITH HETEROUE TRANSITION
US4195307A (en) * 1977-07-25 1980-03-25 International Business Machines Corporation Fabricating integrated circuits incorporating high-performance bipolar transistors
EP0036620A2 (en) * 1980-03-22 1981-09-30 Kabushiki Kaisha Toshiba Semiconductor device and method for fabricating the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2618733A1 (en) * 1975-04-30 1976-11-11 Sony Corp SEMICONDUCTOR COMPONENT WITH HETEROUE TRANSITION
US4195307A (en) * 1977-07-25 1980-03-25 International Business Machines Corporation Fabricating integrated circuits incorporating high-performance bipolar transistors
EP0036620A2 (en) * 1980-03-22 1981-09-30 Kabushiki Kaisha Toshiba Semiconductor device and method for fabricating the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2700418A1 (en) * 1993-01-12 1994-07-13 France Telecom Electronic component capable of negative dynamic resistance and corresponding manufacturing process.
EP0607075A1 (en) * 1993-01-12 1994-07-20 France Telecom Electronic component which can have a negative dynamic resistance and process for making the same
US5465001A (en) * 1993-01-12 1995-11-07 France Telecom Electronic component capable of negative dynamic resistance
US6329675B2 (en) * 1999-08-06 2001-12-11 Cree, Inc. Self-aligned bipolar junction silicon carbide transistors
WO2002049115A1 (en) * 2000-12-11 2002-06-20 Cree, Inc. Method of fabricating a self-aligned bipolar junction transistor in silicon carbide and resulting devices
CN102664190A (en) * 2012-05-16 2012-09-12 清华大学 Embedded epitaxial external base region bipolar transistor and manufacturing method thereof

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GB8926414D0 (en) 1990-01-10

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