WO1991006952A2

WO1991006952A2 - Offset correction apparatus

Info

Publication number: WO1991006952A2
Application number: PCT/US1990/005677
Authority: WO
Inventors: Narottam N. Patel; Robert W. Dean
Original assignee: Unisys Corporation
Priority date: 1989-10-27
Filing date: 1990-10-04
Publication date: 1991-05-16
Also published as: WO1991006952A3

Abstract

Embodiments disclose techniques and apparatus for correcting offset in a magnetic recording disk drive system without burdening drive overhead; particularly where the data heads for a stack of disks are monitored for offset according to their read-out of disk index-gap information, this read-out being stored in a special memory means and manipulated by a special related microprocessor means.

Description

OFFSET CORRECTION APPARATUS

This concerns high speed disk drive equipment and particularly the alignment of head assembly (transducers) therefor.

Background, Features:

In disk storage devices which employ rotating disks with concentric data tracks, magnetic data heads are used for reading and writing data on these tracks.

Workers in these arts are well aware of "head-offset" problems major ones for some time now. Head-offset can result from various causes; a principal cause is "carriage tilt". "Carriage tilt" is simplistically illustrated in Figs 4A and 5A, where part of a typical "Head-Disk assembly" (HDA) is shown, including a carriage 11 controllably propelled across a carriageway on a base plate 13 to reciprocate transducing head structures (data heads h, servo head S) across the faces of respective disks,D_Q, D.,, D₂ etc. (i.e. across data tracks on disks) as known in the art. The disks are understood as alike and co-rotated by associated spindle means SP.

Fig. 4A indicated carriage-tilt "away from" the spindle, while Fig 5A indicates carriage-tilt "toward" the spindle. "Carriage tilt" can be caused by such things as temperature differences between disks, distortion of the disk drive, tilt of the spindle rotational axis, changes in the spindle tilt caused by/with removable disk packs, and dirt particle beneath a carriage bearing. Upper head offset, caused by tilt, has plagued the industry for sometime, yet no one has yet appeared with an adequate solution; though many solutions have been proposed (e.g. heat treating carriage parts, baseplate and spindle; change in head conformation, reduction in HDA particles etc. )

Effects of head tilt are plotted in Fig. 4A where, assuming 32 stacked data heads h, the bottom head (h-O).is depicted as "close to center alignment", while the top head ( e.g. h-31,not shown) is displaced the farthest from center (here assume max. of about -300u"). Conversely, in Fig 5A the opposite tilt throws the top head to a +300 U" "offset" from center.

As a solution to such head - offset problems, I offer the following "Automatic Upper-head Offset Correction" scheme that, in real time, will electronically shift the stacked head array "toward center" to compensate for tilt (e.g. as schematically indicated in Fig. 4B, For Fig. 4A, and in Fig. 5B for Fig. 5A).

Thus apparatus and methods are disclosed for correcting

"upper head offset" relative to recording media (such as like rigid disks having circular concentric recording "cylinders" formed thereon. ) The associated high speed disk file is assumed to have a dedicated servo surface at the bottom of the disk stack, (e.g. see D_n, Fig. 4A) with the magnetic head arm assemblies mounted in a common, on one carriage which is moved in response to received servo command current (e.g. voice-coil actuated). Thus, the set of heads is moved linearly, by a desired cylinder-increment, along the radii of respective disks.

The carriage should be controllably moved during linear "Track

Following" mode to correct upper head offset. The "correction increment" S, -0 is assumed to be kept above a minimum, and below the servo constraint limit. This small incremental distance S,n-0 is thus defined as "Upper head offset" and will be understood as controlled and auto-corrected by a microprocessor according to this invention.

Offset voltage is to be injected into a servo amplifier for real-time correcting, without requiring any "overhead". According to a feature hereof "Tilt" will be determined based on two special "Offset Tables": a Reference Table I (x) and an Update Current Table II (x) stored in memory, where x=o, 1, 2, and 3 and so divides the magnetic surface (tracks) into four zones (tracks groups). Reference Table I(x) is intended to reflect reference amplitude data output from heads in terms of magnetic readout (voltage) from standard portion of "initialized data" along each disk track, (called "gapl-gap2" readout as explained below). In like fashion Table II(x) likewise reflects the real time amplitude data of the said heads any variance between the Tables indicating "Offset" and triggering an offset- correcting-shift (of carriage) according to this invention. A special memory stage (cf NVRAM) can be used to store Reference Table I (x) values, plus four shift-voltage values (4 Zones) which are updated when tilt correction is required.

One object of the present invention is to teach novel methods and apparatus for correcting "upper-head offset" arising from "tilt" in a magnetic disk file, particularly for a drive which has a dedicated servo surface in the disk stack. Another object is to identify "bad" HDA's which exhibit excessive "Upper-Head offset" and associated head output degradation. A related object is to provide improved apparatus and methods for repositioning an HDA to ameliorate "Upper-Head offset".

Yet another object to provide an "Upper-Head offset servo" for positioning an HDA so as to minimize Upper-Head offset, as determined by the amplitude of "Gap^ & Gap " readout along disk tracks.

Another object is to provide such, using offset voltage to correct Upper-Head offset (arising from carriage tilt; e,g, use a dual polarity offset voltage to correct offset within servo limits) .

Another object is to provide improved apparatus and methods to yield Tilt criteria on a real-time basis, adding no overhead to system performance.

With these and other objects in view, as will become apparent to one skilled in the art as the description proceeds, this invention involves novel construction, combination, arrange ent of parts and methods substantially as hereafter described, and more particularly defined by the appended claims

BRIEF DESCRIPTION OF DRAWINGS:

The above, and other, features and advantages of the present invention will be appreciated by workers as they become better understood by references to the following detailed description of present preferred embodiments, these being considered in conjunction with the accompanying drawings:

Fig. 1 is a simplified block diagram of offset correction apparatus according to an embodiment of this invention;

Fig. 2 is schematic simplified perspective view of a Unisys 8470 Winchester disk drive, apt for using this invention;

Fig. 3 is a Head Disk Assembly (HDA) and Electromagnetic Actuator of such a drive utilizable with this invention, with Fig 3A schematically showing 32 heads and related parts sectionally and in part;

Fig. 4A is a very simple schematic perspective view of part of such an HDA, depicting "carriage tilt" away from the center of the spindle, while Fig 4B shows this as corrected by the invention; Fig. 5A is a like view depicting "carriage tilt" toward the center of the spindle while Fig 5B indicates correction of the tilt;

Fig. 6 is an extended block diagram of the Auto Upper Head Offset Servo embodiment shown in Fig. 1,

Fig. 7 shows the typical Gapl and Gap2 amplitude of Head 31 before and after upper head offset is applied in an Unisys 8470 type disk drive;

Fig. 8 is a timing diagram indicate exemplary acquisition of five samples of DC_Peak value of "Gap.. & Gap " amplitude for a SMD disk drive;

Fig. 9 shows SMD drive interface required for with a subject embodiment;

Fig. 10 shows an SCSI drive interface block diagram applicable with the present invention.

Fig. 11 shows ESDI drive interface block diagram applicable to the present invention, and

Fig. 12A, 12B, 12C are a Flow Chart of a preferred Automatic Offset Correction program embodiment.

DESCRIPTION OF PREFERRED EMBODIMENTS

The invention will be better appreciated by workers upon consideration of the following detailed description of some preferred embodiments. —General description, background;

The embodiments illustrate magnetic recording disk drive subsystems, including associated servo means with tilt correction means.

These, and the other means discussed herein, will generally be understood as selected, formulated, and operating according to present good practice, except where otherwise specified. And, except as otherwise specified, all materials, methods, and devise and apparatus herein will be understood as implemented by known expedients according to present good practice.

Embodiment I

As one preferred embodiment of my Offset Correction scheme, consider the block diagram in Fig 1, comprising an automatic upper head offset servo apparatus designated as 100, this including a read channel 101, a DC Peak detector 102, A/D converter circuit 103, drive interface 104, a servo uP 105 for "Gap. & Gap-" data acquisition and offset, an Offset D/A Converter and mux 106 with a suitable microprocessor uP. Associated summing and power amplifiers are designated as 107, (reside in the "electronic library" of the drive as does the servo channel 108). Read Channel circuit 101 is fed by an input line 110 for receiving disk data which include Gapl, Address mark, Gap2, Gap3 and Data. The read channel output line 111 is coupled to the DC_Peak detector, [and it can include amplifier means for the raw readback signal.]

DC_Peak detector 102 provides an a output line 112 to the A/D converter.

A/D converter 103 receives an Input Start Command 113, from the drive interface and Control logic 104. Digitized data from A/D converter 102 is designated as 114 (an 8-bit bus). A control bus designated as 115 originates from the uP 105 and goes to the drive interface and control logic 104 as well as to the Offset D/A converter 106. D/A 106 is employed in a bipolar mode. Its output may be buffered to provide offset voltage. (uP- compatible). The Offset voltage signal is designated as 117 and originates from D/A converter 106. The summing/power amplifier stage 107 drives a VCM 109 (Voice Coil Motor)

The Servo channel 108 receives input 120 and outputs position signal 119. The VCM 109 drives the Head Arm Assembly signal 121. The uP may preferably comprise an Intel iAPX188 microprocessor and is detailed below relative to Fig. 6.

A storage subsystem is shown in Fig. 2, consisting of an electronic library, an HDA and I/O Cable Adapter. As an embodiment of the invention, an Upper head Offset Servo Board is installed in this electronic library. The HDA is a sealed unit and can be removed from the drive.

Fig. 3 shows an HDA consisting of nine disks, which are stack-mounted on a common spindle which rotates counter¬ clockwise. The HDA has also nine moving head arm assemblies (eight 4-head Read/Write head/arm assemblies and one servo head/arm assembly). These nine assemblies are mounted on a single moving carriage assembly. A Coil assembly is secured within the casing to the rear of the HDA carriage assembly, protruding through a hole in the HDA faceplate. Current pulses passing through the coil assembly control the position of the coil and the carriage. The servo surface is composed of one band of prerecorded servo data tracks, which are used for "Seeking", "Track Following", Data Clocking, Index point signal generation, and Rotational position signal generation. Carriage Tilt is simplistically illustrated in Figs. 4A and 5A, where part of a typical "Head Disk Assembly" (HDA) is shown, including a carriage 11 controllably propelled across a carriageway on a base plate 13 to reciprocate transducing head structures (data heads h, servo head S) across the faces of the respective disks, DO, Dl,..etc. (i.e. across data tracks thereon) as known in the art. The disks are rotated by an associated spindle means SP.

Fig. 4 indicates carriage tilt "away from" the spindle, while Fig. 5 indicates carriage tilt "towards" the spindle.

The effect of such head offset is plotted in Fig. 4A where, assuming 32 stacked heads h, the bottom head (h-o) is depicted as "close to the center of the spindle", while the top head (h-31 not shown) will be understood as displaced the farthest from the center of the spindle (here assume about -300u" ) . Conversely, Fig. 5A similarly depicts +300u" tilt towards the center of the spindle.

To resolve such head offset, we are suggesting an "Auto Upper Head Offset Servo for Disk File" scheme that, in real time, will electronically shift the head assembly to (at least partly) compensate for the tilt. This method prefers to compensate tilt with reference to Head 16 or a like "medial head" The head offset servo receives, as input, head data reflecting "Gap, & Gap₂" readout on a real time basis. These data create two dimensional data arrays for Update Table II(x) (cf. read channel for data heads). A two dimensional Reference Table l(x) is created during HDA initialization. This Reference Table can be stored in an NVRAM memory and used to restore data during "power up". The recording surfaces (tracks) are divided into four (x=o, 1, 2, 3) zones to allow for mechanical warpage and like problems. Average readout data from heads 16 through 31 is stored in Reference Table I(x).

Comparison of the two tables is used to identify offset ("tilt"). Preferably, an Offset Voltage for each zone is stored in the NVRAM memory and is updated when tilt correction is required. The offset voltage is applied only prior to "Write Ready" and when the next linear mode is asserted. This automatic head offset servo method does not require added system overhead. Correction can be effected in real time using state of the art means.

Thus, visualize the effect of such "correction" in Fig. 4B, where carriage 11 in Fig. 4A will be assumed as shifted just enough — to the left— to place head 16 (the "medial" head) at "zero tilt" position (cf. the curve in Fig. 4B indicates this), with the rest of the heads being shifted to, essentially, re- distribute overall offset relatively equally between upper and lower heads —[Note: heads #17-#31, offset in staggered fashion to the right, or minus-offset, direction, with #31 being offset the most: i.e. about -150 u"; conversely for the lower heads with heads #0-#15 offset in staggered fashion to the left, and #0 being offset the most: i.e. +150u"3

A companion correction ("to-the-right") is indicated si plistically in Fig. 5B where carriage 11 in Fig. 5A will be assumed as shifted just enough — to the right — to place medial head 16 at "zero tilt" position, and to distribute overall-offset between upper and lower heads as in Fig. 4B (i.e. essentially, to "split-the-difference" ) .

—CHIP, Fig. 6

As a preferred integrated circuit embodiment of my electronic Upper Head Offset Servo, consider the block diagram in Fig. 6 comprising the following:

The Raw readback signals (through the head matrix of the drive and representing "Gap. & Gap " readout voltage) are received as the input designated as 200 by the read channel 37. This readback 200 is amplified by a Video Amplifier within the Read channel 37. A high speed DC_Peak Detector 38 receives the amplified readback signal via line 201, and detects the DC_Peak of the readback signal. (DC_Peak provided at output line 202) An A/D Converter 39 digitizes this DC_Peak of "Gap.. & Gap " readout providing a digital data signal on data bus 203 to the microprocessor 31. This microprocessor (uP 31) is employed for processing and controlling as noted elsewhere. The Status PAL stage 391 provides the head information to the microprocessor. Units 311, 317, and 33 are Address Latch, Data Transceiver and Control Register respectively. As firmware, EPROM 313 is used for uP 31, SRAM 315 is used for data storing and computation and (non-volatile RAM) NVRAM 36 is used for storing the Table I(x). A D/A converter 34 is used for generating Offset voltage via an associated Analog Mux 341. Thus, NVRAM 36 can load four points into DAC 34; at completion of each "SEEK", the uP will select the appropriate Zone and DAC setting.

More particularly, microprocessor unit 31 preferably comprises an Intel "iApxl88" microprocessor. The support devices for uP unit 31 include 2KB SRAM unit 315, and an 4KB EPROM containing firmware to provide a vehicle for the Auto Offset Servo.

The microprocessor uP is always in a "wait loop". When INTO occurs due to CAL_SW or TAG6 or TAG14, it starts acquiring five samples (digital data) of the readback signal. The firmware shorts-out the Normal Seek, or CAL REQ. The START command to the A/D converter 39 is synchronized with the Index Signal. At the end of the conversion by 39 (EOC), the iAPX188 processor reads the digital data. When iAPX188 asserts "-RD" and "-PCSO", the digitized data stored into the buffer of block 391 is read via data bus 203. The head number is also read by asserting l/o address "- PCSl" and "-RD". Writing into the control register 33 is achieved by asserting l/o port address PCSl and -WR. The data provided on the data bus 203 is written into Control Register 33. This provides the necessary control signals for the board in Fig. 6: EN_C0NV, +SIGN, -STORE, BAD_HDA, and RECL.

The interface signals TAG(0-3) and TAG_GATE are used to provide TAG6 and TAG14 for the LO CAR and HI CAR strobe, respectively. The decoded TAG6 and TAG14 are also used to generate INTO which initiates the acquisition of five samples and start offset correction (which, preferably, is enabled only during track-follow).

The NVRAM 36, is a 128 bytes deep module. This module is addressed by "mid memory" chip selects MCSO and MCS1. This approach is preferred where (as here) the size of NVRAM device is only 64 x 4. The data on data bus 203 is written into the SRAM portion of the NVRAM by asserting -WR and -MCSO and -MCS1. Data is transferred from SRAM to EPROM of the NVRAM by asserting - STORE and WR, MCS0/MCS1. The data written into the EPROM- portion of the NVRAM is permanently stored. The reading from the NVRAM is achieved by asserting -RECL, -RD and -MCSO/MCSl, with transfer of data from the EPROM portion of the NVRAM into the SRAM. The microprocessor uP31 reads on the data bus 203 by asserting -RD and -MCSO/MCSl (only).

The D/A converter 34, is an 8 bit device (e.g. pref. by "Analog Devices"). It has an internal data buffer and analog circuit. Offset data is written into the D/A device by asserting -WR and -PCS0. The processor updates offset data, Table III (x), whenever tilt is observed. This updated offset data is loaded into D/A when TAG6 or TAG14 is asserted during normal seek command.

The analog mux has a control signal, "Offset_Sel", which is used to pass Offset Voltage to the Servo (during Linear mode).

The operating code will be down-loaded into the SRAM 315 from the EPROM 313.

Fig. 8 suggests a Read/Write data format of SMD drive 8470/8480. (With Gapl, HA and Gap2 assumed wide enough.) The data is stored permanently during formatting of the HDA. These data are rewritten only during TI prep at the customer site. Two methods are available to install this equipment.

The First method is to initialize the HDA per the SMD format requirement. Table I(x) is created, accessing the drive from cylinder 0 through cylinder 629. Five samples of "Gap. & Gap " amplitudes are derived for each data head and for each cylinder. The "Upper" Heads selected: i.e. #16 ^'through #31. The average amplitude of head 16 through 31, for each zone, is stored in NVRAM 36 creating "Reference Table" l(x). The same data is down¬ loaded in SRAM creating "Update Table" II(x). Table II(x) will later be updated on a real time basis.

The Second method is used at a customer site where the HDA is not to be initialized. Here the DC_Peak algorithm is used to acquire Maximum Amplitude readout of "Gap. & Gap,,,, for each cylinder, thereby acquiring average amplitude of heads #16 through #31 for each zone. Thus, Table l(x) is created and stored in NVRAM 36. The Table II(x) will have the same data in SRAM 315 at the outset, but its data will be updated on a real time basis providing criteria for indicating "tilt".

The acquisition of five samples by the microprocessor is a preferred way of creating these Tables. Fig. 8 schematically indicates timing to acquire five samples. The microprocessor, (assume in "loop mode") will acquire five samples of DC_Peak of "Gap₁ & Gap₂" for heads #16 through #31. When Index pulse occurs, the sampling process starts (Fig. 8.1). The particular (selected) head starts reading "Gap & Gap " (Fig. 8.2) amplitude. The START pulses (Fig. 8.3) initiate A/D converter 39 to digitize the analog DC-Peak value of "Gap.. & Gap~". When End of Conversion (EOC) occurs (Fig. 8.4 i.e. after 25usec), the microprocessor reads the status bit DO (Fig. 8.5) and then it reads the digitized data. The average value is used in generating Table l(x) and Table II(x). The offset voltage (+- Voff) is generated by the D/A converter 34 through the analog mux 341. There are four offset voltage points stored in the NVRAM 36, these corresponding to four zones of the disk surface. These offset voltages are each designed to shift head 16 back to center so that its offset becomes effectively ZERO, thus simulating a "servo data disk surface" at the center of the disk stack.

Fig. 6 represents a preferred "chip implementation" of my invention. Advantageously, this Fig. 6 circuit may be implemented on one small circuit board (for an SMD interface type drive). The same kind of board is applicable for an SCSI/ESDI type drive (which differs only at the interface level).

The microprocessor (IApxl88 by Intel) used here has on-chip decoder means for selection of peripheral chip and memory chip. STATUS PAL ( 048 Oh )

The implementation of the CAR Register will be evident. An 8 bit register 391 provides LOW CAR and Status PAL, and HI CAR. This Status PAL 391 also provides HAR (head) information.

If CAL_SW is depressed, then CAR 256 and CAR 512 both assert a logical "1". The firmware differentiates the CAL_SW and HI CAR situations. The microprocessor 391 enters INTO routine and looks for "DO active" to go low, indicating end of conversion. Then it looks for "head number" to be equal to or greater than 16. If this is so, then acquisition of readback signal data starts. It should be noted that the sampling process starts upon reading the head number. The firmware is tightly coupled so that there is sufficient time to acquire data.

RESULTS;

It is surprising to note the results that can be realized with such an Auto Head Offset Servo board; (Fig. 6). For instance: Fig. 7 shows the increase in amplitude of "Gap₁ & ^GaP " ^{s read}~ out by head #31. This increase is referred to head 16 which has "peaked up" at a higher amplitude. This scheme simulates the servo at the center of the disk stack and therefore, the "lower" heads (0 through 15) will have to modulate the amplitude of "Gap. & Gap-," read out. The boards were installed in a test drive at several locations; this required minimal hardware modification. Good reliable performance was exhibited by the drive module, yet without impacting throughput.

Other results achieved are noted in Table I as follows:

TABLE I

(results with Fig.6 circuit used with Test Drive) a - Offset correction range will be +512uinch. b - Simulates the servo at the center of the disk stack, c - The Reference Table I(x) contains "Gap & Gap " amplitude data for heads 16 through 31 at the time of board initialization. This table is stored in NVRAM, d - Table II (x) contains real time updated data of "Gap. &

Gap-" amplitude for heads 16 through 31. e - Comparison of array points between these two tables gives the basis for updating offset voltage. An empirical formula is:

%decrease in amplitude+(31-head #)=25

This can be used to determine updated offset voltage, f - The four zones' offset voltage values are each updated and stored in the NVRAM. g - Zero voltage is applied during Seek mode; offset voltage is applied only during Linear mode (before Read or Write is asserted. ) h - This Auto Head Offset Servo scheme does not require any overhead time of the drive or the system CPU. i - NVRAM provides Ref. Table I(x) and Offset Voltage Table

III(x) —preferably provided during power up routine.

Update Table II(x) will initially be identical with

Ref. Table l(x). The microprocessor updates Update

Table Il(x) thereafter.

Disk Surface Zones:

The surfaces of each Test Disk are alike and have 630 data tracks (or "cylinders" up thru the stack). These 630 are divided into four zones conveniently as follows:

Zone 0 spans cylinders: 0 through 157 Zone 1 spans cylinders: 158 through 314 Zone 2 spans cylinders: 315 through 471 Zone 3 spans cylinders: 472 through 629)

Assuming all heads are perfect, "Reference Table I(x)" might look like this: (simplified): REF. TABLE I (x) example of

"Update Table II(x)" is created on a real-time basis. The two Tables will have identical data at the time of board initialization. Table II(x) is updated on a real time basis, and therefore, data in Table II(x) can vary from that of Table I(x). Thus Table II(x) might look like the following sample:

UPDATE TABLE II (x) example of

As time passes, the microprocessor will compare values in the Tables (i.e. two dimensional array of points or read-out voltages). If the amplitudes for head 16 through 31 fall, confirming the empirical formula:

^decrease in amplitude +(31-head #) ^~~ 25 then, the microprocessor updates the offset voltage using maximum peak search routine.

The "Offset Voltage TABLE" III (x) might be as follows: TABLE III (x) samples of V _f,

I Zone 0 I Zone 1 | Zone 2 [ Zone 3 | I +-V0 I +-V1 I +-V2 1 +-V3 1

These four Offset Voltage points (values) would be stored in NVRAM and down-loaded into SRAM for updating and for providing Offset Voltage during Linear Mode (Track-Follow). The microprocessor updates these data whenever Tilt Correction is required.

Simplified Offset Correction Method:

—Cf. for high speed Disk Drive system using stack of like disks accessed by (1 or more) multi-head Carriage; disks all having same"entry" on same Address sector of each Track, with common Gap-area following index pulse (cf. "Gap.. & Gap_" area commonly preceding data fields on such disks); and especially for system with "dedicated" servo, and with voice-coil actuated carriages.

—For each such Carriage, this Method corrects for Offset (e.g. eliminate "home address-errors"), by developing and applying Shift-voltage values V to shift Carriage so as to bring the "medial head" (middle head along stack) to ZERO offset position.

—This method involves read-out, V by a head (heads) of this "Gap.. & Gap-" area, then averaging this readout (voltage) across an entire sub-group of tracks (e.g. four sub-groups, each spanning 1/4 of the tracks) and using this averaged (V ) as a Tilt-indicator (Offset indicator) to invoke the said shift voltage.

i—Reference Readout set, variance therefrom indicates TILT:

—Preferably, this read-out Vga is developed for each of the

"upper" heads (medial plus those flanking on the extreme-tilt side, e.g. if Hd #16 is medial, develop V for each of heads

#16-31) along each track to establish "base values", placing the average of each (Vga) in memory (cf. average across each given track sub-group, or Zones 0, 1, 2, 3). Thus, for example, one can develop four values of V for each of "Upper" heads 16-31, or values V 0, V -1, V„ -2, V„ -3 for each head, at each zone, ya-" 9^ 9^- 9" to create a "Reference Table I" as below:

REF. TABLE

Head Zone Zone Zone Zone

etc etc

To repeat, each V value is the "Gap.. & Gap " readout voltage, averaged over all tracks in that Zone (sub-group of tracks). Thus, each Vga is used, according to the invention, to establish a "base" or "reference" against which one may assess offset by monitoring "current" V values — a serious variance therefrom ( V ) to be used to determine "offset". That is, workers will recognize that, as a carriage is tilted (e.g. as in Fig. 4A or Fig. 5A), the heads in a stack (especially "Upper" heads) will develop correspondingly less readout voltage as they traverse the "Gap. & Gap-" area. ii—Tilt-Correction referred to "medial" head:

—Preferably, where such Vga variances, indicate Offset,

(exceed a preset minimum), they are "referred" to the "Medial" head (e.g. Hd-16), so that, no matter which "upper" head indicates "offset", correction will take place by shifting the "medial" head back to its Zero Offset position, (cf. applying a corresponding shift-voltage V to shift carriage enough to do this) .

Thus, it may be convenient .to develop values of V corresponding to offset values ( ^v _σa) f°^{r one or} all, of upper heads (16-31).

For instance, one may develop, or compute, V values for a number of Vga values for each of heads 16-31. Then, when a g^iven variance Vga is detected for a g ^~-iven head, > a corresponding shift signal value can be applied to the carriage so as to shift it and bring head 16 back to Zero offset position (e.g. as in Fig 4B, 5B). As workers know, a known microprocessor control arrangement can effect this (e.g. via Table-Lookup etc).

Now, workers may wonder exactly when, and how, this is to be done: Preferably, the correction begins when a "new" track is arrived at (i.e. end of related SEEK operation and beginning related Linear, "Track-Follow" mode, whereupon, the subject

"upper-head" will pass the Index Pulse on its disk track (servo sector), and then immediately read-out Vga ("GapJ_η. & Gap J-L") to the special Correction Microprocessor, C-M, added for this invention — this head continuing on to the associated "data field" where its normal, called-for READ/WRITE will take place — after which a "NEXT SEEK" (usually to another track) will usually be invoked, this followed by the "Next-Track Follow" mode.

In this interim, this uP C-M will have had ample time to determine "Offset" (i.e. Vga if any), to ascertain the corresponding V etc — but will not apply V to shift the carriage until this "Next-Track-Follow" operation begins

(whereupon a new Vga will be read-out to uP C-M, as before)

This V shift awaits a following "Track-Follow" operation because it involves a like minor shift in carriage position and, hence, the correcting-shift will always be (at least) one track- operation late. This shouldn't matter if this "next-track" is in the same Zone; but if it is in one of the other three zones, "Tilt Conditions" there may be rather different of course (but, as noted elsewhere, this invention may be optimized so that a V is given for each of the four Zones, the uP selecting V for the "upcoming Zone") . iii—Variance monitored in "real time":

Preferably, the upper heads are monitored in some convenient fashion to give a running, real-time indication of offset this being used to "set a flag", to trigger automatic correction (as above) or the like. Workers will perceive that this can be done as with the method above for generating V ga readout voltage values (e.g. and a "Current Table II" may be thus developed and updated in the same general fashion as for Reference Table I).

Further, such may be done, conveniently, when any given upper head (all heads may be involved if one so chooses) gives a variance before it performs a READ or WRITE operation (or with each nth^* such operation, if this proves adequate) i.e. a g³iven Vga value resulting -> from comp earison of Current Vg_a with

(average) Ref. V for that head in that Zone, this V g ga corresponding with a predetermined V which is to be applied to shift the medial head (16) to Zero Offset.

This, of course, makes it unnecessary to physically access the medial head (#16), or to secure a "Gap₁ & Gap-" readout therefrom or to determine its Up ^cdated V ga — all selected Vga values for the other upper heads (#17-31) being referred to the medial head and a shift-voltage V applied that will reposition the medial head (#16) to zero offset. Workers will perceive obvious savings of time and complexity in doing this. Particularized Offset Correction:

A more particular version of the foregoing method follows. Here, a disk drive system like the Unisys 8470 is assumed, (with dedicated servo, voice coil, etc) with its HDA in place and ready for "initialization", the carriage being set and coupled to its disk stack. Four equal Zones (subgroups) of Tracks are assumed also.

1. For reference purposes, a Reference Table I is developed.

This is done by running each "upper" head (H-16 thru H-31) past the index point and past the "Gap. & Gap " area (or its equivalent) to develop a read-out voltage (DC equiv. ) for each track (or selected tracks) in the subject Track-Zone, averaging these across the Zone to derive an average readout Vga for each

Zone. These may be registered in memory as Reference Table I: with four values for each of heads 16-31, i.e. one Vga for each of the 4 Zones.

This assumes that all heads are (geometrically, spatially) aligned, with Zero Offset presumed (accepting any actual misalignment). It assumes that, even so, Vga can vary between heads and for different tracks for various reasons as workers realize: e.g. according to particular head characteristics, flying-height or velocity, according to magnetic coating variations at different tracks (cf. coating thickness often varies with track radial position).

2—Develop values of V for each head, each zone, various levels of Vga in Shift Table III.

This may be done experimentally, or be computed, in ways known in the art. For each of heads 16-31, at each of the four zones, + V values will be postulated, with corresponding +V shift values.

In operation of Drive, monitor Vga for "tilt" indication.

3. During operation of disk drive, periodically monitor for

V or "Tilt" [i.e. update the Update Table II, compare with

Ref. Table I and see if Vga exceeds preset minimum; This determines if "TILT" has occured].

Do this periodically for selected ones of upper heads 16-31.

For instance, we prefer to read-out "Gap. & Gap-" at the end of each SEEK as noted above [or alternatively every n SEEK, if this suffices] to avoid "Home-Address-Error". 4. If "TILT" found, initiate Carriage-shift so H-16 offset goes to zero:

This is, whatever Upper Head (16-31) shows "TILT" (excess V ), one ascertains what shift-voltage V (e.g. via Table- Look-up in uP C-M) is needed to bring medial-head to ZERO Offset (as above) — and one applies that V as programmed, (e.g. on next Track-Follow as noted above)

As a preferred optimization, the Vga detected may, further, be used to project four (4) values of shift voltage V ; c one for each of four Zones [subject Zone, plus other 3]; then, as the "Next-SEEK" proceeds, the associated destination-Zone identity may be fed to the uP C-M, which then will apply only that V for that Zone to shift the carriage.

The decision chain will involve successive queries on whether the "upcoming Zone" (for track-following) is Zone 0, 1,

2, 3; then the system initiates the offset-correcting Vc for the

"upcoming Zone", as workers will appreciate.

As an example of how the foregoing might be applied in an actual disk drive system like the Unisys 8740, I offer, below, examples of Initialization mode (Routine A), Search mode (Routine B) and Power-Up mode (Routine C), as follows. OFFSET Initialization Mode: Routine A

1. Back up the data and perform level I Prep.

2. Set the drive module in CE Inline Mode.

3. Enable the Auto Offset board.

4. Run a Seek-Seek routine to position the head from cyl 0 through 629. Select Head #16 also.

5. Store the digitized DC_PEAK values of "Gap.. & Gap." for each cylinder. Total samples will be 5 x 630 = 3150.

6. uP will optimize the four set points for four zones and will store in NVRAM.

7. uP will store them into Offset Search DACs.

OFFSET Search Mode: Routine B

1. Flag the TILT [0-3] gated by GAP12 gate.

2. If "TILT error", then request the SCU for a Non Standard REZERO routine.

3. If HD16 not selected within 24 hours, then request.the SCU for a Non Standard REZERO routine.

4. SCU selects HD16 and seeks to cyl. 0, 157, 315, and 473 sequentially.

5. When HD16 & Zone 0 asserted, adjust the Offset voltage for Zone 0. 6. When HD16 & Zone 1 asserted, adjust the Offset voltage for Zone 1.

7. When HD16 & Zone 2 asserted, adjust the Offset voltage for Zone 2.

8. When HD16 & Zone 3 asserted, adjust the Offset voltage for Zone 3.

Note: This method of solving the Offset problem is suggested due to 8470/8480 uP design constraints.

POWER UP Mode: Routine C (Board learns about HDA):

1. Reload set points data from the NVRAM into Offset Search DACs.

2. TILT error will request the SCU for a Non Standard REZERO routine.

3. When HD16 and Zone 0 asserted, adjust the Offset for Zone 0.

4. When HD16 and Zone 1 asserted, adjust the Offset voltage for Zone 1.

5. When HD16 and Zone 2 asserted, adjust the Offset voltage for Zone 2.

6. When HD16 and Zone 3 asserted, adjust the Offset voltage for Zone 3. *Design can be made modular for future expansion. Head selection can be jumper-selectable.

—Other Approaches

Workers should consider alternative methods of Offset- Correction. For instance, a system is contemplated that detects a prescribed kind of predetermined "Offset" (e.g. "Home-Address- Error"), whereupon the carriage is incremented in invariant fashion e.g. +0.1 volt to "bump" carriage an ave 2 u"to the Right".

Next, the system re-tests for Offset — if offsets still exists, then wait 1+ disk revolutions and repeat this 2u" - right "bump" (e.g. decide if +_ bump also?), then recheck for offset, etc.

Problems with this:

Read/Write must often wait, or be degraded; one must wait one or more disk revolutions to "fix" Offset; no qualitative determination of degree of Offset is determined; no adjustment is made for "normal" variations (e.g. due to head characteristics track/coating characteristics, fly-height/velocity of head, etc) — all unlike this invention. Also, unlike this invention:

— here is no use of common servo indicia (e.g. "Gap.. & Gap-" Read-out) to determine TILT/Offset degree; no use of this by a microprocessor (e.g. to flag TILT, to automatically initiate correction thereof); No use of such readout to create Reference head data or to, in real time, update such data and use variances therebetween to indicate "offset", and to correct for it.

— o Track-subgrouping (e.g. to average-out TILT in 1 of 4 Zones) .

—No correction limited to Linear, Track-follow mode —No simplification or distribution of Offset by focusing only on a medial head, (no referring of all carriage-shifting thereto, and

—to thereby eliminate offset of the medial head, and so redistribute overall offset).

—Disk drive overhead/user-time is greatly expanded. —Flow Chart (Figs. 12A, 12B, 12C); Figs 12A, 12B, 12C constitute a single Flow Chart summarizing a program designed to implement (automate) an Automatic OFFSET Correction embodiment like the foregoing. For clarity, the steps are given as follows: START;

1. Por and Reset;

2. Initialize iAPX188 and on Board Registers; 3. Cal-Req. switch Depressed;

4. Starts upts test 14;

5. Is into due to Tag6 or Tagl4;

6. Read Har [16-31];

7. Is Head 16 detected;

8. Peak up amplitude of each head. Find average V. . ;

then store. Average offset V into the dia and table, Find median head for 0, 1 cyl.

9. Is into;

10. Read Hs(i, j ) where i=16,17, — 31, j=2,3,—157 and Hs(i,j) data head amplitude. Then take Hs(i,j) for

Table I (o)

11. Is Median head;

12. Peak up amplitude of median head. Find offset-V and take ¹⁶ VoU (J=2,4,6,-156; ¹⁵⁷ Vo(k), K=3,5—157;

13. Is cylinder j=157;

14. Take average of ^l36 Vc(j); j=2,4,—156; ¹⁵⁷Vc(k), K=

3,5,—157 and store as Vce (o); Vco(o).

15. Is into;

16. Read Hs(i,j) where i=16,17, 31; j=158, 159, —315 and Hs(i, j) Data head amplitude. Then take Hs(i,j) for Table 1(1); 06952 -37-

17 . Is Median head;

18. Peak up amplitude of median head. Find offset V and take ³¹⁴V_c(j); j=158, 160, —314; ³¹⁵Vc(k); k=

159,161, 315;

19. Is cylinder j=315;

20. Take average of ³¹⁴Vo(j); j=158,160 314; ^3l5Vc(k)

k=159,161, 315; and store as Vcr(l), Vcα.(1) ;

21. Is into;

22. Read Hs (i, j ) where i=16,17 31 and J=316, 317, 472.

And Hs(i,j) data head amplitude. Take Hs(i,j) for Table 1(2);

23. Is median head

24. Peak up amplitude of Median head. Find offset-V and

472 471 take Vo(j); j=316,318,—472; Vo(k) k=317,

319, — 471;

25. Is cylinder j=472;

26. Take average of ⁴⁷² Vo(j); j=316, 317, —472,⁴⁷¹ Vo(k);

k=317, 319,—471 and store as Vce(2), Vco(2); 27. Is into; 28. Read Hs ( i , j ) where i=16 , 17 , 31 ; j=473 , 476 — 629

Hs(i,j) data head Gapl and Gap2 amplitude; Take

Hs(i, j) for Table 1(3);

29. Is median head;

30. Peak up amplitude of Median head. Find offset-V and take ⁶²⁸ Vo(j); j=474, 476, —628; ⁶²⁹Vc(k)

k=473,475,— 629;

31. Is cylinder 629 and head 31;

32. Take average of ⁶²⁸ Vo(j) j=474, 476, 628, ⁶²⁹ Vo(k)

k=473,475,—629, and store as Vce(3) Vco(3);

33. Take average of Hs(i,j) over each zone and store

in Table I(x) where x=o, 1,2,3; also store Table I(x) in NVRAM; Store also Vce(x) and Vco(x) where x=o,l,2,3, in NVRAM;

34. Create image of Table I(x) as Table II(x) for real-time comparision of Gapl and Gap2 amplitude;

35. End.

It will be understood that the preferred embodiments described herein are only exemplary, and that the invention is capable of many modifications and variations in construction, arrangement and use without departing from the spirit of what is claimed.

Workers will contemplate possible modifications. For example, the means and methods disclosed herein are also somewha applicable to other disk drive equipment and the like which are subject to offset problems.

The above examples of possible variations of the present invention are merely illustrative. Accordingly, the present invention is to be considered as including all possible modifications and variations coming within the scope of the invention as defined by the appended claims.

Claims

What is claimed is:

1. Apparatus for correcting carriage offset in a multi-disk drive system wherein each disk has a cooperating read-write (R/W) head carried on reciprocating carriage means, said apparatus comprising.

transport means for initially aligning said R/W heads and for causing each R/W head to traverse selected tracks of its associated disk and for providing readout signals from said R/W heads, said signals being indicative of a selected portion of an embedded sector along each selected track;

first memory means for storing said signals as "Reference Readout";

microprocessor means coupled to said memory means and adapted to use said Reference- Readout for offset-correction purposes; and

control means adapted to activate selected ones of said R/W heads to provide an update of said Reference Readout as Updated Readout which reflects the currect location of the said selected R/W head along a given selected track of its associated disk while each selected head is engaged in READ/WRITE operations along said given track;

second memory means for storing the updated readout as "Updated Readout"; and comparison means adapted to compare said Updated Readout with corresponding portions of said Reference Readout for producing calculated "Variance" therebetween as a measure of "Offset".

2. The invention of claim 1 which further includes correction means coupled to said comparison means and adapted to use the "Variance" to generate correction signals for shifting the position of the subject carriage to correct Offset.

3. The invention of claim 2 including, as part of said transport means, logic means coupled to said correction signals to provide a "medial-head position" by modified values of said correction- signals to be applied to said correction means,

said correction means being adapted to use the signals to effect the shift of said carriage means so as to eliminae offset for the selected medial head in the stack.

4. The invention of claim 1 wherein said apparatus is part of a "closed-loop" automatic Head Offset Servo system that shifts heads electronicaly to compensate for tilt doing so in "real time".

5. The invention of claim 3 wherein said tracks comprise cylinders divided and grouped into N Zones; wherein said logic means develops said values of modified correction-signals for each of said Zones; and wherein said microprocessor means includes means to control said selection of the so-modified correction signals to eliminate Offset of the medial head in the Zone occupied by said medial head; and including all heads flanking said medial head.

6. A method of detecting and correcting carriage offset in a multi-disk drive storage system of the type having associated read-write (R/W) heads carried on reciprocating transport means, comprising the step of:

initially aligning said R/W heads with tracks on the disk and then causing each said R/W head to traverse the associated disk media means and to provide Reference-Readout information reflecting the position of a selected initial gap-portion of the disk media means;

storing said Reference Readout in memory as a Reference Table;

providing dedicated microprocessor means adapted to use said Reference Readout information for offset-correction purposes;

selecting "extreme-offset ones" of said R/W heads to provide an update of said Reference Readout information which reflects the current alignment condition of said selected gap-portion of said disk media means, said selecting occuring while each selected R/W head is engaged in read or write operations;

storing the update of said Readout in memory as an "Update Table"; comparing said update of said Readout with the corresponding portions of Reference Readout information, and

using the variance therebetween as a measure of carriage offset.

7. The method of claim 6, also including:

using said variance to generate correction-signals, and

applying said correction-signals to said transport means to correct carriage offset.

8. The invention of claim 7 wherein said step of initial aligning said R/W heads further includes developing values of correction-signals adapted to so shift the position of the subject transport means as to effectively eliminate offset for a selected read write head in the stack.

9. The invention of claim 8, which further includes the step of dividing and grouping said disk media means into N Zones; wherein said values of said correction-signals are developed for each of said Zones; and wherein the step of selection of the correction-signal to eliminate Offset is controlled to reflect the Zone of N zones presently occupied by said read write head.