WO1991005415A1

WO1991005415A1 - Received signal strength indicator

Info

Publication number: WO1991005415A1
Application number: PCT/US1990/005050
Authority: WO
Inventors: Gary A. Kurtzman; Joseph P. Heck
Original assignee: Motorola, Inc.
Priority date: 1989-10-06
Filing date: 1990-09-24
Publication date: 1991-04-18

Abstract

An RSSI signal for indicating the strength of a received signal in a zero IF receiver is provided. The RSSI signal and the received signal level are logarithmically proportional. The received signal is mixed down in a down mixer (120), and produces a ZIF signal (125) having a substantially low frequency. The ZIF signal (125) is applied to an up mixer (140), and the output of the up mixer is applied to an AGC circuit (150). The AGC circuit (150) maintains the ZIF signal level constant by lowering the gain of the down mixer (120), after the received signal level has exceeded a threshold level. A first RSSI circuit (160) provides a first RSSI signal (165), when the received signal level is below the threshold level. A second RSSI circuit (190) provides a second RSSI signal (195), when the received signal is above the threshold level. Diodes provide a logarithmic transfer function for the first and second RSSI circuits. The first and second RSSI signals are summed together, by a summer (140), to provide a logarithmic RSSI signal.

Description

PATENT APPLICATION

RECEIVED SIGNAL STRENGTH INDICATOR

Technical Field

This invention relates generally to the field of radio receivers, in particular those receivers having a received signal strength indicator (RSSI).

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In a radio receiver, a received signal strength indicator (RSSI) signal may be utilized to enhance system features of a communication system in which the receiver is utilized. The RSSI signal indicates the power of the received signal. Accordingly, the received signal power(or strength) may be indicated by a DC voltage having a level which varies linearly with respect thereto. It is well known in the art that the received signal power, expressed in dbm, is logarithmically proportional to received signal level induced at a receiver antenna, generally expressed in μV (microvolts). Accordingly, in order to provide a linear relationship between the received signal power and the RSSI signal, a logarithmic relationship must exist between the RSSI signal and the received signal level. Conventionally, the RSSI signal is generated at an intermediate frequency (IF) stage of the receiver.

Referring to FIG. 1 , a block diagram of a conventional circuit for producing a logarithmic RSSI signal 30 is shown. An IF signal 25, which may be an output of a frequency mixer (not shown), is applied to an IF stage 50. The IF stage 50 includes a plurality of cascaded amplifier stages 10. Each amplifier stage 10 includes an amplifier 15 and a detector 20. The amplifiers 15 have identical gains and limiting characteristics to provide amplified signals, and the detectors 20 include circuitry to convert the amplified signals to corresponding DC outputs. As the received signal level increases, the IF signal level increases, and accordingly the DC output of each detector 20 increases. A summing stage 40 sums the DC outputs of each detector 20, and produces the RSSI signal 30. It may be appreciated that the RSSI signal 30 increases sharply before the of the amplifier stages 10 have reached limiting. This is because every detector 20 contributes to the increase of RSSI signal 30. Subsequent increases of the RSSI signal 30 are not as sharp, because the last amplifier stage 10 no longer contributes to the increase. Finally, the RSSI signal will become flat , when the first amplifier stage 10 has reached limiting. Because further increases of the received signal level no longer contribute to any of the amplifier stages 10.

FIG. 2 illustrates the variation of the RSSI signal 30 with respect to variation of the received signal level. A person of ordinary skill in the art will appreciate that the curve shown in FIG. 1 illustrates a substantially logarithmic relationship between the RSSI signal and the received signal level.

Some receivers produce a substantially low frequency IF signals. Since this IF frequency may be substantially zero Hertz (i.e. DC), the term zero IF (ZIF) is used in describing such IF signal. Utilization of ZIF signals in the receiver provides some advantages-, namely, it eliminates the need for complex high frequency bandpass IF filters, and facilitates integration of the IF circuitry on an integrated circuit (IC). The received signal is mixed down, by a downmixer, with a local oscillator (LO) signal having substantially the same frequency as the received signal thereby producing a low frequency ZIF signal. A simple lowpass filter may be used to filter out the spurious frequencies. Subsequently, a modulating signal may be recovered by any suitable demodulation technique. The demodulation technique may comprise upmixing, by an upmixer, the ZIF signal with a second high frequency local oscillator, and applying the output of the upmixer to a well known phase lock loop (PLL) demodulator. It is critical , however, to insure that the lowpass filter and the upmixer remain in their dynamic region and are not over driven due to increases in the received signal level. Therefore, an AGC circuit may be used to maintain a constant level at the input of the lowpass filter. Accordingly, the AGC circuit reduces the gain of the downmixer, when the received signal level has exceeded a threshold level.

The received signal strength indicator of FIG. 1 , may not be suitable for a ZIF receiver, since the low frequency zero IF signal has a substantially long transient settling time. Moreover, the high frequency signal at the output of the upmixer^* may not be used either, since this signal, due to gain control, is not indicative of the received signal level.

Summary of the Invention

Accordingly, it is an object of the present invention to provide a received signal strength indicator signal having logarithmic relationship to a received signal level.

Briefly, according to the invention, a circuit for indicating the level of a received signal comprises an intermediate circuit for producing an intermediate signal having a level, which corresponds to the received signal. The intermediate signal is applied to an automatic gain control circuit, which maintains the intermediate signal at a constant level. A received signal strength indicator circuit is responsive to the output of the automatic gain control circuit, and includes circuitry for providing a RSSI signal. The RSSI signal is logarithmically proportional to the received signal level.

Brief Description of the Drawings

Figure 1 is a block diagram of a conventional logarithmic received signal strength indicator. Figure 2 is a graph of the relationship between the received signal level and the RSSI signal.

Figure 3 is a block diagram of a portion of a receiver, which includes one embodiment of the received signal strength indicator of the present invention.

Figure 4 is a schematic diagram of another embodiment of the received signal strength indicator according to the present invention.

Figure 5 is a block diagram of a converter circuit for the automatic gain control circuit of FIG. 3.

Figure 6 is a schematic diagram of the downmixer, the gain control circuit and the received signal strength indicator circuit of FIG. 3.

Detailed Description of the Preferred Embodiment

Referring to FIG. 3, the preferred embodiment of the RSSI circuit of the present invention is included in a portion of a FM receiver 100. In the preferred embodiment of the invention, the circuits comprising this portion of the receiver 100 utilize BIMOS technology for integrating the circuit on a IC. The receiver 100 may be used in radio communication units, such as mobile two- way transceivers. In the receiver 100, a received radio frequency (RF) signal 110 is initially processed by a downmixer 120, which mixes the received signal 110 with a local oscillator (LO) signal 112, and provides an intermediate frequency (IF) signal 125. The frequency of the LO signal has been selected such that it is substantially equal to the frequency of the received signal 110. Therefore, the IF signal 125 has a substantially low frequency of preferably 28 Hz, which is primarily modulated at the baseband frequency. The IF signal 125 is applied to a well known baseband filter 130, which removes received spurious signals. In the preferred embodiment of the invention, modulating signal recovery is achieved by applying the output of the base band filter 130 to a suitable upmixer 140, which produces an upmixer signal 145 at preferably 131 kHz. Accordingly, the down mixer 120 and the baseband filter 130 and the upmixer 140 constitute processing means for the received signal 110. The upmixer signal 145 is subsequently applied to a phase lock loop (PLL) demodulator 180 which may be of of any suitable type. In order to avoid over driving the baseband filter 130 and the upmixer 140, the IF signal 125 is maintained at a constant level, after the received signal level exceeds a threshold level. An AGC circuit 150 controls gain of the down mixer 120, and may reduce the gain when the received signal exceeded the threshold level. The upmixer signal 145 is utilized as a feed back signal, since it is linearly proportional to the received signal level 110. The AGC circuit 150 comprises a detector circuit 151 coupled to a gain control circuit 158. The detector circuit 151 provides a signal corresponding to the received signal 110. The gain control circuit 158 is coupled to the detector circuit 151 , and provides a AGC signal 155, which reduces the gain of the mixer 120.

The received signal level may be indicated by the upmixer signal 145 before a threshold level of the received signal 110 is exceeded, and it may be indicated by AGC signal 155 after the threshold level of the received signal 110 is exceeded. Accordingly, the upmixer signal 145 is coupled to a first RSSI circuit 160 to provide a first RSSI signal 165 when received signal is below the threshold level, and the AGC control signal 155 is coupled to a second RSSI circuit 190 to provide a second RSSI signal 195, when received signal is above the threshold level. Referring to FIG. 4, schematic diagram of the first RSSI circuit 160 of FIG. 3 is shown. The upmixer signal 145 is applied to a half wave rectifier 161. The output of the half wave rectifier 161 is coupled to a well known filter comprising a resistor 162 and a capacitor 163, which provides a filter output 164. The filter output 164 has a DC voltage level corresponding to the level of the upmixer signal 145. It is well known in the art that the voltage across a non-liner processing means, such a diode, and the current through it have a logarithmic relationship. The filtered signal 164 is coupled to a well known voltage to current converter 166 to provide an output current 367. A non-linear processing means comprising two diodes 167 and 168 provide a logarithmic transfer function for the first RSSI circuit 160. A current source 169 sources a constant current 368. The output current 367 is applied to the diode 167, and the constant current 368 is applied to the diode 168. One of ordinary skill in the art appreciates that the voltage potential produced across the anodes of the diodes 168 and 169 is logarithmically proportional to mixer output signal 145, and accordingly to the received signal 110. This voltage potential is the first RSSI signal 165.

Referring to FIG. 5, a block diagram of the detector circuit 151 of the AGC circuit 150 is shown. The detector circuit 151 receives the upmixer signal 145 and applies it to a well known peak detector 152, which provides a detector voltage 153. The detector voltage 153 is applied to a well known current converter 154, in order to convert the received signal level to proportional identical current signals 156 and 157. The current converter 154 utilizes well known current mirroring circuitry to provide the identical currents 156 and 157, wherein they linearly correspond to the detector voltage 153.

Referring to FIG. 6, the schematic diagram of the gain control circuit 158, the downmixer 120 and the second RSSI circuit 190 is shown. The downmixer 120 comprise a well known Gilbert mixer, and is utilized to function as a balanced mixer. An RF signal 610, which comprises preselected received signal, and its complement NRF signal 620 ( i.e., NRF signal 620 is 180 degrees out of phase with the RF signal 610) are coupled to differential pair 656. A LO signal 630 and its complement NLO 640 are coupled to differential pairs 652 and 654. A current sink 660 sinks a constant current 662, which is ideally equal to the sum of currents 602 and 603. The differential pairs of the downmixer 120 are sized such that in absence of mixer input signals, currents 602 and 603 are identical. The output of the downmixer 120, the IF signal 125 of FIG. 3, is taken at nodes 664 and 666, and provides a balanced input to the baseband filter 130. In FIG. 6, the current 156 of FIG.5 is shown as a current source 156. A transistor 632, a transistor 634, a diode 642 and a diode 644 comprise the gain control circuit 158, which is a well known translinear loop. The current 156 is supplied to the downmixer 120 through the diodes 642 and 644, and controls the gain of the downmixer 120. When the current 156 is increased (due to increase in the received signal level), the currents 602 and 603 are reduced accordingly. This is because the current sink 660 sinks a constant current 662, therefore any current increase due to current 156 must be compensated by current decreases in the currents 602 and 603. As a result the gain of the downmixer 120 is reduced, when the received signal level is increased, thereby the IF signal 125 is maintained at a constant level. Accordingly, the detector circuit 151 and the gain control circuit 158 constitute the automatic gain control means for the receiver 100. According to the above discussion, the received signal level is proportional to the sum of currents 602 and 603 and the current 662. Therefore, in the second RSSI circuit 190, these currents are duplicated, and indicate the received signal level. The current 662 of the down mixer 120 is duplicated by providing a current sink 670, which is one half of the current sink 660. The second RSSI circuit 190 also comprises a gam control circuit 605, which is identical to the gain control circuitry 158. The differential pairs 682 and 684 are duplicates of differential pairs 652 and 654, and are shown in a circuit block 695. Accordingly, the currents 602 and 612, and currents 603 and 613 are mirrored, and they vary identically as the currents 156 and 157 are changed. A current 696, which is the sum of the currents 636 and 638, flows through a diode 692, and a current 672 which is sunk by the current sink 670 flows through a diode 694. As described in conjunction with the first RSSI signal 165, the second RSSI signal 695 obtained at nodes 698 and 699 has a logarithmic relationship to the received signal level, and corresponds to the second RSSI signal 195 of FIG. 3.

Now referring back to FIG. 3, the first RSSI signal 165 and the second RSSI signal 195 are summed together by a well known summing circuit 170 to provide an RSSI signal 175. Accordingly, the level of the RSSI signal 175 is logarithmically proportional to the level of the received signal 110.

It will be appreciated by one of ordinary skill in the art that the described preferred embodiment of the invention is only one variation for implementing the received signal strength indicator circuit of the invention, and other variations are possible without deviating from the true scope of the present invention.

What is claimed is:

Claims

1. A circuit for determining the level of a received signal, comprising: processing means for processing said received signal and providing an intermediate signal, automatic gain control means coupled to said intermediate circuit means and responsive to said received signal level for maintaining said intermediate signal at a substantially constant level when said received signal exceeds a predetermined level, a received signal strength indicator means responsive to said automatic gain control means for providing a signal being logarithmically proportional to said received signal level.

2. The circuit of claim 1 , wherein said circuit comprises a portion of a radio frequency receiver.

3. The circuit of claim 2, wherein said received signal strength indicator means utilizes at least one diode for providing said logarithmically proportional RSSI signal.

4. The circuit of claim 3, wherein said processing means includes a frequency mixer.

5. The circuit of claim 4, wherein said intermediate signal comprises an intermediate frequency signal for said receiver.

6. The circuit of claim 5, wherein said receiver is utilized in a transceiver.

7. A circuit for indicating the level of a received signal, comprising: processing means for processing said received signal and providing an intermediate signal, automatic gain control means coupled to said processing means and responsive to the level of said received signal for maintaining said intermediate signal at a substantially constant level when the level of said received signal exceeds a predetermined level, first received signal strength indicator means for providing a first signal when the level of said received signal is below said predetermined level, second received signal strength indicator means for providing a second signal when the level of said received signal is above said predetermined level, summing means for summing said first signal and said second signal.

8. The circuit of claim 7,wherein said first signal and said second signal have a logarithmic relationship to the level of said received signal.

9. The circuit of claim 8, wherein said first and said second received signal level indicator circuits utilize at least one diode to provide said logarithmic relationship.

10. The circuit of claim 9, wherein said circuit is a portion of a radio frequency receiver.

11. The circuit of claim 10, wherein said processing means includes a frequency mixer.

12. The circuit of claim 11 , wherein said intermediate signal comprises an intermediate frequency signal for said receiver.

13. The circuit of claim 12, wherein said receiver is utilized in a transceiver.

14. A circuit for indicating the level of a received signal , comprising: processing means for receiving said received signal and providing an output signal being linearly proportional thereto, received signal level indicator means including non¬ linear processing means for receiving said output signal and providing a signal being logarithmically proportional to the level of said received signal.

15. The circuit of claim 14, wherein said circuit is a portion of a radio frequency receiver.

16. The circuit of claim 15, wherein said intermediate circuit means comprises a frequency mixer.

17. The circuit of claim 16, wherein said intermediate signal comprises an intermediate frequency signal for said receiver.

18. The circuit of claim 17, wherein said intermediate frequency signal has a substantially zero frequency.

19. The circuit of claim 18, wherein said receiver is utilized in a transceiver.

20. The receiver of claim 14, wherein said non-linear processing means comprises at least one diode.