WO1991001027A3 - Detection de sequence interdite et circuit de protection - Google Patents

Detection de sequence interdite et circuit de protection

Info

Publication number
WO1991001027A3
WO1991001027A3 PCT/US1990/003397 US9003397W WO9101027A3 WO 1991001027 A3 WO1991001027 A3 WO 1991001027A3 US 9003397 W US9003397 W US 9003397W WO 9101027 A3 WO9101027 A3 WO 9101027A3
Authority
WO
WIPO (PCT)
Prior art keywords
data
protection circuit
sequence detection
illegal
illegal sequence
Prior art date
Application number
PCT/US1990/003397
Other languages
English (en)
Other versions
WO1991001027A2 (fr
Inventor
Kuo-Hui Liu
Original Assignee
Pacific Bell
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pacific Bell filed Critical Pacific Bell
Publication of WO1991001027A2 publication Critical patent/WO1991001027A2/fr
Publication of WO1991001027A3 publication Critical patent/WO1991001027A3/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0763—Error or fault detection not based on redundancy by bit configuration check, e.g. of formats or tags
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/24—Testing correct operation
    • H04L1/242—Testing correct operation by comparing a transmitted test signal with a locally generated replica
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0057—Operations, administration and maintenance [OAM]
    • H04J2203/006—Fault tolerance and recovery

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

Circuit pour éliminer les séquences de données interdites provenant d'un flot de données. Le circuit (10) examine et mémorise une partie d'un flot de données d'entrée (28). La séquence de données reçue précédemment est ensuite examinée. Si les données reçues précédemment concordent avec une séquence interdite, les données mémorisées sont modifiées. Les données mémorisées sont alors extraites pour former une séquence de sortie (29).
PCT/US1990/003397 1989-07-13 1990-06-18 Detection de sequence interdite et circuit de protection WO1991001027A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/379,487 US5023612A (en) 1989-07-13 1989-07-13 Illegal sequence detection and protection circuit
US379,487 1989-07-13

Publications (2)

Publication Number Publication Date
WO1991001027A2 WO1991001027A2 (fr) 1991-01-24
WO1991001027A3 true WO1991001027A3 (fr) 1991-03-21

Family

ID=23497470

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1990/003397 WO1991001027A2 (fr) 1989-07-13 1990-06-18 Detection de sequence interdite et circuit de protection

Country Status (2)

Country Link
US (1) US5023612A (fr)
WO (1) WO1991001027A2 (fr)

Families Citing this family (30)

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JPH04262630A (ja) * 1991-02-15 1992-09-18 Fujitsu Ltd 衛星通信方式
JPH0512809A (ja) * 1991-07-03 1993-01-22 Nec Corp デイスク駆動装置のフオーマツト制御回路
US5544180A (en) * 1992-06-08 1996-08-06 Qlogic Corporation Error-tolerant byte synchronization recovery scheme
US5606604A (en) * 1993-12-13 1997-02-25 Lucent Technologies Inc. System and method for preventing fraud upon PBX through a remote maintenance or administration port
FR2715786A1 (fr) * 1994-02-02 1995-08-04 Trt Telecom Radio Electr Système de transmission de données transmises par une liaison comprenant des équipements intermédiaires et équipement intermédiaire pour un tel système.
US5603941A (en) * 1994-05-03 1997-02-18 Lonza, Inc. Multifunctional biodispersant/biocidal compositions
US5809091A (en) * 1996-06-04 1998-09-15 Ericsson, Inc. Timing signal generator for digital communication system
US5955977A (en) * 1997-03-31 1999-09-21 Sharp Laboratories Of America, Inc. System for avoiding start code emulation and long carry-over propagation
US6185649B1 (en) * 1998-05-19 2001-02-06 Toshiba America Electronic Components, Inc. System for correcting an illegal addressing signal by changing a current bit from one to zero if a bit immediately left adjacent to the current bit is zero
US6362763B1 (en) * 2000-09-15 2002-03-26 Texas Instruments Incorporated Method and apparatus for oscillation recovery in a delta-sigma A/D converter
US6760791B1 (en) * 2001-10-15 2004-07-06 Advanced Micro Devices, Inc. Buffer circuit for a peripheral interface circuit in an I/O node of a computer system
US7111228B1 (en) 2002-05-07 2006-09-19 Marvell International Ltd. System and method for performing parity checks in disk storage system
US7287102B1 (en) 2003-01-31 2007-10-23 Marvell International Ltd. System and method for concatenating data
US7007114B1 (en) * 2003-01-31 2006-02-28 Qlogic Corporation System and method for padding data blocks and/or removing padding from data blocks in storage controllers
US7870346B2 (en) * 2003-03-10 2011-01-11 Marvell International Ltd. Servo controller interface module for embedded disk controllers
US7080188B2 (en) * 2003-03-10 2006-07-18 Marvell International Ltd. Method and system for embedded disk controllers
US7492545B1 (en) 2003-03-10 2009-02-17 Marvell International Ltd. Method and system for automatic time base adjustment for disk drive servo controllers
US7064915B1 (en) 2003-03-10 2006-06-20 Marvell International Ltd. Method and system for collecting servo field data from programmable devices in embedded disk controllers
US7039771B1 (en) 2003-03-10 2006-05-02 Marvell International Ltd. Method and system for supporting multiple external serial port devices using a serial port controller in embedded disk controllers
US7526691B1 (en) 2003-10-15 2009-04-28 Marvell International Ltd. System and method for using TAP controllers
US7139150B2 (en) * 2004-02-10 2006-11-21 Marvell International Ltd. Method and system for head position control in embedded disk drive controllers
US7120084B2 (en) * 2004-06-14 2006-10-10 Marvell International Ltd. Integrated memory controller
US8166217B2 (en) * 2004-06-28 2012-04-24 Marvell International Ltd. System and method for reading and writing data using storage controllers
US9201599B2 (en) * 2004-07-19 2015-12-01 Marvell International Ltd. System and method for transmitting data in storage controllers
US8032674B2 (en) * 2004-07-19 2011-10-04 Marvell International Ltd. System and method for controlling buffer memory overflow and underflow conditions in storage controllers
US7757009B2 (en) * 2004-07-19 2010-07-13 Marvell International Ltd. Storage controllers with dynamic WWN storage modules and methods for managing data and connections between a host and a storage device
US7386661B2 (en) 2004-10-13 2008-06-10 Marvell International Ltd. Power save module for storage controllers
US7240267B2 (en) * 2004-11-08 2007-07-03 Marvell International Ltd. System and method for conducting BIST operations
US7802026B2 (en) * 2004-11-15 2010-09-21 Marvell International Ltd. Method and system for processing frames in storage controllers
US7609468B2 (en) * 2005-04-06 2009-10-27 Marvell International Ltd. Method and system for read gate timing control for storage controllers

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3990049A (en) * 1975-05-12 1976-11-02 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Selective data segment monitoring system
US4169212A (en) * 1975-04-14 1979-09-25 Datotek, Inc. Multi-mode digital enciphering system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4169212A (en) * 1975-04-14 1979-09-25 Datotek, Inc. Multi-mode digital enciphering system
US3990049A (en) * 1975-05-12 1976-11-02 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Selective data segment monitoring system

Also Published As

Publication number Publication date
WO1991001027A2 (fr) 1991-01-24
US5023612A (en) 1991-06-11

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