WO1990016105A1 - Alimentations ininterrompues en courant - Google Patents

Alimentations ininterrompues en courant Download PDF

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Publication number
WO1990016105A1
WO1990016105A1 PCT/GB1990/000958 GB9000958W WO9016105A1 WO 1990016105 A1 WO1990016105 A1 WO 1990016105A1 GB 9000958 W GB9000958 W GB 9000958W WO 9016105 A1 WO9016105 A1 WO 9016105A1
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WIPO (PCT)
Prior art keywords
voltage
bus
battery
output
reversible
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Application number
PCT/GB1990/000958
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English (en)
Inventor
James William Piper
Original Assignee
James William Piper
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Publication date
Application filed by James William Piper filed Critical James William Piper
Publication of WO1990016105A1 publication Critical patent/WO1990016105A1/fr

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J9/00—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting
    • H02J9/04—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source
    • H02J9/06—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems
    • H02J9/061—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems for DC powered loads

Definitions

  • This invention relates to power supplies and has particular (though not sole) application to the provision of an uninterruptible power supply for mainframe and mini computers and other load critical situations.
  • the invention also relates to buffering; protecting the load from damaging impulses delivered via the mains supply, and conversely protecting the mains supply from harmonic distortion as a result of current consumption peaks within each cycle.
  • this feature will form part of the uninterruptible power supplies of this invention but the invention could be provided as a separate power line filter.
  • UPS uninterruptible power supply
  • An UPS In the event of a fault condition an UPS can maintain the supply electrical power to a critical load with no break and no perceptible discontinuity at the time of the fault.
  • Such power supplies are essential for large computers where even momentary loss of power below the industry guideline of 16% below nominal level may cause a system shut-down at a very considerable cost. Furthermore under some conditions data may be lost and may be almost impossible to recreate thereby causing concern for financial transactions and other areas where security is important.
  • UPS Standby or back-up power supplies where a disruption of a few seconds before the alternate source can commence supply is not really critical.
  • An ideal UPS would includes means to test itself and particularly whether its batteries are still capable of delivering full current, while under normal load, without interruption of the supply to its critical load.
  • UPSs operate in the manner shown in Figure 1. Input power from an AC supply is transformed (in Tl) and rectified (by Rl) and used to charge a battery (Bl). Power from this battery is then used to synthesise an output voltage waveform within the inverter II to supply the load through the transformer T2. In the event of a power supply failure the output is still driven by the battery so that no disruption occurs.
  • the UPS has a number of characteristics.
  • the input power goes through a transformer so that when it is rectified the voltage produced is suitable for charging the battery.
  • the output from the battery is inverted with an inverter to produce, commonly, a synthesised sinewave output which again goes through a transformer to produce a mains compatible output voltage.
  • the inverter waveforms must also vary to hold the fundamental output voltage constant
  • UPSs provide a battery level-of-charge indication but this may not reflect the capacity of their batteries - at some time in the future - to actually deliver the required amount of electric power.
  • the current taken by the rectifier may have significant harmonic content causing harmonic pollution of the utility power supply.
  • the power factor of the input is likely to vary considerably from unity.
  • the input and output transformers are quite bulky, heavy and expensive.
  • the efficiency of the system is typically 80%.
  • the invention provides power supply apparatus comprising an input stage, a storage stage, an output stage, and at least one common bus; wherein said input stage includes an input from an AC supply, means for reversibly converting an incoming alternating current at first AC voltage into a direct current supplied to said at least one common bus at a DC bus voltage which is higher than said first AC voltage, and means for controlling said DC bus voltage; said storage stage comprises means for controllably storing charge which in use allows the charge to be returned to said at least one common bus to maintain the DC bus voltage within predefined limits; and said output stage includes means for regulating the output voltage.
  • the power supply apparatus is configured as an uninterruptible power supply wherein said storage stage comprises storage batteries, a reversible DC-DC converter between said at least one common bus and said storage batteries, and means for controlling the said reversible DC-DC converter to allow in use either (a) the batteries to draw current from said bus for charging or maintaining the charge in said batteries or (b) the batteries to supply current to said bus.
  • said storage stage comprises storage batteries, a reversible DC-DC converter between said at least one common bus and said storage batteries, and means for controlling the said reversible DC-DC converter to allow in use either (a) the batteries to draw current from said bus for charging or maintaining the charge in said batteries or (b) the batteries to supply current to said bus.
  • this power supply apparatus also includes a battery test means which in use allows the storage batteries to be tested under full load by causing said batteries to discharge power into said at least one common bus for a limited time and back into said AC supply via said reversible converting means, and means for monitoring the extent of battery voltage drop so caused.
  • a battery test means which in use allows the storage batteries to be tested under full load by causing said batteries to discharge power into said at least one common bus for a limited time and back into said AC supply via said reversible converting means, and means for monitoring the extent of battery voltage drop so caused.
  • the uninterruptible power supply has an AC input voltage and an AC output voltage, wherein the common bus is maintained at a DC bus voltage substantially greater than the expected peak AC input voltage, but is not otherwise a function of the input voltage.
  • the DC bus voltage is also substantially higher than the peak voltage of the required output voltage from the output stage.
  • the input rectifier means is of the reversible rectifier type to allow the instantaneous current consumption of the UPS to have the same waveform as the incoming voltage - that is to say that it mimics a pure resistance and causes minimal harmonic pollution of the utility supply.
  • the input rectifier means is of the reversible rectifier type in order to allow the battery means to be tested on full load; when said reversible rectifier operates in reverse to dump the power added to the bus(es) from the battery.
  • all voltage-translation stages are of the hysteretically controlled current- forced reversible rectifier configuration employing semiconductor switches as the switching elements, and operating, for medium to large UPSs, in the 5-15 KHz frequency band.
  • the invention provides a UPS having an input capable of receiving an AC input at a first voltage, a DC bus operative at a bus DC voltage which is substantially higher than said first voltage, said input stage connected to said DC bus by rectifier means to supply said bus DC voltage, means for sensing a predetermined drop in said bus DC voltage, battery means capable of supplying said bus DC voltage when required, battery control means capable of connecting said battery means to said DC bus in response to the detection of said predetermined drop in said bus DC voltage, and an output stage connected to said DC bus.
  • the output stage consists of a reversible rectifier configuration as before, creating a sine-wave AC power waveform based on stored reference data. Preferably this is phase-locked to the input mains supply to avoid hazard, or transient impulses when the UPS is bypassed.
  • said battery control means allows the battery means to be charged from or (more usually) to draw a float current from the DC bus.
  • the said battery control means allows substantial currents to be drawn from the battery when the UPS is replacing the usual mains power supply, or during tests.
  • the UPS may be started from the mains supply - even if die batteries have no remaining charge.
  • the UPS may be used in conjunction with a local generator - wherein considerations of frequency instability and gradual introduction of heavy loads must particularly be taken into account
  • each of the stages of the UPS is modular, so that the capacity or voltage requirements of the input output/battery stage can be changed by connecting different modules to the DC bus, or by adding modules to become a larger capacity or even a multi-phase version of the single-phase device described below.
  • the invention provides a power line filter capable of protecting the load from damaging impulses delivered via the mains supply, and conversely, protecting the mains supply from harmonic distortion as a result of current consumption peaks within each cycle.
  • Figure 1 is a schematic circuit diagram illustrating a conventional UPS.
  • FIG. 2 is a schematic circuit diagram illustrating a UPS constructed in accordance with this invention, having an input stage, a battery control stage, and an output stage.
  • Figure 3 is a circuit outline showing power control means for a reversible rectifier responsive to both positive and negative bus voltages, and sensed current Figures 11 and 12 are practical embodiments of this Figure.
  • FIG. 4 is a circuit diagram of a preferred embodiment of the UPS, showing the components connected to the switches S1..S6 of
  • Figure 5 is a block diagram of a preferred embodiment of the UPS, showing as blocks the controlling circuitry connected to the switches S1..S6 of Figure 2.
  • Figure 6 is a circuit diagram of part of a preferred embodiment of the
  • Figure 7 is a circuit diagram of part of a preferred embodiment of the
  • UPS showing circuit elements used to drive the reversible rectifier switches between the buses and the battery.
  • Figure 8 is a circuit diagram of part of a preferred embodiment of the
  • UPS showing circuit elements used to generate the PWM-like pulses in response to battery voltage and current drawn, and the DC bus voltage. It also accepts a Vboost input
  • Figure 9 is a circuit diagram of part of a preferred embodiment of the
  • UPS showing circuit elements used in conjunction with Figure 6, to inhibit battery testing under fault conditions.
  • Figure 10 is a circuit diagram of part of a preferred embodiment of the
  • UPS showing circuit elements which implement control functions, particularly during starting-up.
  • FIG 11 is a circuit diagram of part of a preferred embodiment of the UPS, showing circuit elements used to generate a PWM-like pulse train to ultimately drive the output reversible rectifier switches.
  • Figure 12 is a circuit diagram of part of a preferred embodiment of the UPS, showing circuit elements used to drive the reversible rectifier switches that generate the output AC power.
  • Figure 13 is a circuit diagram of part of a preferred embodiment of the UPS, showing circuit elements involved with generation of a PWM-like waveform for control of the switches SI and S2 at the input of the UPS.
  • FIG. 14 is a circuit diagram of part of a preferred embodiment of the UPS, showing circuit elements used to drive the reversible rectifier switches S 1 and S2, at the UPS input
  • FIG. 15 is a circuit diagram of part of a preferred embodiment of the UPS, showing circuit elements used to supervise the internal high-voltage buses.
  • FIG 16 is a circuit diagram of part of a preferred embodiment of the UPS, showing circuit elements involved with the soft-start process.
  • FIG 17 is a circuit diagram of part of a preferred embodiment of the UPS, showing circuit elements used for protection, in particular over-voltage protection and for other alarm signals.
  • FIG. 18 is a circuit diagram of part of a preferred embodiment of the UPS, showing circuit elements used for protection, in particular against bus imbalance (of eitiier side with reference to ground) of the capacitors.
  • FIG 19 is a circuit diagram of part of a preferred embodiment of the UPS, showing circuit elements used for component protection, in particular over-current protection of the output stage.
  • FIG 20 is a circuit diagram of part of a preferred embodiment of the UPS, showing those circuit elements that actually drive the (included) semiconductor switches of the reversible rectifiers. This circuitry floats at a high voltage and is powered through the pulse transformer.
  • references to particular design approaches, currents, voltages or component values are for the purpose of illustration only and are in no way limiting because the invention can be embodied in many different configurations depending upon the supply voltage and number of phase lines, power rating, and number of inputs or outputs required.
  • the DC bus voltage is preferably significantly greater than the nominal AC supply voltage. For example if the supply voltage is 110 volts AC (as for single-phase lines in the USA) then the preferred DC bus voltage would be about 400 volts (200V each side of the neutral line).
  • the advantages of a UPS with a DC bus system is that all elements of the UPS may be modular. There are three major elements: an input stage feeding the bus or buses (comprising Ll, SI and S2 with associated controllers, a battery control stage (comprising S3, S4, L2 with associated controllers, and an output stage (comprising S5, S6 and L3 with C3) and these will now be described with reference to Figure 2. It should be appreciated that this configuration is equally capable of operating under DC supply, and/or DC load conditions, as the reversible rectifier is capable of acting as a DC-DC converter. In practice, virtually all utility supplies are AC although in some applications a DC output may be required.
  • the input stage preferably has a reversible rectifier capable of converting the nominal 230 volt AC input to the bus-to-bus voltage of say 700 volts; or 350 volts each side of neutral for one preferred embodiment
  • the battery control stage preferably has a reversible rectifier acting as a DC-DC converter capable of supplying a battery charge voltage of for example 210 volts (for the preferred 90 cell battery) or a float voltage of for example 203 volts, and conversely the battery output can be stepped up to supply the bus voltage of 700 volts when required.
  • a reversible rectifier acting as a DC-DC converter capable of supplying a battery charge voltage of for example 210 volts (for the preferred 90 cell battery) or a float voltage of for example 203 volts, and conversely the battery output can be stepped up to supply the bus voltage of 700 volts when required.
  • the output stage preferably has a further reversible rectifier stage acting as an inverter capable of supplying a nominal 110 or 230 volt AC output; in accordance with the input to the UPS, although in some applications it may be preferable to provide one or more DC-DC converters if an output DC voltage is required (eg running directly to the DC bus of a computer thereby bypassing the computers internal power supply).
  • the DC bus system comprises a positive busbar and a negative busbar (labeled + and -) and two electrolytic capacitors Cl and C2 with their centre tap connected to the incoming neutral of a single phase supply.
  • the capacitors which have a reserve capacity corresponding to the duration of several cycles of the mains, are composed of one set of three 4700 microfarad 350V capacitors (Sprague or Marcon) between each bus and ground.
  • the input stage comprises inductor Ll, and switches SI, and S2.
  • the battery stage comprises switches S3 and S4, inductor L2 and battery B.
  • the output stage comprises switches S5 and S6, inductor L3 and capacitor C3. All these components are interconnected as shown in Figure 2. Note that there is no interconnection between any of these stages - all stages simply connect from their respective source/sink to the DC bus.
  • the input stage operates by taking power from the input phase supply to maintain the DC bus system at its rated (say 700 volt) voltage.
  • the battery stage takes power from the bus to maintain the battery voltage which may be of the order of 90V and the output stage takes power from the bus to produce an output voltage waveform. This is the normal operating mode for the UPS.
  • the input stage In the event of a power failure the input stage is no longer able to maintain the DC bus voltage which therefore sags.
  • the battery control stage changes its mode of operation and maintains the DC bus constant at that 1.5% sag.
  • the output stage is not affected by such a small change in the DC bus voltage.
  • the battery maintenance stage has three modes of operation: battery charging, battery float and DC bus maintenance. These modes are compatible with each other and present no design difficulties. There is also a fourth mode - battery test-under-load, which will be discussed later.
  • the operation of the input stage will now be described since it may be operated with unity power factor.
  • the prototypes proved to have power factors of 0.98 or better.
  • the current through inductor Ll may be completely controlled at all times. If we arbitrarily choose a sign convention that the instantaneous current inwards through Ll is positive when it is floating, then the current into the inductor from the mains supply may be increased by switching on S2 and decreased by switching on S .
  • SI or S2 are complementary and may never be on together. In this way by instantaneous point on wave comparisons and switchings, die current through Ll may be controlled to have any desired waveform at all. Preferentially therefore it is chosen to be a sinewave current exactly in phase with the input phase voltage.
  • Figure 3 is a circuit outline showing power control means for a reversible rectifier responsive to both positive and negative bus voltages, and sensed current (Figures ⁇ 1 and 12 are practical embodiments of this Figure.)
  • the DC bus voltage is determined by differential amplifier Al to give an output which is used as the input to PI controller A2.
  • A2 is used to take the "proportional + integral" differences between the measured bus voltage (from Al) and the reference bus voltage as shown.
  • the output of A2 is the power demand signal which is multiplied with a sinewave reference voltage formed from the phase voltage V ⁇ (and scaled by the resistors Rl and R2) by the electronic multiplier Kl to give the current demand signal which is compared with the measured current signal I_SENSE using any of a number of well known current measurement techniques. If the sensed current is larger than the demand current IJDEMAND SI is switched on to reduce it and vice versa. In this way the input stage maintains unity power factor while maintaining the DC bus voltage constant
  • the fourth mode - the test-mode - of operation for the battery charger stage will now be introduced.
  • a special test-mode feature of the charger will allow the stage to act as though there is a total (full) power failure when none actually exists. In the preferred embodiment this is accomplished by altering the reference-bus voltage comparison relationship so that the controller for the battery-charger responds to a non-existent drop in bus voltage.
  • the battery charger will put full power into the DC bus system so that the DC bus voltage will rise.
  • the output of amplifier A2 in Figure 3 will reverse sign and die current demand signal will therefore be formed with the opposite sense. No change in logic is required - d e input stage will now transfer the excess power from the DC bus to the input mains supply.
  • This reversible rectifier and controller combination permits a novel feature important in a UPS: namely that it allows full 100% testing of the battery without disrupting the performance of the unit If a power failure should occur during this test it is a simple matter to disengage the test immediately - this is a function performed by the circuitry. As the output section of the system is presented only with a slightly raised bus voltage during this test it can carry on synthesising an AC output as at any other time.
  • the battery charger stage operates in a very simple way.
  • switches S3 and S4 generate a pulse width modulation (PWM)-like type of output to float the battery at the correct float voltage.
  • PWM pulse width modulation
  • the discharge mode of operation uses a circuit exactly the same as Figure 3 but with the bus reference reduced by 5% so that under normal circumstances the power demand from Amplifier A2 is always zero. Note that for the battery stage a negative output from A2 must be suppressed. Since the stage is a DC one no multiplier is required and the power demand may be used to control S3 and S4 directly by measuring the current in L2 and operating S3 and S4 to control the current according to the power demand signal.
  • the fourth mode of operation is preferably initiated by changing the bus reference voltage in the battery charger stage by (say) +10%.
  • the output stage operates in a very simple way.
  • An output voltage sinewave reference signal is generated; preferably by analogue conversion of digital, stored data. If the instantaneous output voltage is greater than the reference voltage, S6 is turned on; if it is smaller, S5 is turned on. Since the output is obtained through inductor L3 and capacitor C3 this mode of operation may be unstable without current feedback. Current feedback is easily obtained by measuring either the inductor current or the capacitor current and adding a small fraction of this signal to the measured output voltage.
  • the UPS is preferably controlled by a microprocessor and has appropriate user controls and displays. Apart from meters and lamps (eg LEDs) to provide warnings and show output volts and output current it is preferred that the UPS includes an LCD or other display capable of passing messages to die user. Communication po ⁇ s may also be provided to supply messages to the computer system receiving power from the UPS. Typically the computer system will be programmed to close files and shut down in an orderly fashion if the UPS signals that a power outage has occurred - the battery capacity will typically be specified to provide an uninterrupted power supply of sufficient duration to allow the designated computer system to shut down without malfunction.
  • a microprocessor Apart from meters and lamps (eg LEDs) to provide warnings and show output volts and output current it is preferred that the UPS includes an LCD or other display capable of passing messages to die user. Communication po ⁇ s may also be provided to supply messages to the computer system receiving power from the UPS.
  • the computer system will be programmed to close files and shut down in an orderly fashion if the UPS signals that a power outage has occurred
  • An autotransformer is employed at both input and output, to bring the working bus voltage by 12-15% from 230V RMS to a level compatible with practical capacitor units, and also to render the UPS capable of operating at different mains voltages in different environments. It is not necessary; it is cheaper than higher-voltage-rated bus capacitors. In some instances, full isolation may be provided by a transformer with separate primary and secondary windings.
  • Capacitor C4 serves to minimise reverse transmission of switching transients arising from the normal action of SI and S2.
  • the LEM device is used as a inductance current monitor for assistance in the control of SI and S2.
  • a LEM device is a type LT100 Hall-effect-based current sensor, accurate to 1% over 0-100 A, made by LEM SA, CH-1228, Geneva, Switzerland. The action of the reversible rectifiers connected to the positive and negative buses has been described with reference to Figure 2.
  • the capacitor C5 serves to effectively minimise ripple current in the battery supply lines, as excessive ripple is known to damage batteries.
  • the control functions of the UPS consists of three closed loops.
  • One loop endeavours to maintain the positive and negative buses at a certain voltage by drawing current from (or returning current to) the incoming mains supply
  • the second endeavours to maintain the buses by drawing battery current
  • the third section endeavours to maintain the UPS output at a predetermined level by drawing current from the buses.
  • Some of the interlinkage between these three loops is provided through a microcontroller, and some is provided by interconnections of analogue signals.
  • the user can force the battery to discharge into the incoming mains and diereby test the battery and the entire UPS under load.
  • the present UPS system consists of three main areas of circuit board. These are die Main Control Board (MCB), the Microprocessor board (consisting of 2 printed circuit boards) and die three driver boards - each containing a pair of the circuits of Figure 20.
  • MBC Die Main Control Board
  • Microprocessor board consisting of 2 printed circuit boards
  • driver boards die three driver boards - each containing a pair of the circuits of Figure 20.
  • FIG. 13 maps the control circuitry onto die centrally depicted set of six switches that comprises the core of the UPS, and complements Figure 4.
  • the boxes labelled DB contain pulse transformers and circuitry (see Figure 20) to drive die actual switches witii electrical isolation.
  • the input switches SI and S2, together with the inductor Ll and d e sensing and control circuitry in the blocks labelled 13, 14, 15, and 16, further revealed in Figures 13 to 16 comprise a reversible rectifier unit which endeavours to maintain the UPS buses at a certain DC voltage by either drawing current from, or returning it to die AC mains supply (mainly during battery tests) in a manner optimised to power utility requirements in that harmonic distortion (under 2%) or power factor effects (above 0.98) are minimal.
  • the battery switches S3 and S4 together with the circuits in Figures 6 to 10 and die inductor L2 comprise a second reversible rectifier unit which performs a DC to DC voltage translation function - not true rectification as such. Normally it is either charging the battery, or maintaining a float charge. If the bus voltages sag by more than 5% it is made to reverse-convert battery power into bus power, for that occurrence indicates that the incoming mains supply is now inadequate to maintain the buses. Furthermore, if the battery test mode is in effect it forces this reversible rectifier to dump power into the buses, which in turn forces the first reversible rectifier to dump d e bus power into the mains supply (so long as the mains is present).
  • the output switches S5 and S6 together with die inductor L3 and die circuits in Figures 11,12, and 17..19 comprise a further reversible rectifier unit which simply has to convert the DC of the buses into constant-value (voltage and frequency) AC according to instantaneous demand - which includes even repetitive charging peaks intrinsic to rectification into a capacitative load.
  • Figure 6 comprises logic circuitry to co-ordinate commands through the active-high Btest line with possible countermanding commands from the normally high Testinhib line - eg if the mains supply drops during a test
  • the digital signal Btest emanates from an external source (die microprocessor board, in response to an operator's command) and is filtered and limited by R78, CR24, R125 and C43 and then fed into U33.4; a Schmitt-input CMOS NAND gate. When Btest goes high the signal is inverted by U33.4 then passes via R167 and is again inverted by the simple inverter U38.4 then limited to 5V by R166 and CR21 (5V1).
  • This circuit comprises drivers for the pulse transformers for the power semiconductor switches SI to S6 of Figures 4 and 5. It includes (1) logic for the startup and inhibitory 75 functions, (2) inputs for 0.5 MHz and 1 MHz clocks, and (3) a PWM-like input to determine ON-times.
  • InhibitBC signal into the NAND gate U41.4 and the inverter U38.5 is low then transmission gates U65.1 and U65.2 will be enabled passing a 1MHz (off) signal to 0 both U62.1 and U62.2. If die InhibitBC signal is high tiien input PWMBC controls a 0.5MHz (on) signal to be fed to eidier D-type flipflop U62.1 according to die level of PWMBC.
  • Input signal PTE is involved widi startup. PTE is held high for about 2 seconds when 5 die circuit is powered up and from then on will always be low. If it is high then all outputs of U62 (dual D-type CMOS flipflops) are held low and die driver boards will not be powered. This enables the clock circuit to start operating before the FSK signals are sent to the pulse transformer drivers (ICL7667 - dual inverting power MOSFET drivers) which would be damaged by a DC signal. 0
  • High frequency FSK signals are fed into die D-type flip/flops (U62) via the clock input
  • the D input is connected to not-Q output so that a divide by 2 frequency division occurs.
  • the dual-frequency (now 0.5MHz 0.25MHz) waveform is divided by resistor pairs R120/R91 etc and supplied at TTL levels to the ICL7667 driver circuits.
  • the 5 waveform at input 'a' shall always be the complement of that at input 'b' for each 7667 when PTE is not enabled.
  • the ICL 7667 drivers are paired to provide extra drive - 18 -
  • This circuit effects the analogue control of the (+) and (-) battery voltages by taking the actual battery voltage as one input battery current as another input battery current flow commands as a third, plus a battery boost command, and emitting a type of PWM signal - actually a hysteretic control signal of non-stable frequency - for the purpose of reversible rectifier control.
  • the output is passed to Figure 7.
  • Resistors R202 and R203 reduce the battery voltage signal to compatible levels; protection diodes CR59/CR62 and CR60/CR61 respectively - low-power Schottky devices - are used to protect the amplifiers.
  • R200 and R196 widi the JFET quad operational amplifier U76.4 complete a summing circuit of the two battery terminal voltages Vb+ and Vb- at pin 6 of U76.2.
  • R195 provides a reference voltage opposite in polarity from the observed battery voltage which is also summed to pin 6 of U76.2.
  • U76.3 is a non-inverting buffer which is supplied with a battery voltage reference from the voltage divider R34/R169 which also allows the reference to be boosted via R124 by the microprocessor for boost charging of the battery to 2.33 volts per cell (VP .
  • Normal battery float voltage is 2.25 VPC for a 90 cell battery.
  • the output of U76.2 is the input to a frequency-restricted amplifier (with C18 and R31 in the feedback loop) which provides battery voltage float control (BATTV) at the preset reference.
  • Transmission switches U7.1 and U7.2 (FET analogue switch devices) select either the battery float voltage signal or a DC bus reference signal from page 5 depending on whetiier power is to be drawn from d e battery or returned to it Either duly selected voltage level is fed through R191 (battery float) or R175 (bus support) to the input of die PI controller U76.1 R190/C79.
  • the output is a battery current demand signal which is limited by CR45/CR14 at die characteristics of the LEM device to about 85A discharge and by the precision 0.9V reference (R194/R101/U75.3/CR46) to about 9A charge current.
  • This signal is buffered by U75.2 and passed via R172 to the PWM summing input 'SUM' - pin 2; the (-ve) input of U75.1.
  • Each LEM current sensor requires + and - 15 V supplies and a load resistance of 25 ohms; made up of 4 x 100 ohm resistors in parallel.
  • the battery inductor current is then amplified by U75.4 R105/R121 and passed through R174 to die point 'SUM * .
  • C34 (2.2 nanofarads) is provided to limit the minimum switching pulse width to about 4 microseconds thus reducing die effect of circuit noise.
  • the operational amplifier U75.1 produces a PWM type signal with about 2% hysteresis set by R77/R1 ⁇ 0 (47K/1K) which signal is level shifted by R170/R171 for subsequent logic circuits ( Figure 7) to pass to the transistor driver boards to the battery stage transistors.
  • the amplifier U75.1 will aim to control battery inductor current to the level specified by the signal Currentdemand within the 2% hysteresis limit Switch control is hysteretic and not at a fixed frequency like true PWM.
  • This circuit includes some of the overall control functions for the UPS. It will block the battery test mode if the bus voltage reaches more than 1.5% over the design value, and will disable all switches and contactors if the bus voltage is more than 10% high. It also commands reversible rectifier direction (via the RObat lines) for the battery as when the DC buses if tiiey become more than 1.5% low, and forms part of the battery test function.
  • Vdc(obs) the observed bus voltage
  • Vdc(ref) the reference bus voltage
  • Signals Vdc(obs) (the observed bus voltage) and Vdc(ref) (the reference bus voltage) are compared by the voltage divider R74/R75 R57 and if the bus voltage is or becomes more than 1.5% high, battery testing is stopped via U74.2/C35/CR40 using the line Testinhib. This is to prevent the input stage attempting to feed back into d e supply when the mains is absent
  • the same signals are similarly divided by R71/R72 R97 to provide a bus overvoltage signal BusOV which is fed to logic witi in Figure 17 via U74.3/C39/CR41 when the bus voltage is 10% high.
  • the switching transistors S1-S6 and contactors will all be disabled if this occurs.
  • Vdc(ref) is scaled by R129 R56/R73 to provide -1.5% and -3% reference voltages which are buffered by amplifiers type OP11 (U28.3 and U28.4) respectively.
  • the -1.5% reference is provided to detect when die observed bus voltage as buffered by U28.2 compared via R69 and R67 is 1.5% lower than die desired bus voltage. If this is the case, the battery charger is operated in battery support mode.
  • This signal is detected by U74.1 with 1% hysteresis fixed by the ratio of R186/R96 biased by 0.7% and filtered by C78. Biasing the signal by 0.7% means that the battery support voltage of the bus can be closer to the mains support voltage, improving performance.
  • the signal is level shifted (R160/R161) and made digitally compatible as 'Testinhib' for use by die circuit of Figure 6 by U31.4/U31 and finally limited to 5V levels by R159/CR20 andR158/CR19.
  • the -3% reference is summed to the observed bus voltage by R70/R68 and buffered by R55/U74.4 before being sent as DCBusref to Figure 8.
  • the bus is floated 3% low by die battery support stage.
  • R104/R187 and die FET switches/transmission gates U7.3/U7.4 form me battery test function. Normally the transmission gates will be conducting with a combined impedance of less than 50 ohms; negligible compared to R187 - 100K. When the battery test is activated, d e observed bus voltage is artificially divided by R104/R187 or by about 8% thus forcing the battery support mode to be entered. The battery will deliver maximum current into the bus and the regenerative rectifier input stage will regenerate into the mains (it has an independent DC bus reference).
  • This digital logic contributes to overall control, especially at startup. Power cannot be applied to a series string of reversible rectifier switches unless they are already activated in a complementary fashion so no direct patii exists through all erf diem. Thus, for instance, the battery may not be connected to an inactive UPS.
  • R176 and C42 provide a delay and reset pulse via U33.1 to the startup sequencing circuit U61.1/U61.2, made of a dual D-type flipflop.
  • CR44 is a protection diode for U33.1 on power down. When signal InhibitRR goes high the 1Hz clock circuit
  • Signal Shutdown resets the startup latches shutting down all transistors and disabling all contactors.
  • Signal -TXL inhibits all transistors.
  • Signal PWMBC is monitored by R164/C2 forming an RC delay line with U55.2 - the exclusive-NOR gate - a configuration which produces a pulse on every PWMBC transition (battery stage PWM signal). Every transition discharges C40 via the Q4/R99/R163 network. If a transition does not occur within approximately lmS, R188 will charge C40 up sufficiendy to produce a reset pulse on the output of U31.6. CR42 and R98 will limit the length of this pulse to lOuS.
  • tiiis circuit The purpose of tiiis circuit is to develop the PWM-like signals for hysteretic control of the output stage, and to be responsive to the output current, as detected by die LEM device, and also be responsive to the DC voltage in both buses.
  • Input LEMOP carries the output inductor current information. It is loaded by 25 ohms (R10-13; each 100 ohms) and amplified by U68.2/R103/R108 to give the output inductor current. This is fed via R27 to the summing point.
  • the signal labeled 190VACOP, which carries die input power sinewave signal, is fed via R43 to the same summing point CR56/CR57 protect the circuit from this high voltage signal.
  • R44/R45 provide a DC bus balance signal protected by CR55/CR56 which is integrated by U73.1/R47/C33 to form a bus-balance controller. This signal is fed via R185 to the summing point completing die current control signal.
  • U72.4/R51 sums and buffers the signal which is compared widi die signal SINEW via R154/R155 and supplied to die comparator input pin 9 of U72.3.
  • a small capacitor (2.2 nF) is added at d e comparator input to prevent high-frequency noise transients from causing erroneous switchings of the output transistors.
  • 1% hysteresis of the comparator is provided by R184/R95 and the signal is level shifted by R152/R153 before being supplied to driver board controlling logic as shown on Figure 12.
  • Figure 12
  • This circuit is for controlling the switches of the third, output reversible rectifier set S5 and S6. It is die same as that described as Figure 7; with different signal names and parts labels.
  • This circuit is for control of the input stage reversible rectifier (SI, and S2 of Figures 4 and 5, for example. It has to be kept in step widi the phase of the incoming mains.
  • Signal 190VACRR carries that information, and is attenuated and filtered by R46/R147/R193/C12 before passing into the 50Hz filter U71.2/R146/R145/CR35/R144/C11/U71.3 that is tuned by R39.
  • the filtered 50Hz sine wave is passed via R143 as one input to die analogue multiplier U20. (See Figure 3 for an overview of the process).
  • the input stage DCBusctrl signal is the otiier input to die multiplier.
  • the processed, reference 50Hz sine wave is multiplied by die bus control signal to produce a current demand signal which is supplied via R141 to die PWM- generating comparator U70.4.
  • the input current sensor is loaded widi 25 ohms by R6-R9 (actually 4 x 100-ohm resistors), amplified by U68.1/R102/R107 and added to a small amount of 90 degree phase shifted input sine wave reference by R178/R201 to provide compensation for the input capacitor power factor.
  • This signal is summed to die proportional bus balance signal DCbusbal tiien amplified by U71.1/R183 and compared to the current demand signal by R142/U70.4 widi 1% hysteresis supplied by R182/R79. Cl limits the minimum switching pulse to about 4 ⁇ S.
  • the input stage PWM signal PWMRR is level shifted by R139 R140 before being passing on to the driver board controlling circuitry ( Figure 14).
  • This circuit supervises DC bus voltage values.
  • R36 and R37 sum both the DC bus values to provide a balance signal which is protected by CR47/CR48 and filtered slighdy by C76/R33 before passing to Figure 13. See Figure 18, which serves to ensure that die bus voltages are balanced about d e central earth (neutral) value.
  • DC bus control signals are divided by R25 and R26 and protected by CR50/CR51 and CR47/CR48 respectively.
  • the positive bus voltage is summed to pin 6 of U70.2 by U70.3/R199/R198 and this signal is buffered by U70.2 and R197 to provide -Vdc(obs).
  • This signal is compared to a reference generated by R35/R54 within U70.1 which indicates to control logic when the bus has charged to a suitable voltage to bring in the main contactor.
  • This signal is level shifted to 15V/0V by R122/R134 and passed on to control logic within Figure 16.
  • the -Vdc(obs) signal is buffered by U69.4 and is compared to a reference generated by CR25/R106 buffered by U69.3 via R65/R66. This signal is supplied to pin 6 of U69.2 which forms a PI bus controller with R179/C13/C75. CR13/CR30 limit the magnitude of die current demand signal to 10V.
  • This signal (DCBUSctrl) is passed to the analogue multiplier in Figure 13 via R133.
  • R139/C41/CR33/U31.2 ensure that the dual D-flipflop circuits U58/U59 are reset on powerup.
  • R180/C36 form a delay circuit with CR34 as power-down protection.
  • the signal is clocked through U59.2 by a 1Hz clock circuit comprising U32.3/R181(330K)/C37 with CR32 power-down protection.
  • the action of pin 13 of U59.2 going high enables the driver board drive circuits via U36.3. This high level is then clocked through U59.1 to enable the soft-start contactor via R137/R206(10K)/Q3/CR15.
  • Signal TXL disables all contactors and transistors.
  • Signal Inputoff disables all input contactors and d e input transistors.
  • This circuit relates to overvoltage protection and is die 'central point' for a number of related alarm signals.
  • Signal OFF is provided widi impulse protection by R123/C74 and is diode-'OR'ed with the bus und ⁇ rvoltage/out of balance signals from Figure 18 before being limited by CR22 and filtered by C74.
  • a 100K resistor in parallel with C74 ensures that C74 discharges when d e OFF signal is inactive.
  • U31 inverts the signal to an active low state to shut down the UPS. The power transistors are shut down via U32.1 and U36.6. (TXL and -TXL).
  • the BusOV signal (active low) from Hgure 9 indicates tiiat die bus is in an overvoltage state so all transistors are shut down by U32.1 and U36.6.
  • TXL (transistor lockout) is active low.
  • This circuit is a recent modification attached to die version 2.0 UPS main controller board.
  • Vdc(obs) is compared to Vdc(ref) and if Vdc(obs) is seen to be 10% low U800.1 in conjunction widi a diode and capacitor will pass a high signal through a 10K resistor R813 to pin 6 of U801.1. If the battery contactor is enabled d e UPS is shut down via U802.1. This modification is intended to shut down die UPS if the bus has collapsed for any reason.
  • Two references are generated from the +/-15V supply and compared widi die bus balance signal by U800.2 and U800.3 with a small amount of hysteresis.
  • This circuit serves to create a shutdown signal Ilimit if the input signal IOobs indicates too high an output current
  • the output inductor current IOobs is passed through a half wave rectifier circuit R58/R64/CR29/CR28/U69.1 to provide a series of negative half cycles which are summed to die input signal IOobs/2 giving a full wave rectified magnitude of output current signal.
  • This signal is buffered at a set level by R38 U68 before being compared with a reference voltage generated by R59/R30.
  • a 2% hysteresis provided by R32.
  • the output is a current limit signal which is level shifted by R132/R126 before being passed on to Figure 17 where it shuts down die output stage transistors if the inductor current rises above a limit set by R38.
  • the driver board which is connected to the actual semiconductor switch and the semiconductor switch itself are shown in Figure 20.
  • the semiconductor switch is a 'FUJI* 2DI150Z-120 unit, rated at 150A, 1200V, and comprises two individual sections - say S 1 and S2, or S3 and S4, or S5 and S6 of Figure 2.
  • the associated circuitry as shown here is replicated 6 times in the entire UPS, and is driven by die circuits of Figures 7,12, and 14.
  • circuit elements which actually drive the semiconductor switches, float at a high voltage and are powered by rectifying and smoothing the control pulses received through the pulse transformer. These control pulses arrive continuously but at eidier 0.5 or 0.25 MHz; the frequency determines whether the switch is to be closed or open. High frequency means 'open' thus stray impulses cause a fail-safe condition.
  • the circuit comprises means to decode the information and drive the power transistor/switch while at the same time being powered by tiiose pulses.
  • a bridge rectifier plus a voltage doubler comprised of diodes Dl-4 and D13-14 respectively are connected to die secondary of die pulse transformer PT.
  • Pulsed data is coupled tiirough the resistor Rl to an exclusive-OR gate acting as a buffer and pulse shaper; then to a second exclusive-OR gate generating one pulse at each transition of die incoming data.
  • These pulses enter the 40193 counter, clocked by the crystal oscillator (XI etc).
  • Each pulse from the shaping circuit resets the 40193 counter (IC2).
  • die output Q3 goes high, and is connected to die 'D' pin of IC4 - a flipflop. This remains high for a further four clock pulses; the next shaped pulse clocks the 'high' or T tiirough to die 'Q' output (pin 1) of IC4 and resets IC2.
  • High-frequency pulses on the oti er hand, reset IC2 before it counts to the 'Q3 high' state. Also, an absence of pulses will cause IC5 to count freely until Q4 (pin 7) becomes set and d e main transistor is then turned OFF.
  • Pulses to drive die main transistor are inverted by the 6 sections of the 4049 in paral .
  • Q3 starts to conduct
  • Q2 starts to conduct also, thus Q2 and Q3 form a 'current source'.
  • the buffer chain removes any stored charge from Q4 to cause fast turn-off.
  • Q5 and Q4 form a current source at a current set by R14, to withdraw stored charge from the base region. Current is also dumped via C7 and R12 into the gate of Q4, turning it on.
  • the purpose of the multiple- buffer drive is to adequately drive die gate of Q4. Transient-current limiting is also provided, via the components at the top right of this circuit diagram.
  • the two LEDs serve for visual indication of normal or abnormal activity; both should be equally bright in normal operation.
  • the microprocessor board is an analog and digital interface board which monitors and controls the UPS main control board.
  • the present functions of the microprocessor board are:
  • the prototype units were proven to operate with an input voltage within 15% of the rated value, a frequency within 10% of the rated value, a power factor of better than 0.98, a smooth 'walk-in' over 10 seconds (for generator compatibility) and a maximum current of 60A. Battery voltage was 204V.
  • the output was measured at 230VAC, with a 1% frequency variation and a maximum slew rate of 1 cycle per second.
  • the power rating of 10 kW was maintained.
  • Steady state voltage regulation was 1%, was within 10% for an 0-100% step, and was within 3% at the second cycle.
  • the output waveform had an approximately 3% total harmonic distortion.
  • the efficiency was measured at 87% from input to output; and die maximum heat dissipation (loss) was 1500W.
  • the UPS is preferably controlled by a microprocessor and has appropriate user controls and displays.
  • Panel controls include means to start up and shut down die UPS, means to initiate a battery test, means (using the microprocessor) to evaluate the battery condition from the droop of voltage during d e test For emergency shutdown a pair of buttons which must be pressed simultaneously are provided.
  • die UPS includes a character-based liquid-crystal or other display device capable of displaying messages to the user. Communication ports may also be provided to supply messages to the computer system receiving power from the UPS.
  • the computer system will be programmed to close files and shut down in an orderly fashion if the UPS signals that a power outage has occurred - die battery capacity will typically be specified to provide an uninterrupted power supply of sufficient duration to allow the designated computer system to shut down without malfunction.
  • a feature of the UPS shown in Figure 2 is that die neutral may be continuous tiirough the system (if so required). Alternatively the neutral can be isolated by suitable transformers. Input and output voltages may be transformer coupled as shown in Figure 1 but with the continuous neutral these transformers may be low cost auto- transformers. The inputs and outputs may be different frequencies and different voltages widiout restraint while leaving the internal working of the UPS unaffected.
  • the regenerative rectifier permits the UPS to draw a unity power factor current from the reticulation network with very low distortion, while at the same time highly non-linear loads can exist at the UPS output
  • This invention can be used for different capacity UPSs.
  • a prototype lOkW UPS having an input and output voltage of nominal 230 volts single phase AC, with a full load of 50 amps at nominal input voltage.
  • This has a bus voltage of 700 volts DC suppled from the input or from a nominal 90 cell lead acid battery having an output of 203 to 157 volts (between 2.25 volts per cell at float voltage down to 1.75 volts per cell at the end of d e discharge cycle).
  • Such a battery is preferably configured as a lOkW 10 minute battery to enable the computer system to be automatically shut down during power outage.

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  • Business, Economics & Management (AREA)
  • Emergency Management (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)
  • Stand-By Power Supply Arrangements (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Electrical Discharge Machining, Electrochemical Machining, And Combined Machining (AREA)
  • Rectifiers (AREA)

Abstract

L'invention concerne un appareil d'alimentation en courant pouvant être configuré comme un filtre de ligne d'alimentation, ou une alimentation ininterrompue en courant dotée d'une fonction de test de batteries en charge. Il comprend un redresseur d'entrée réversible (L1, S1, S2), pouvant être connecté entre une alimentation en courant alternatif et un bus de courant continu intérieur de haute tension, un second redresseur réversible (L2, S3, S4) interconnectant des batteries de stockage (B1) au bus de courant continu à haute tension, et un module de sortie (L3, S5, S6) délivrant une sortie de courant continu ou une sortie de courant alternatif désiré. En utilisation, la tension se trouvant dans le bus de courant continu intérieur est maintenue à un niveau supérieur à celui de (a) la crête répétitive instantanée de la tension entrante et (b) la tension de crête de stockage de la batterie. Un moyen de test des batteries consiste à permettre la décharge de la charge stockée dans les batteries de stockage, pendant une période de temps donnée à la vitesse disponible maximum, dans le bus intérieur et en retour dans l'alimentation en courant alternatif, par l'intermédiaire desdits redresseurs réversibles, tout en contrôlant l'ampleur de la chute de tension des batteries ainsi provoquée.
PCT/GB1990/000958 1989-06-21 1990-06-21 Alimentations ininterrompues en courant WO1990016105A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NZ229639 1989-06-21
NZ22963989A NZ229639A (en) 1989-06-21 1989-06-21 Uninterruptible power supply: full-load battery test by discharging into ac supply

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WO1990016105A1 true WO1990016105A1 (fr) 1990-12-27

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2310089A (en) * 1996-02-08 1997-08-13 Nokia Telecommunications Oy Battery charging; back-up power supply
GB2313721A (en) * 1996-05-31 1997-12-03 Fujitsu Ltd Battery charging; backup power supply
RU2521086C2 (ru) * 2008-12-10 2014-06-27 Шнайдер Электрик Айти Корпорейшн Способ и устройство управления выходным сигналом, подлежащим достаке в нагрузку, и система бесперебойного питания
WO2016019982A1 (fr) * 2014-08-05 2016-02-11 Vega Grieshaber Kg Dispositif de connexion et procédé de connexion
WO2018096563A1 (fr) * 2016-11-23 2018-05-31 Sedemac Mechatronics Pvt Ltd Système de régulation de puissance électrique générée par une machine à aimant permanent
CN111030285A (zh) * 2019-12-20 2020-04-17 科华恒盛股份有限公司 不间断电源的锁相实现方法及终端设备

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2111326A (en) * 1981-12-01 1983-06-29 Chloride Group Ltd No-break power supply
US4709318A (en) * 1986-10-22 1987-11-24 Liebert Corporation UPS apparatus with control protocols
WO1989001719A1 (fr) * 1987-08-21 1989-02-23 Electronic Research Group, Inc. Alimentation integree ininterrompue pour ordinateurs personnels

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2111326A (en) * 1981-12-01 1983-06-29 Chloride Group Ltd No-break power supply
US4709318A (en) * 1986-10-22 1987-11-24 Liebert Corporation UPS apparatus with control protocols
WO1989001719A1 (fr) * 1987-08-21 1989-02-23 Electronic Research Group, Inc. Alimentation integree ininterrompue pour ordinateurs personnels

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
IEEE PROCEEDINGS vol. 136, no. 3, May 1989, pages 113 - 120; A.W.GREEN: "Hysteresis current-forced three-phase voltage-sourced reversible rectifier" see the whole document (cited in the application) *
IEEE PROCEEDINGS vol. 136, no. 5, September 1989, pages 205 - 211; J.T BOYS - A.W. GREEN: "Current-forced single-phase reversible rectifier" see the whole document (cited in the application) *
INTELEC 87 17 June 1987, STOCKHOLM pages 163 - 168; G.ANDERSON - S.RATHMAN: "Future powersupplies having built-in battery back up" see the whole document *
INTELEC 87 17 June 1987, STOCKHOLM pages 521 - 524; F.BARZEGAR - M.J.MODEL: "A novel AC uninterruptible power supply" see the whole document *

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2310089A (en) * 1996-02-08 1997-08-13 Nokia Telecommunications Oy Battery charging; back-up power supply
GB2313721A (en) * 1996-05-31 1997-12-03 Fujitsu Ltd Battery charging; backup power supply
US5898234A (en) * 1996-05-31 1999-04-27 Fujitsu Limited Power supply unit with simplified circuitry
GB2313721B (en) * 1996-05-31 2000-11-08 Fujitsu Ltd Power supply unit with simplified circuitry
RU2521086C2 (ru) * 2008-12-10 2014-06-27 Шнайдер Электрик Айти Корпорейшн Способ и устройство управления выходным сигналом, подлежащим достаке в нагрузку, и система бесперебойного питания
WO2016019982A1 (fr) * 2014-08-05 2016-02-11 Vega Grieshaber Kg Dispositif de connexion et procédé de connexion
US10581268B2 (en) 2014-08-05 2020-03-03 Vega Grieshaber Kg Connecting device and method for connecting
WO2018096563A1 (fr) * 2016-11-23 2018-05-31 Sedemac Mechatronics Pvt Ltd Système de régulation de puissance électrique générée par une machine à aimant permanent
US11190118B2 (en) 2016-11-23 2021-11-30 Sedemac Mechatronics Pvt Ltd System for controlling electrical power generated by a permanent magnet machine
CN111030285A (zh) * 2019-12-20 2020-04-17 科华恒盛股份有限公司 不间断电源的锁相实现方法及终端设备

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AU636364B2 (en) 1993-04-29
NZ229639A (en) 1993-03-26

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