WO1990013957A1 - Architecture modulaire pour tres larges commutateurs par paquets - Google Patents

Architecture modulaire pour tres larges commutateurs par paquets Download PDF

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Publication number
WO1990013957A1
WO1990013957A1 PCT/US1989/005849 US8905849W WO9013957A1 WO 1990013957 A1 WO1990013957 A1 WO 1990013957A1 US 8905849 W US8905849 W US 8905849W WO 9013957 A1 WO9013957 A1 WO 9013957A1
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WO
WIPO (PCT)
Prior art keywords
switch
packet
modules
outputt
packet switch
Prior art date
Application number
PCT/US1989/005849
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English (en)
Inventor
Tony Tong Lee
Original Assignee
Bell Communications Research, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bell Communications Research, Inc. filed Critical Bell Communications Research, Inc.
Publication of WO1990013957A1 publication Critical patent/WO1990013957A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • H04L49/1507—Distribute and route fabrics, e.g. sorting-routing or Batcher-Banyan
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5672—Multiplexing, e.g. coding, scrambling
    • H04L2012/5674—Synchronisation, timing recovery or alignment
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • H04L49/1515—Non-blocking multistage, e.g. Clos
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/20—Support for services
    • H04L49/205—Quality of Service based
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/35—Switches specially adapted for specific applications
    • H04L49/356—Switches specially adapted for specific applications for storage area networks
    • H04L49/357—Fibre channel switches
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/45—Arrangements for providing or supporting expansion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/55—Prevention, detection or correction of errors
    • H04L49/557—Error correction, e.g. fault recovery or fault tolerance

Definitions

  • the present invention relates to a packet switch and, more particularly, to a modular architecture for a very large packet switch.
  • a packet switching network comprises an array of packet switches interconnected by trunks.
  • a packet switch comprises a set of inputs which receive arriving packets via a set of incoming trunks and a set of outputs which are connected to a set of outgoing trunks via which packets depart the switch.
  • the inputs and outputs are connected by a switch fabric.
  • the switch fabric is a self-routing switch fabric.
  • a self-routing switch fabric typically comprises an array of nodes organized into stages. At each node routing decisions are made based on an address contained in the header of the packet being routed.
  • Such self -routing networks are synchronous so that packets arrive simultaneously at the inputs in intervals of time known as time slots.
  • a banyan network is a self-routing network which can route a packet from any input to any output based on an address contained in the packet header.
  • the banyan network suffers from internal packet collisions.
  • the packets in any time slot are presented to the inputs of the banyan network in increasing or decreasing order according to destination address.
  • the packets received at the inputs to the banyan network should be concentrated, i.e., there should be no inactive input lines to the banyan network in between active input lines to the banyan network in any particular time slot.
  • the banyan network is usually preceded by a Batcher network which sorts arriving packets according to destination address. The sorted packets are then routed to the desired outputs as indicated by their addresses by the banyan network.
  • the combined Batcher-banyan network provides a full connection, internally collisionless switch fabric.
  • a concentrator network may be located between the Batcher network and the banyan network.
  • the Batcher outputs and the banyan inputs are connected with a pattern known as a perfect shuffle.
  • a perfect shuffle For a situation where there are 64 interconnections between the Batcher network and the banyan network. Assume the Batcher outputs are numbered 1 to 64 and that the banyan inputs are also numbered 1 to 64. The first half of the Batcher outputs (1-32) are connected to the odd numbered banyan inputs 1,3...63. The second half of the Batcher outputs (33-64) are connected to the even numbered banyan inputs 2,4...64. This is like a perfect shuffle of the two halves of a deck of playing cards.
  • switch fabrics based on the Batcher-banyan network do not suffer from internal collisions, they do suffer from external collisions.
  • An external collision occurs when two or more packets destined for the same output are simultaneously presented at the inputs of the Batcher-banyan network.
  • Recirculation Algorithm This algorithm feeds blocked packets back to the inputs for re-entry at the next time slot. (See e.g., Huang, A. and Knauer, S., Starlite: A Wideband Digital Switch, Proceeding of Globecom 84, pp. 121-125).
  • This algorithm is also a feedback scheme. Each input sends a probing header for arbitration in phase 1. The inputs then receive a positive or negative acknowledgement back from the outputs in phase 2. The actual transmission of the winning packets, i.e., those who receive positive acknowledgements, takes place in phase 3.
  • Ring Reservation Algorithm This is a token passing scheme. At the beginning of a time slot, a clear token is issued by a token generator. The token has an N-bit field to indicate the availability of each of N outputs. The token is circulated around a ring connecting input ports associated with each of the packet switch inputs.
  • the packet at the head of a queue at the particular input port will make a reservation by writing a logic "1" into the bit position of the token corresponding to the desired output, if the desired output has not been reserved by a previous input port on the ring. If the intended output is successfully reserved, the packet is transmitted during the next time slot.
  • the reservation cycle and transmission cycle can be overlapped to minimize the overhead.
  • Batcher-banyan switch fabric requires that the whole set of input packets (i.e. the set of packets arriving at the inputs of the switch fabric during one time slot) be synchronized at every stage of the switch fabric. For a switch with 10,000 inputs, this means synchronizing up to 10,000 packets within a network of about 100 stages.
  • a second problem with a very large packet switch is the physical limitations on the size of the VLSI chips and the complexity of the interconnection wiring between the chips.
  • a third problem with very large packet switches relates to reliability and maintainability. It is clear that smaller switch fabrics ar easier to develop, to test, to maintain, and to replace.
  • each Batcher-banyan module in one stage is connected to each Batcher-banyan module in the next stage.
  • This provides full interconnectivity between all the inputs and all the outputs of the very large packet switch.
  • the packets in order for packets arriving at the switch in a particular time slot to be routed from particular inputs to particular outputs, the packets must pass through a plurality of the relatively small Batcher-banyan modules in a plurality of stages.
  • this type of modular architecture it is possible to independently synchronize the individual Batcher- banyan modules only if buffer* are utilized between the stages. Without such buffers all of the modules have to be globally synchronized.
  • the conventional modular architecture described above requires complex interconnections between the stages of Batcher-banyan modules.
  • a packet switch having N inputs and N outputs may be implemented using K (1 ⁇ K ⁇ N) relatively small switch modules.
  • Each subset of M inputs is connected to all N outputs using one of the K switch modules. More particularly, each switch module has M inputs and N outpuu.
  • the j ⁇ output of each module is connected to a multiplexer, which multiplexer is connected to the j A output of the packet switch.
  • the switch module is the basic building block of the NxN packet switch according to the present invention.
  • Each of the switch modules is an autonomous, non-blocking, self-routing packet switch.
  • each switch module comprises a Batcher sorting subnetwork and an expansion routing network.
  • the expansion routing network comprises a set of binary tree subnetworks interconnected with a set of banyan subnetworks.
  • a packet is routed from a particular input to a particular output, through use of only one switch module. There are no interconnections between modules, and the modules operate independently of each other.
  • the inventive packet switch architecture allows for the independent synchronization of the modules which simplifies timing substantially.
  • the relatively small size of each switch module makes synchronization within each module relative straightforward.
  • the packet switch of the present invention it is an advantage of the packet switch of the present invention that contention resolution algorithms developed for Batcher-banyan switches, such as the Recirculation Algorithm, Three-Phase Algorithm, and Ring Reservation Algorithm, remain valid for the individual switch modules.
  • the Ring Reservation Algorithm is an attractive contention resolution algorithm for the switch modules because a separate ring is used for each switch module, thereby converting an otherwise serial procedure into a parallel procedure.
  • a further advantage of the packet switch architecture of the present invention is that any fault in a module will disturb only the local traffic carried by that module, while the remaining switch modules can still be normally operated. Fault tolerance can therefore be accomplished by providing a spare module, not a duplication of the entire switch. It should also be noted that because the packet switch of the present invention is constructed utilizing independent switch modules, the capacity of the packet switch can be distributed over a rural exchange area to reduce access costs.
  • the modular packet switch architecture of the present invention represents a significant advance over conventional modular packet switch architectures especially for the implementation of very large packet switches.
  • FIG. 1 schematically illustrates a very large packet switch comprising N inputs and N outputs.
  • FIG. 2 schematically illustrates a conventional modular implementation of the switch of FIG. 1.
  • FIG. 3 schematically illustrates a modular implementation of the switch of FIG. 1, in accordance with an illustrative embodiment of the present invention.
  • FIG. 4 schematically illustrates how a plurality of switch modules of the type shown in FIG. 3 are interconnected in three dimensions to form the switch of FIG. 3.
  • FIG. 5 schematically illustrates an expansion network for use in the packet switch modules of FIG. 3 and FIG. 4.
  • FIG. 6 is a table which summarizes the properties of the subnetworks comprising a switch module.
  • FIG. 7 schematically illustrates an alternative modular packet switch, in accordance with an alternative embodiment of the present invention.
  • FIG. 8 illustrates, by way of flow chart, a ring reservation contention resolution algorithm for use in connection with the packet switch of FIG. 7, in accordance with an illustrative embodiment of the invention.
  • Subsection A describes a conventional packet switch architecture.
  • Subsection B presents an overview of a modular packet switch architecture according to the present invention.
  • Subsection C describes in detail the packet switch modules of the present invention.
  • Subsection D describes contention resolution and output space extension for the packet switch modules of the present invention.
  • the switch 10 comprises a non- blocking, self-routing switch fabric 20.
  • the switch fabric 20 may be a Batcher-banyan switch fabric.
  • Packets arrive at the packet switch 10 via the high speed fiber optic input trunks 22.
  • Each of the fiber optic input trunks 22 is connected to a demultiplexer 23.
  • Each demultiplexer 23 demultiplexes the stream of packets arriving on the corresponding fiber optic trunk 22 into a plurality of packet streams on the input lines 24 because the electronic switch fabric 20 operates at a slower speed than the optical fiber input trunks 22.
  • the switch fabric 20 has N inputs 25 and N outputs 26 so that there are N input lines 24 leading to the switch fabric 20. There are also N output lines 27 leaving the switch fabric. Typically, N is on the order of 10,000.
  • the switch fabric 20 serves to route each packet arriving via an input line 24 to a particular output line 27 based on an address contained in the packet header. If the switch fabric 20 is a Batcher-banyan network, then the switch fabric 20 is synchronous and the packets are routed through the switch fabric in time slots. The packets leaving the switch fabric 20 via the lines 27 are multiplexed using the multiplexers
  • switch fabric 20 is a Batcher-banyan network
  • the contention resolution mechanism may involve use of the Recirculation, Ring Reservation, or Three-Phase algorithms mentioned above.
  • FIG. 2 schematically illustrates a conventional approach for modularizing the switch fabric 20 of FIG. 1.
  • the switch fabric 20 is formed from a plurality of Batcher-banyan modules 30.
  • the modules 30 are organized into stages
  • Each module 30 includes a Batcher network and a banyan network.
  • each Batcher-banyan module 30 has 256 inputs and 256 outputs.
  • One output from each of the modules 30 in stage 31-1 is connected to each of the modules in the stage 31-2.
  • the switch fabric of FIG. 2 provides full connectivity, i.e. a packet arriving at a particular input of a module in stage 31-1 can be routed to any output of any module in stage 31-2.
  • the switch fabric of FIG. 2 has a number of significant disadvantages. Firstly, for a packet to be routed from an input of the switch fabric to an output, it must pass through modules located in a plurality of stages. Thus, the individual modules 30 can be synchronized independently only if buffers are located between the stages. Secondly, the architecture of FIG. 2 requires a complex interconnection pattern between the Batcher-banyan modules of two adjacent stages. Thirdly, because packets are transmitted from particular inputs to particular outputs via a plurality of modules located in a plurality of stages, if one module fails, the entire switch fabric may not operate properly. A further disadvantage of the architecture of FIG.
  • FIG. 2 is that contention between packets containing conflicting output addresses cannot be resolved independently for each module, thereby making overall contention resolution for the switch fabric quite complicated. For these reasons, the modular architecture of FIG. 2 has a limited throughput and is not suitable for implementation of a very large packet switch having on the order of 10,000 inputs and 10,000 outputs.
  • a switch fabric 20' in accordance with an illustrative embodiment of the present invention is shown in FIG. 3.
  • the switch fabric 20' has N inputs 41 and N outputs 42.
  • the N inputs 41 are divided into K subsets 47 of M inputs each.
  • the first subset 47 of inputs 41 includes inputs 1 VietnameseM
  • the K A subset 47 of inpuu 41 includes inputs M(K-1)+1,....,MK where M -N.
  • the switch module 20* comprises a plurality of modules 40.
  • Each subset 47 of M inpuU 41 forms the set of inpuu for one of the switch modules 40.
  • each switch module 40 has M inpuu.
  • Each module 40 has N outputt 43.
  • the module outputt 43 with the same address, one from each module 40, are multiplexed together using the multiplexers 44 and fed to the output 42 bearing that address. It is a highly desirable feature of the present invention that each module 40 is an autonomous, non- blocking, self -routing packet switch network.
  • FIG. 4 A three-dimensional implementation of the architecture of FIG. 3 is shown in FIG. 4.
  • the switch fabric 20* comprises a plurality of modules 40, each of which is implemented by combining a plurality of subnetworks in three dimensions.
  • Each module 40 of FIG. 4 comprises a Batcher sorting subnetwork
  • the Batcher subnetwork 51 comprises an array of nodes 58 which are organized into stages 59.
  • the expansion network 52 comprises a set of binary tree subnetworks 53 and a set of banyan subnetworks 54.
  • the binary tree subnetworks 53 comprise the nodes 60 and are stacked vertically.
  • the banyan subnetworks 54 comprise the nodes 61 and are stacked horizontally.
  • the multiplexers 44 (see FIG.3) are arranged in sett of four, which sett of four multiplexers are stacked vertically.
  • the outputs of the banyan subnetworks 54 form the module outpuu 43 (see FIG. 3).
  • the outpuu 43 with the same address, one from each switch module 40 are multiplexed together by means of a multiplexer 44 and connected to the corresponding output 42.
  • the modules 40 of FIG. 3 and 4 operate as follows. As shown in
  • a set of N packett arriving at the inpuu 41 in a particular time slot is partitioned into K subsett of M packett each so that each module 40 receives a subset of up to M packets at its inputt.
  • the subset of packett arriving at the M inputs of a module 40 are sorted by the Batcher subnetwork 51.
  • the sorted subset is then partitioned again into sub-subsets by the binary tree subnetworks 53.
  • the ordered packeu of these sub-subsets are routed concurrently to their destinations by the banyan sub-networks 54.
  • the multiplexers 44 collect the packett from the banyan outputt 43 and route them to the packet switch outputt 42.
  • the modules 40 are not interconnected with each other. It is only after processing by the modules 40, that packett leaving the modules 40 are multiplexed together. In other words, the modules 40 operate independently of each other. This means that each module 40 can be synchronized independently. It is only necessary to synchronize with each other the M packett which propagate through a module 40 in a given time slot rather than all N packett which may arrive at all the modules in a given time slot.
  • FIG. 2 no complex pattern of interconnections exists between groups of modules.
  • a further advantage of the inventive modular architecture of FIG. 3 and 4 is that a packet which is routed from a particular packet switch input 41 to a particular packet switch output 42, only passes through one switch module 40. Thus, if one switch module 40 fails to operate, the remainder of the modules 40 will continue to operate properly. Fault tolerance can be accomplished by providing a spare module not a duplication of the entire switch.
  • the conventional modular packet switch architecture comprises a complex arrangement of interconnected Batcher-banyan modules, if one module fails, the whole switch may fail to operate properly.
  • Another advantage of the inventive packet switch architecture is that contention resolution can be carried out for each module 40 separately.
  • the modules 40 can be spread over a rural exchange area to reduce access costs.
  • a switch module 40 (see FIG. 3 and 4) including a Batcher subnetwork 51 and an expansion network 52 is shown in more detail in FIG. 5.
  • An expansion network is a network with more outputt than inputt.
  • the module 40 comprises an expansion network 52 having n»4 stages (labeled 1,2,3,4 in FIG. 5).
  • each of the binary tree networks 53 has one input and K-4 outpuu.
  • Each binary tree network 53 of FIG. 5 has k->*log__ logN-logM»logl6-log4 «m-n ⁇ 4-2 stages.
  • each banyan subnetwork is an MxM network having m stages.
  • each banyan subnetwork 54 is a 4x4 network having two stages.
  • Every node 60 in a binary tree subnetwork 53 is a 1x2 switch element capable of performing a binary routing algorithm based on an n-bit destination address in the header of a packet to be routed. That is, a node at stage j (as labeled in
  • FIG. 5 sends an arriving packet out on the upper output link (link 0) or the lower output link (link 1) according to the j** bit of the packet header.
  • every node 61 in a banyan network 54 is a 2x2 switch element which performs the same binary routing algorithm.
  • a packet arriving on one of the two input links of a node 61 in the stage j is routed to the upper output link (0) or the lower output link (link 1) according to the j A bit of an n- bit packet header.
  • the outputt of a binary tree subnetwork can be labeled by two binary numbers (x,y) * (x ⁇ ...jc m y ⁇ ...y - m - k ) where is the top down numbering of the binary tree sub-network and y 1 ....y Jt is the local address of each output within its binary tree.
  • the binary tree outputs are labeled with the appropriate binary numbers in FIG. 5.
  • the inputs of the banyan subnetworks can also be identified by two binary numbers (a,b) ( ⁇ _ ⁇ ....__horizon.. constitute,_*, b ⁇ ....b m ) where a x ....a H - m is the top down numbering of the banyan subnetworks and b ⁇ ...b n is the local address of the input within its banyan subnetwork.
  • the banyan inpuu are labeled with the appropriate binary numbers in FIG. 5.
  • the binary tree output 01,10 of FIG. 5 is connected to the banyan input 10,01.
  • This interconnection pattern is easily realized in three dimensions as shown in FIG. 3 wherein the binary tree subnetworks 53 are stacked vertically and the banyan subnetworks 54 are stacked horizontally.
  • a Batcher subnetwork 51 sorts the subset of packett incident on that module in a particular time slot according to destination address.
  • the cross-interconnection pattern between the binary tree and banyan subnetworks described above insures that packett arrive at the banyan subnetworks 54 of a switch module 40 ordered according to destination address so that no internal collisions take place in the banyan subnetworks.
  • the non-blocking property of the expansion network 52 may be stated another way. If the set of destination addresses of input packett to an expansion network is monotone and concentrated, then so is every subset of input packett to each banyan subnetwork of the expansion network. Consequently, a non- blocking, self -routing packet switch with more outputt than inputt may be formed by combining a Batcher sorting network and an expansion network in the manner described above.
  • a switch module 52 may include a concentrator network (not shown) located between the Batcher sorting subnetwork 51 and the expansion network 52.
  • FIG. 6 summarizes the properties of a switch module forming part of an NxN packet switch.
  • the packet switch comprises K switch modules, with each module having M»N/K inputs and N outputt.
  • such a switch module comprises a Batcher subnetwork, a set of binary tree subnetworks and a set of banyan subnetworks.
  • FIG. 6 indicates the number of each type of network in the switch module, the dimensions of each network in the switch module, the number of stages of each network in the switch module, and the number of nodes of each network in the switch module.
  • Knockout Switch A Simple Modular Architecture for High Performance Packet Switching", IEEE Journal on Selected Areas in Communications, Vol. SAC-5, No. 8,
  • each input is connected to every output by a broadcast bus.
  • a bus interface at each output provides packet filters for allowing packett addressed to that output to pass and for blocking all others. If each module of the packet switch of the present switch has M- l inputt, then the switch of the present invention is equivalent to a knockout switch.
  • each binary tree subnetwork 33 carries at most one packet during a time slot. Therefore synchronization is unnecessary for the binary tree networks.
  • the multiplexers 44 (see FIG. 3 and 4), operating asynchronously, are able to collect packett coming from different banyan subnetworks 53 at different instantt of time.
  • each banyan subnetwork 53 can be synchronized independently without global synchronization.
  • the individual switch modules used to form an NxN packet switch are not MxN modules as described above but are instead MxNP modules.
  • Such a module has only N distinct output addresses, but at each of the N addresses there are P outlets which allow up to P packett to be switched concurrently to the same one of the N output addresses.
  • FIG. 7 illustrates a packet switch 100 which utilizes output address extension and a recirculation algorithm for contention resolution.
  • the switch 100 of FIG. 7 has N inputt 102 and N outputs 104.
  • the N inputs 102 are divided into K sett 103 of M inputt each.
  • the first set 103 of inputt 102 includes the inputt 1...M
  • the K A set 103 of inputt 102 includes the inpuu M(K-1)+ 1...MK.
  • Each set of M inputt 102 is associated with a packet switch module 106.
  • each module 106 comprises a Batcher network and an expansion network.
  • Each module 106 has M inputt 108 which are associated with one of the K sett 103 of M inputt 102 described above.
  • Each module 106 has NP outputt 110. More particularly, each module 106 has N distinct output addresses 1...N and P outputt 110 associated with each output address. The outputt 110 with the same address from each module 106 are multiplexed together by the multiplexers 112 and fed to the packet switch output 104 bearing that address.
  • An input port 114 is associated with each of the inputt 108 of the switch module 106.
  • each input port 114 includes a queue (not shown) of packett waiting for service by that particular input.
  • the input portt 114 associated with each switch module 106 are connected into a ring 116.
  • Each ring 116 includes a token generator (TG) 118.
  • the token generator 118 on each ring 116 issues a token at the beginning of each time slot.
  • Each token is passed around the appropriate ring sequentially from input port to input port.
  • the tokens are used by the input ports 114 to reserve outputt of the corresponding switch module 106 for the packett at the head of the associated queues.
  • the tokens are used in conjunction with a ring reservation algorithm which is executed at the input portt 114 to reserve outputt for particular packeu.
  • a packet header 200 includes an n-bit destination address D.
  • the destination address D indicates a group of P outputt.
  • the packet header also includes a priority field S.
  • a p-bit group index is determined by the ring reservation algorithm discussed below so that the packet is routed to a specific one of the outputt having the destination D.
  • a token 202 also comprises two fields.
  • each subfield Gj indicates the number of inputt which previously reserved the set of outputs j.
  • the reservation cycle is divided into Q subcycles, where Q is the number of packet priority classes.
  • a token will circulate around iu ring from input port to input port Q times.
  • i A subcycle only packett in the i A priority class can make a reservation for an output.
  • n-bit destination address in a packet header at a particular input port is D » (rf ll ...._f l ) 2 * » (A) l o, wherein d n ....d x is the binary representation of the n-bit destination address D and h is the decimal representation of the address D (box 204, FIG. 8).
  • the subfield G* of the token may be represented as (box 204, FIG. 8).
  • the token is simply passed to the next input port (Box 208, FIG. 8).
  • the losing packet has to wait for the next reservation cycle, possibly with a higher priority class by modification of its priority field.
  • the token generator will increase the priority field of the token by 1 to commence the next subcycle.
  • packett winning the contention resolution process which takes place during a particular time slot are transmitted through the switch module to the appropriate outputt during the next subsequent time slot.
  • the ring reservation algorithm described above in connection with FIG. 8 is particularly advantageous for use in with a modular switch architecture such as that shown in FIG. 8 because the ring reservation algorithm may be carried out independently for each switch module.
  • switch modules the building blocks of the packet switch, are themselves independently operated packet switches of relatively small size.
  • Each module comprises a Batcher sorting subnetwork, a set of binary tree subnetworks, and a set of banyan subnetworks. Because each of the switch modules - operates independently, operation and maintenance of the whole switch is significantly simplified. For building very large packet switches, it is a particular advantage of the inventive architecture that each of the switch modules can be synchronized independently.

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Abstract

Une architecture modulaire pour très larges commutateurs par paquets comprend des module (40) dont chacun est formé d'un sous-réseau Batcher (51) et d'un réseau (52) d'acheminement par expansion. Le réseau d'acheminement par expansion comprend un ensemble de sous-réseaux (53) à arbres binaires interconnecté avec un ensemble de sous-réseaux (54) en arbre banian. Un paquet peut être acheminé d'une entrée du commutateur à n'importe quelle sortie au moyen d'un seul module commutateur. Les modules commutateurs peuvent ainsi être synchronisés indépendamment les uns des autres et en cas de défaillance d'un module, les autres modules peuvent continuer à acheminer des paquets.
PCT/US1989/005849 1989-05-02 1989-12-28 Architecture modulaire pour tres larges commutateurs par paquets WO1990013957A1 (fr)

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EP0549053A1 (fr) * 1991-12-23 1993-06-30 Philips Communication D'entreprise Dispositif de commutation de données

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EP0292962A2 (fr) * 1987-05-26 1988-11-30 Fujitsu Limited Système de commutation de paquets dirigés par un en-tête
EP0312628A1 (fr) * 1987-10-20 1989-04-26 International Business Machines Corporation Dispositif modulaire de commutation à grande vitesse pour le trafic en mode circuit et paquet

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EP0549053A1 (fr) * 1991-12-23 1993-06-30 Philips Communication D'entreprise Dispositif de commutation de données
US5377180A (en) * 1991-12-23 1994-12-27 U.S. Philips Corporation Data switching device

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