WO1990013944A1 - Current-based computer logic architecture - Google Patents

Current-based computer logic architecture Download PDF

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Publication number
WO1990013944A1
WO1990013944A1 PCT/US1990/002554 US9002554W WO9013944A1 WO 1990013944 A1 WO1990013944 A1 WO 1990013944A1 US 9002554 W US9002554 W US 9002554W WO 9013944 A1 WO9013944 A1 WO 9013944A1
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WIPO (PCT)
Prior art keywords
output
input
current
wires
wire
Prior art date
Application number
PCT/US1990/002554
Other languages
French (fr)
Inventor
Wolfgang J. Poppelbaum
Jeff Bret Glickman
Original Assignee
Advanced Analytics Corporation
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Publication date
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Publication of WO1990013944A1 publication Critical patent/WO1990013944A1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/12—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using diode rectifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/74—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of diodes
    • H03K17/76—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors

Definitions

  • This invention relates to computer logic architecture and more particularly to a current-based logic system which operates reliably and at high speeds and which facilitates interconnections for the performance of complex logic functions.
  • the invention provides logic cells which are simple in construction and operation, which pan be readily fabricated and interconnected using standard integrated circuit technology for economic manufacture and for high speed performance of logic functions.
  • the logic cells can be readily arranged in arrays or other formats which facilitate the design of logic systems.
  • TTL transistor-transistor logic
  • input signals are applied to multiple emitters of an input transistor which has its base connected to a voltage supply and its collector connected to an output circuit which includes at least one and usually a plurality of transistors which are connected through resistors to the voltage supply.
  • the transistors in TTL circuits generally operate in a saturation mode which results in charge storage problems and delays.
  • resistor values may be reduced, but with increased power dissipation.
  • Hot carrier or Schottky diodes may also be used to provide clamping and prevent transistor saturation but with increased cost and complexity.
  • Emitter-coupled logic is another important type of logic. Transistor saturation is avoided through use of a differential amplifier arrangement.
  • ECL logic gate input signals are applied to the bases of a plurality of input transistors which form one side of a differential amplifier and which are connected in parallel with their collectors connected through a common collector resistor to a voltage supply and also to the base of an output transistor.
  • the other side of the differential amplifier is formed by a transistor which has its collector connected through a resistor to the voltage supply and also to the base of a second output transistor.
  • the base of the transistor which forms the second side of the differential amplifier is connected to a fixed reference voltage supply and its emitter and the emitters of the input transistors are connected to a common current source.
  • ECL circuits have advantages in being capable of operating at high speeds and also in providing complementary outputs but ECL circuits are substantially more expensive and consume much more power than other types of logic circuits.
  • Diode logic has also been used in the prior art.
  • a positive logic OR gate may be formed by a plurality of diodes having anodes connected to input terminals and having cathodes connected to an output terminal and through a resistor to ground.
  • a positive logic AND gate may be formed by a plurality of diodes having cathodes connected to input terminals and having anodes connected to an output terminal and through a resistor to a positive voltage supply terminal.
  • Diode-transistor logic (DTL)and other types of logics have also been used or proposed in the prior art.
  • CCML Complementary Current-Mirror Logic
  • a current mirror is formed by input and output transistors having emitters connected together and to a voltage supply terminal with the base and collector of the input transistor and the base of the output transistor being connected together an to an input terminal and with the collector of the output transistor being connected to an output terminal.
  • Such current mirrors may have multiple outputs or may have an output current which is a multiple or fraction of the input current, related to the ratio of the area of the output transistor to that of the input transistor.
  • a PNP mirror circuit is formed by PNP input and output transistors connected to a positive voltage supply terminal.
  • a NPN mirror circuit is formed by NPN transistors connected to a negative supply terminal.
  • An invertor may be formed by connecting the inputs and outputs of PNP and NPN mirrors.
  • This invention was evolved with the general object of providing a computer architecture which is operative at high speeds with low power consumption and which facilitates reliable performance of logic functions, while being readily and economically manufacturable.
  • a further object of the invention is to provide basic forms of logic cells which can be readily provided and interconnected to perform many types of functions as desired.
  • Important aspects of the invention relate to the recognition of sources of problems with the designs of prior architectures as well as in the recognition of features of prior architectures which are desirably retained.
  • a current- based logic cell includes one or more sections each of which may be a quite simple circuit and which in one embodiment may consist essentially of two diodes, a current source and connecting wires. In other embodiments a transistor and other components may be added.
  • a circuit is provided which includes an input wire to which a plurality of input signals may be applied, each input signal being in the form of a current, and processing circuitry which responds to the net current flow in the input wire to control development of an output signal. High switching speeds are achieved by using very small voltage swings, avoiding saturation and minimizing the effects of capacitances.
  • the circuit includes an output wire in which a current is developed which corresponds to the net current flow in the input wire of the section and which forms the output signal of the section.
  • the input wire of a section may be directly connected to output wires of two or more other sections of the same or similar form, simplifying the interconnection of cells and reducing the length and shunt capacitances of connections between cells, to minimize propagation delays.
  • the circuit includes a first diode which is connected between the input wire and a ground or return path conductor to provide a path for any current through the input wire which may flow in one direction through the first diode.
  • a second diode operates as a summing diode to conduct a current equal to the algebraic sum of input currents applied in reference direction opposite to the direction in which the first diode may conduct, the second diode being operative to develop an output signal which corresponds to the magnitude of summation of input currents conducted by the second diode.
  • the second diode is connected directly between the input wire and an output wire and a bias current is applied to the output wire in opposition to any net input current flow through the second diode.
  • the output signal is a thereby a current in the output wire, flowing in one direction when the net input current exceeds the bias current and flowing in the reverse direction when the net input current is less than the bias current. Since the output signal is a current, the output wire and an output wire of another section of the same form may be directly connected to an input wire of a third section of the same form to provide two input currents to the third section.
  • a current-based logic cell includes a pair of sections, each section having an input wire to which a plurality of input signals may be applied and each section further including processing circuitry which responds to a summation of currents flowing in the input wire of the section to control the development of an output signal, preferably as a current in an output wire of the section.
  • the two sections operate in push-pull.
  • Each input to cell may be provided by applying currents in opposite directions to the input wires of the two sections, one flowing into the processing circuitry of the cell and the other flowing away from the cell.
  • the two input wires of the push-pull cell may be referred to as a "TRUE” wire and a "FALSE” wire.
  • TRUE The two input wires of the push-pull cell
  • FALSE The two input wires of the push-pull cell
  • one current component of each applied pair of components may be applied in a direction to flow through the "TRUE” wire in a direction which is the same as a preferred or reference direction, defined as being toward the processing circuitry, while the other component is applied to flow through the "FALSE” wire in a direction opposite the preferred or reference direction, i.e. away from the processing circuitry.
  • Logic "0" and logic “l” currents are defined in accordance with currents in such "TRUE” and "FALSE” wires.
  • a very important advantage of the current-based push-pull cell of the invention is that an invertor for use with the cell requires no parts and represents no delay.
  • An invertor is made by simply reversing or transposing wires in connecting the cell to another cell or to input or output circuits. All basic types of logic gates can use the same basic cell, using readily implemented combinations of normal and reversed connections of the pairs of input and output wires, without any propagation delay.
  • transistorized circuitry is provided within cells which operates to insure more uniform and reliable development of output currents for application to other cells or to output circuits and which also operate to permit fan-out as desired, such that one cell can supply output currents to a number of other cells or circuits.
  • sums of "TRUE” and "FALSE” input currents are applied through level-shift circuits to the bases of one or more pairs of transistors which have output electrodes connected to "T" and "F” output wires and to bias current sources.
  • a basic building block which is a current-based logic element so constructed that through direct connections of such elements, substantially all desired types of logic functions may be accomplished.
  • FIGURE 1 is a schematic diagram of a current- based push-pull logic cell construction in accordance with the invention and shown connected to signal-receiving and applying circuits;
  • FIGURE 2 illustrates a method of representing the logic states of circuits of the invention
  • FIGURE 3 shows the use of transposed or reversed connections of a cell to implement a NAND logic gate
  • FIGURE 4 shows the use of transposed or reversed connections of a cell to implement an OR logic gate
  • FIGURE 5 shows the use of transposed or reversed connections of a cell to implement a NOR logic gate
  • FIGURE 6 is a schematic diagram showing the implementation of a three-input AND gate using two cascaded single-section cells
  • FIGURE 7 is a schematic diagram showing another implementation of a three input AND gate, using on single- section cell
  • FIGURE 8 is a schematic diagram of another preferred form of logic cell which is constructed in accordance with the invention and which provides for increased fan-out and other advantages;
  • FIGURE 9 is a schematic diagram of another preferred form of logic cell of the invention.
  • FIGURES 10, 11 and 12 illustrate level shift circuits usable in the logic cell of FIG. 9.
  • Reference numeral 10 generally designates a current-based push-pull logic cell which is constructed in accordance with the principles of the invention.
  • the cell 10 is operative to produce currents in a pair of upper and lower output wires 11 and 12 in directions which are determined by the directions and magnitudes of currents applied to a pair of lower input wires 13 and 14.
  • the output wires 11 and 12 are shown connected to a signal- receiving circuit 16 which may, for example, be another logic cell or an output or interface circuit, circuit 16 being shown schematically as providing resistances 17 and 18 connected between wires 11 and 12 and ground.
  • the input wires are shown connected to two signal-applying circuits 19 and 20 which apply logic signals in the form of currents, each of which may, for example, be another current based logic cell or an input or interface circuit operative to supply current-based signals in response to voltage-based signals.
  • both upper and lower input wires 13 and 14 of cell 10 are directly connected to upper and lower output wires 21 and 22 of signal-applying circuit 19 and also to upper and lower output wires 23 and 24 of signal-applying circuit 20.
  • Each of the signal-applying circuits 19 and 20 may be assumed to be operative to effect flow of a normalized current of a certain magnitude in one direction through its upper output wire while effecting flow of a normalized current of the same magnitude but in the opposite direction through its lower output wire.
  • the illustrated logic cell 10 comprises an upper section 25 and a lower section 26 which operate independently of each other and which are of complementary form in the illustrated embodiment.
  • the section 25 comprises a diode 27 having an anode connected to ground and a cathode connected to the input wire 13, a diode 28 having an anode connected to the input wire 13 and a cathode connected to the output wire 11, and a bias current source 30 which is connected to effect flow of normalized current from the output wire 11 to ground.
  • the section 26 comprises a diode 31 having a cathode connected to ground and an anode connected to the input wire 14, a diode 32 having a cathode connected to the input wire 14 and an anode connected to the output wire 12 and a bias current source 34 which is connected to effect flow of a normalized current from ground to the output wire 12.
  • the upper and lower sections 25 and 26 have the same mode of operation.
  • the current in the input wire 13 has a magnitude equal to twice the magnitude of each of the two • normalized currents applied in the same direction from the circuits 19 and 20 and is applied through the diode 28 which operates as a summing diode. One-half of this current is drawn off through the bias source 28 to ground. The remaining half, a current equal to the normalized current, flows out through the output wire 11 and through the resistor 17 of the receiving circuit 16 to ground.
  • a normalized current flows in the reverse direction through the output wire 11, i.e. from the receiving circuit 16 and toward the logic cell 10 thence through the bias source 30 to ground, there being no current through the summing diode 28.
  • the diode 28 cannot conduct, and both currents will be conducted by the diode 27.
  • the diode 27 thus operates as a return diode, insuring a return path for input currents applied in a direction opposite the direction in which they would be conducted through the summing diode 28.
  • the operation of the lower section 26 is independent of the operation of the upper section 25, and is the same except that the diodes 31 and 32 and the bias current source 34 are connected to conduct in directions which are the reverse of the conductions of the diodes 27 and 28 and the bias current source 30. The corresponding directions of flow of input and output currents are therefore reversed.
  • Figure 2 illustrates a method of representing the logic states of circuits of the invention which may be uniformly applied and which is useful in showing advantages of the current-based push-pull operation of circuits of the invention.
  • a logic "1” may represented by the combination of a current flow to the right in one of the upper wires 11, 13, 21 or 23 and to the left in the corresponding lower wire 12, 14, 22 or 24 while logic "0" is represented by a combination of current flows in the opposite direction.
  • Figure 2 provides a more generalized representation, in which one wire in a pair is identified as a "TRUE" wire, the other is identified as a "FALSE" wire and a reference direction of current flow is also identified.
  • a logic “1” is defined as a current flow in the "TRUE” wire in the reference direction accompanied by a current flow in the "FALSE” wire opposite the reference direction.
  • a logic “0” is defined as a current flow in the "TRUE” wire in a direction opposite the reference direction accompanied by a current flow in the "FALSE” wire in the reference direction.
  • Figures 3-5 show use of transposed or reversed connections to implement different forms of logic gates.
  • Figure 3 shows the cell 10 with "T” and “F” output wires 11 and 12 connected through transposed or reversed connections to a "T” wire 35 and a “F” wire 36 for connection to a receiving circuit, the "T" output wire 11 being connected to the "F” wire 36 and the “F” output wire 12 being connected to the "T” wire 35.
  • the connections of the input wires 13 and 14 to the signal-applying circuits 19 and 20 are “normal” connections which are the same as in Figure 1. With such connections, a NAND gate is provided. A logic “0” is produced on the "T” and “F” wires 35 and 36 in response to input currents as indicated by the arrows.
  • Figure 4 shows the cell 10 with "T” and “F” output wires 11 and 12 connected through transposed or reversed connections to “F” and “T” wires 36 and 35, respectively, in the same way as in Figure 3.
  • a pair of "T” and “F” wires 37 and 38 are shown connected to the "T” and “F” wires 21, 23 and 22, 24 of the signal applying circuits 19 and 20 and also through transposed or reversed connections to the "F” and "T” input wires 14 and 13, respectively.
  • an OR gate is provided.
  • a logic "1" is produced at the "T" and "F” wires 35 and 36 when a logic "1” is applied by either or both of the signal applying circuits 19 and 20, a logic "0” being produced only when both circuits 19 and 20 apply a logic "0" to the wires 37 and 38.
  • Figure 5 shows the cell 10 with normal connections between the output wires and the signal- receiving circuit 16 but with transposed or reversed connections of the input wires 13 and 14 to the wires 37 and 38, the same as in Figure 4. With such connections a NOR gate is provided, a logic "1" being produced when neither the signal-applying circuit 19 nor the signal- applying circuit 20 applies a logic "1" to the wires 37 and 38.
  • FIG. 6 shows the implementation of a three-input AND gate using two cascaded single-section cells 41 and 42 as shown, the cell 41 is the same as the section 25 of the cell 10 and comprises diodes 43 and 44 and a current source 46, respectively corresponding to the diodes 27 and 28 and current source 30 of the section 25.
  • Output and input wires 47 and 48 correspond to output and input wires 11 and 13 of the cell 10.
  • the circuit of the cell 42 is not shown but it will be understood that it is a single section cell which is the same as that of the cell 41 and it has one output wire 49 and one input wire 50.
  • the output wire 49 of the cell 42 is connected to a signal-receiving circuit 52 which may provide a single resistance 53 to ground, as diagrammatically shown.
  • Three signal-applying circuits 54, 55 and 56 are shown in Figure 6, having output wires 57, 58 and 59.
  • Each of the output wires 57-59 may supply a normalized current flowing out of the circuit or a normalized current flowing into the circuit.
  • the output wire 57 of the circuit 54 and the output wire 58 of the circuit 55 are connected directly to the input wire 48 of the cell 41.
  • the output wire 47 of the cell 41 and the output wire 59 of the cell 56 are connected to the input wire 50 of the cell.42. With these connections, a logic "1" current signal is applied through the wire 49 to the signal- receiving circuit 52 when logic "1" currents are applied by all three of the signal-applying circuits 54-56.
  • Connections such as shown in Figure 6 may be used to implement a three input AND gate with push-pull logic cells.
  • Two push-pull cells such as the cell 10 may be cascaded, using the connections such as shown in Figure 6 for the "TRUE” sections of the two cells and using complements of such connections for the "FALSE” sections of the two cascaded cells.
  • Figure 7 shows another method of providing a three input AND gate which is shown being implemented using the single section cell 41 but which may alternatively be implemented using the push-pull cell 10.
  • the single section cell 41 is usable as shown with its output wire 47 connected to the signal-receiving circuit 52 and with its input wire 48 connected directly to the . output wires 57, 58 and 59 of the signal-applying circuits 54-56.
  • a bias current source 60 is connected between the input wire 48 and ground and applies a current in a direction to flow from the wire 48 to ground. With this arrangement, a current signalling a logic "1" is produced in the output wire 47 only when all three signal- applying circuits 54-56 apply the logic "1" current signal.
  • the bias source 60 and a set of connections such as shown in Figure 7 may be used in connection with the section 25 of the cell 10 and an additional bias source and a complementary set of connections may be used in connection with the section 26 of the cell 10.
  • reference numeral 62 generally designates another preferred form of logic cell constructed in accordance with the invention and which provides for increased fan-out and other advantages.
  • the cell 62 utilizes current mirrors to provide output currents to a plurality of additional cells or other forms of signal-receivers. Fan-out is increased by adding more output transistors to the current mirrors.
  • the cell 62 includes two sections 63 and 64 which, like the sections 25 and 26 of cell 10, are independent but which provide a plurality of outputs. Two outputs are provided in the circuit as shown but it will be understood that a number of additional outputs may be added. It should also be understood that the circuit may be used to advantage when using a single output in that a current mirror provides isolation and insures development of output currents such that any number of cells may be cascaded.
  • the sections 63 and 64 have two "T” output wires 67 and 68 and two "F” output wires 69 and 70, shown connected to two signal receiving circuits 71 and
  • the sections 63 also have upper and lower "T" and "F” input wires 73 and 74 which are connected to two signal- applying circuits 75 and 76 which apply logic signals in the form of currents, each of which may, for example, be another current based logic cell or an input or interface circuit operative to supply current-based signals in response to voltage-based signals.
  • both upper and lower input wires 73 and 74 of cell 62 are directly connected to upper and lower output wires 77 and 78 of signal-applying circuit 75 and also to upper and lower output wires 79 and 80 of signal-applying circuit 76.
  • Each of the signal-applying circuits 75 and 76 may be assumed to be operative to effect flow of a normalized current of a certain magnitude in one direction through its upper output wire while effecting flow of a normalized current of the same magnitude but in the opposite direction through its lower output wire.
  • the input wires 73 and 74 are connected to ground through a pair of diodes 81 and 82 which operate as return diodes in a manner similar to the diodes return diodes 27 and 31 of the cell 10.
  • the input wires 73 and 74 are also connected to ground through a pair of diodes 83 and 84 which are in parallel with the base-emitter junctions of a NPN transistor 85 and a PNP transistor 86.
  • the collectors of transistors 85 and 86 are connected through diodes 87 and 88 to voltage supply terminals 89 and 90 to which positive and negative supply voltages are respectively applied.
  • a first pair of PNP and NPN output transistors 91 and 92 have bases connected to the collectors of transistors 85 and 86, emitters connected to terminals 89 and 90, collectors connected to output wires 67 and 69 and also through bias current sources 93 and 94 to ground.
  • a second pair of PNP and NPN output transistors 95 and 96 have bases connected to the collectors of transistors 85 and 86, emitters connected to terminals 89 and 90, collectors connected to output wires 68 and 70 and also through bias current sources 97 and 98 to ground.
  • the output transistors 91 and 95 of the upper section 63 are conductive in response to logic "l" currents applied to the input wire 65 of the section, they preferably conduct currents equal to twice the current used to represent a logic "1” while currents equal to the logic "1” current are drawn off through the bias current sources 93 and 97, the currents in the output wires being thereby equal to the logic "1" current.
  • the operation of the lower section 64 of cell 62 is complementary to that of the upper section 63 and characteristics of the PNP and NPN transistors are preferably matched so as to produce substantially the same "T" and "F” output currents.
  • the characteristics of the diodes 83, 84, 87 and 88 are also matched to the characteristics of the transistor base-emitter junctions with which they are in parallel to obtain accurate and reliable operation in mirroring the input currents and in insuring reliable development of output currents of substantially constant magnitude.
  • the circuit 62 allows operation of as many cells in cascade as may be desired.
  • Figure 9 is a circuit diagram of another logic cell 100 which is constructed in accordance with the invention.
  • the illustrated cell 100 includes emitter coupled transistors which operate in a manner similar to those of ECL circuits to obtain advantages similar to those obtained from ECL circuits and which, in addition, respond to input currents to obtain the advantages of the above described circuits of the invention.
  • the illustrated cell 100 is a three input, two output cell which receives push-pull inputs from three current signal-applying circuits 101, 102 and 103, an input wire 105 of the circuit 100 being connected to "TRUE" outputs of the circuits 101-103 and a second input wire 106 being connected to "FALSE" outputs of the circuit 101-103.
  • the two outputs of cell 100 are connected to two current signal-receiving circuits 107 and 108. As shown, two "TRUE” outputs are connected through wires 109 and 110 to circuits 107 and 108 and two "FALSE” outputs are connected through wires 111 and 112 to the circuits 107 and 108.
  • the input wires 105 and 106 are connected through resistors 115 and 116 to voltage supply terminals 117 and 118 and are also connected through level shifter circuits 119 and 120 to base electrodes of a first pair of transistors 121 and 122 and base electrodes of a second pair of transistors 123 and 124.
  • the collectors of transistors 121 and 122 are connected to the "FALSE" output wires 111 and 112 and are also connected through current sources 125 and 126 to a voltage supply terminal 128.
  • the collectors of transistors 123 and 124 are connected to the "TRUE" output wires 109 and 110 and are also connected through current sources 129 and 130 to the voltage supply terminal 128.
  • the emitters of all four transistors 121-124 are connected together and through a current source 132 to a voltage supply terminal 134.
  • Operation of the cell involves the generation of a small voltage difference between the voltage at the bases of the pair of transistors 121 and 122 and the voltage at the bases of the pair of transistors 123 and 124, to cause conduction of one pair and to cut off conduction of the other pair.
  • each collector of the conducting pair sinks a current equal to 2i 0 , where i 0 is a normalized current which comes from the corresponding one of the bias current sources 125, 126, 129 or 130 and where another cuurent equal to i 0 comes from the corresponding one of th output wires 109-112. This corresponds to a logic 0.
  • the corresponding pair of the bias current sources 125, 126 or 129, 130 supplies a current to the next gate which represents a logic 1.
  • the voltage difference across the emitter coupled transistors is generated from the input currents in wires 105 and 106 and is shifted in level by the level shifters 119, 120 before application to the base electrodes of the emitter coupled transistors.
  • Input currents which correspond to "TRUE” inputs are summed together and are used to generate a small voltage of one polarity on one side of the emitter coupled pair of transistors while input currents corresponding to "FALSE" inputs are summed together and used to generate another small voltage of the opposite polarity on the other side of the emitter coupled pair.
  • the resistors 115 and 116 are connected to the voltage supply terminals 117 and 118 to supply small negative and positive bias voltages, so chosen that the voltage generated by the "FALSE" input currents is greater than that generated by the "TRUE” input currents except for the case when all the currents on the "TRUE” side are directed into the circuit and all the "FALSE” input currents are directed out of the circuit.
  • This case corresponds to an input of all logic l's and is the only valid logic input which will cause the transistors 123 and 124 of the illustrated circuit to conduct while cutting off conduction of the transistors 121 and 122 on the left side.
  • the two-level shifters 119 and 230 translate the voltage generated by the summed input currents, operating to subtract a constant from the voltage on each side. They operate to keep the emitter coupled resistors from going into saturation to insure high speed operation of the circuit.
  • circuit of Figure 9 may be extended to provide four outputs, rather than two, or as many additional outputs as may be desired. It is also noted that multiple collector transistors may be used.
  • the internal mirror arrangement is such as guarantee substantially equal distributions of bias currents. Very small voltage swings are required, and the corresponding required bias voltages are also small.
  • FIGS 10, 11 and 12 illustrate three representative level shifter circuits 140, 141 and 142 which may be used as the level shifters 119 and 120 in the circuit of Figure 9.
  • an input wire 143 is connected through a Zener diode 144 to an output wire 145.
  • the input wire is also connected through a resistor 147 to a voltage supply terminal 148 while the output wire 145 is connected through a resistor 149 to a voltage supply terminal 150.
  • the voltage supply terminals 148 may, ' for example, be tied to the voltage supply terminals 128 and 134 when the circuit 140 is used as the level shifter 119 or level shifter 120.
  • the input wire 143 may be connected to the wire 105 or wire 106 while the output wire 145 may be connected to the base electrodes of the transistors 121 or 122 or the base electrodes of the electrodes 123 and 124.
  • a substantially constant voltage drop is produced across the Zener diode to down-shift the level of the voltage applied to the input wire 143 to that developed at the output wire 145.
  • the level shifter circuit 141 of Figure 11 is the same as in Figure 10 except that a simple resistor 152 is substituted for the Zener diode 144. With a substantially constant current being applied to the circuit, the voltage drop across the resistor 152 is also substantially constant.
  • a transistor 154 and a pair of diodes 155 and 156 are used in place of the resistor 147 and Zener diode 144 or resistor 152 of the circuits of Figures 10 and 11.
  • the base of the transistor 154 is connected to the input wire 143
  • the collector of the transistor 154 is connected to the voltage supply terminal 148 and the diodes 155 and 156 are • connected in series between the emitter of the transistor 154 and the output wire 145.
  • a "long emitter-follower" is provided in which the diodes provide a subtantially constant current and which operates to produce a substantially constant voltage drop while passing the input current from the input wire 143 to the output wire 145.
  • the diffusion capacitances of the diodes act like speed-up capacitors.

Abstract

A current-based logic cell comprises input means (13, 14), output means (12, 21-24) and processing means (10) coupled to the input and output means. The input means includes an input wire arranged for direct application of a plurality of input signals thereto, each input signal being a current. The processing means is responsive to an algebraic summation of currents flowing in one direction in said input wire to control development at the output means or of first or second forms of output signals.

Description

CURRENT-BASED COMPUTER LOGIC ARCHITECTURE
BACKGROUND OF THE INVENTION
1. Field of the Invention:
This invention relates to computer logic architecture and more particularly to a current-based logic system which operates reliably and at high speeds and which facilitates interconnections for the performance of complex logic functions. The invention provides logic cells which are simple in construction and operation, which pan be readily fabricated and interconnected using standard integrated circuit technology for economic manufacture and for high speed performance of logic functions. The logic cells can be readily arranged in arrays or other formats which facilitate the design of logic systems.
2. Background of the Prior Art:
Many different types of logic have been used in prior art computer circuits. A very common type of logic is transistor-transistor logic (TTL) . In a typical TTL system, input signals are applied to multiple emitters of an input transistor which has its base connected to a voltage supply and its collector connected to an output circuit which includes at least one and usually a plurality of transistors which are connected through resistors to the voltage supply. The transistors in TTL circuits generally operate in a saturation mode which results in charge storage problems and delays. In an attempt to obtain increased operating speed, resistor values may be reduced, but with increased power dissipation. Hot carrier or Schottky diodes may also be used to provide clamping and prevent transistor saturation but with increased cost and complexity.
Emitter-coupled logic (ECL) is another important type of logic. Transistor saturation is avoided through use of a differential amplifier arrangement. In a typical ECL logic gate, input signals are applied to the bases of a plurality of input transistors which form one side of a differential amplifier and which are connected in parallel with their collectors connected through a common collector resistor to a voltage supply and also to the base of an output transistor. The other side of the differential amplifier is formed by a transistor which has its collector connected through a resistor to the voltage supply and also to the base of a second output transistor. The base of the transistor which forms the second side of the differential amplifier is connected to a fixed reference voltage supply and its emitter and the emitters of the input transistors are connected to a common current source. ECL circuits have advantages in being capable of operating at high speeds and also in providing complementary outputs but ECL circuits are substantially more expensive and consume much more power than other types of logic circuits.
Diode logic has also been used in the prior art. A positive logic OR gate may be formed by a plurality of diodes having anodes connected to input terminals and having cathodes connected to an output terminal and through a resistor to ground. A positive logic AND gate may be formed by a plurality of diodes having cathodes connected to input terminals and having anodes connected to an output terminal and through a resistor to a positive voltage supply terminal. Diode-transistor logic (DTL)and other types of logics have also been used or proposed in the prior art.
Another form of logic which has been proposed is referred to as "CCML" and is described in a paper entitled "Complementary Current-Mirror Logic" by C.M.Horwitz and M.D.Silver, appearing at pages 91-97 of the IEEE Journal of Solid-state Circuits, Vol. 23, No. l., February 1988.
In the CCML system as described by Horwitz and
Silver, a current mirror is formed by input and output transistors having emitters connected together and to a voltage supply terminal with the base and collector of the input transistor and the base of the output transistor being connected together an to an input terminal and with the collector of the output transistor being connected to an output terminal. Such current mirrors may have multiple outputs or may have an output current which is a multiple or fraction of the input current, related to the ratio of the area of the output transistor to that of the input transistor. A PNP mirror circuit is formed by PNP input and output transistors connected to a positive voltage supply terminal. A NPN mirror circuit is formed by NPN transistors connected to a negative supply terminal. An invertor may be formed by connecting the inputs and outputs of PNP and NPN mirrors. By combining invertors having current mirrors with selected ratios, various forms of logic gates and other circuits may be formed. The description of the CCML System proposed by Horwitz and Silver indicates that it would have potential advantages over a ECL system with respect to reduction of power requirements, minimizing noise and an ability to handle multilevel logic signals, but it also indicates that it would have disadvantages with respect to a need for frequent current normalization, additional resistors and increased delay times.
SUMMARY OF THE INVENTION
This invention was evolved with the general object of providing a computer architecture which is operative at high speeds with low power consumption and which facilitates reliable performance of logic functions, while being readily and economically manufacturable.
It is also an object of the invention to provide a computer architecture which is such as to facilitate design and implementation of systems which perform complex functions and which may be provided at low cost.
A further object of the invention is to provide basic forms of logic cells which can be readily provided and interconnected to perform many types of functions as desired.
Important aspects of the invention relate to the recognition of sources of problems with the designs of prior architectures as well as in the recognition of features of prior architectures which are desirably retained.
In accordance with the invention, a current- based logic cell includes one or more sections each of which may be a quite simple circuit and which in one embodiment may consist essentially of two diodes, a current source and connecting wires. In other embodiments a transistor and other components may be added. In each embodiment, a circuit is provided which includes an input wire to which a plurality of input signals may be applied, each input signal being in the form of a current, and processing circuitry which responds to the net current flow in the input wire to control development of an output signal. High switching speeds are achieved by using very small voltage swings, avoiding saturation and minimizing the effects of capacitances.
Preferably, the circuit includes an output wire in which a current is developed which corresponds to the net current flow in the input wire of the section and which forms the output signal of the section. As a result, the input wire of a section may be directly connected to output wires of two or more other sections of the same or similar form, simplifying the interconnection of cells and reducing the length and shunt capacitances of connections between cells, to minimize propagation delays.
In one embodiment, the circuit includes a first diode which is connected between the input wire and a ground or return path conductor to provide a path for any current through the input wire which may flow in one direction through the first diode. A second diode operates as a summing diode to conduct a current equal to the algebraic sum of input currents applied in reference direction opposite to the direction in which the first diode may conduct, the second diode being operative to develop an output signal which corresponds to the magnitude of summation of input currents conducted by the second diode. In accordance with a specific feature, the second diode is connected directly between the input wire and an output wire and a bias current is applied to the output wire in opposition to any net input current flow through the second diode. The output signal is a thereby a current in the output wire, flowing in one direction when the net input current exceeds the bias current and flowing in the reverse direction when the net input current is less than the bias current. Since the output signal is a current, the output wire and an output wire of another section of the same form may be directly connected to an input wire of a third section of the same form to provide two input currents to the third section.
In accordance with another very important feature of the invention, a current-based logic cell includes a pair of sections, each section having an input wire to which a plurality of input signals may be applied and each section further including processing circuitry which responds to a summation of currents flowing in the input wire of the section to control the development of an output signal, preferably as a current in an output wire of the section. The two sections operate in push-pull. Each input to cell may be provided by applying currents in opposite directions to the input wires of the two sections, one flowing into the processing circuitry of the cell and the other flowing away from the cell.
The two input wires of the push-pull cell may be referred to as a "TRUE" wire and a "FALSE" wire. To apply a true signal, one current component of each applied pair of components may be applied in a direction to flow through the "TRUE" wire in a direction which is the same as a preferred or reference direction, defined as being toward the processing circuitry, while the other component is applied to flow through the "FALSE" wire in a direction opposite the preferred or reference direction, i.e. away from the processing circuitry. Logic "0" and logic "l" currents are defined in accordance with currents in such "TRUE" and "FALSE" wires.
A very important advantage of the current-based push-pull cell of the invention is that an invertor for use with the cell requires no parts and represents no delay. An invertor is made by simply reversing or transposing wires in connecting the cell to another cell or to input or output circuits. All basic types of logic gates can use the same basic cell, using readily implemented combinations of normal and reversed connections of the pairs of input and output wires, without any propagation delay.
Further important features of the invention relate to the provision of circuits using transistors to obtain more reliable results while retaining the advantages of current-based and push-pull operations. In one type of transistorized circuit, current-mirror circuitry is provided within cells which operates to insure more uniform and reliable development of output currents for application to other cells or to output circuits and which also operate to permit fan-out as desired, such that one cell can supply output currents to a number of other cells or circuits. In another type of transistorized circuit, sums of "TRUE" and "FALSE" input currents are applied through level-shift circuits to the bases of one or more pairs of transistors which have output electrodes connected to "T" and "F" output wires and to bias current sources.
With circuits constructed in accordance with the invention, a basic building block can be provided which is a current-based logic element so constructed that through direct connections of such elements, substantially all desired types of logic functions may be accomplished.
These and other objects, features and advantages will become more fully apparent from the following detailed description taking in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGURE 1 is a schematic diagram of a current- based push-pull logic cell construction in accordance with the invention and shown connected to signal-receiving and applying circuits;
FIGURE 2 illustrates a method of representing the logic states of circuits of the invention;
FIGURE 3 shows the use of transposed or reversed connections of a cell to implement a NAND logic gate;
FIGURE 4 shows the use of transposed or reversed connections of a cell to implement an OR logic gate;
FIGURE 5 shows the use of transposed or reversed connections of a cell to implement a NOR logic gate;
FIGURE 6 is a schematic diagram showing the implementation of a three-input AND gate using two cascaded single-section cells;
FIGURE 7 is a schematic diagram showing another implementation of a three input AND gate, using on single- section cell; FIGURE 8 is a schematic diagram of another preferred form of logic cell which is constructed in accordance with the invention and which provides for increased fan-out and other advantages;
FIGURE 9 is a schematic diagram of another preferred form of logic cell of the invention; and
FIGURES 10, 11 and 12 illustrate level shift circuits usable in the logic cell of FIG. 9.
DESCRIPTION OF PREFERRED EMBODIMENTS
Reference numeral 10 generally designates a current-based push-pull logic cell which is constructed in accordance with the principles of the invention. The cell 10 is operative to produce currents in a pair of upper and lower output wires 11 and 12 in directions which are determined by the directions and magnitudes of currents applied to a pair of lower input wires 13 and 14. The output wires 11 and 12 are shown connected to a signal- receiving circuit 16 which may, for example, be another logic cell or an output or interface circuit, circuit 16 being shown schematically as providing resistances 17 and 18 connected between wires 11 and 12 and ground.
The input wires are shown connected to two signal-applying circuits 19 and 20 which apply logic signals in the form of currents, each of which may, for example, be another current based logic cell or an input or interface circuit operative to supply current-based signals in response to voltage-based signals. As shown, both upper and lower input wires 13 and 14 of cell 10 are directly connected to upper and lower output wires 21 and 22 of signal-applying circuit 19 and also to upper and lower output wires 23 and 24 of signal-applying circuit 20. Each of the signal-applying circuits 19 and 20 may be assumed to be operative to effect flow of a normalized current of a certain magnitude in one direction through its upper output wire while effecting flow of a normalized current of the same magnitude but in the opposite direction through its lower output wire.
In a condition in which currents flow as depicted by arrows in Figure 1, and in which it may be assumed that a logic "1" is applied by each of the circuits 19 and 20, a normalized current flows in each of the upper wires 21 and 23 to the right, out of or away from the circuit 19 or 20 and into or toward the cell 10, while a normalized current flows in each of the lower wires 22 and 24 to the left into or toward the circuit 19 or 20 and out of or away from the cell 10. Under this condition, the logic cell 10 operates to produce a logic "1" as an output, represented by a current which flows to the right in the upper output wire 11 and which has a magnitude equal to the normalized current while a current of the same magnitude flows to the left in the lower output wire 12. Thus when two pairs of input currents are applied to the cell 10, each pair representing a logic "1", the cell develops a pair of output currents which represents a logic "1".
Under other conditions, when the currents applied by either or both of the circuits 19 and 20 are reversed in direction to represent a logic "O", the directions of currents flowing in the output wires 11 and 12 are reversed to represent a logic "0". Thus the logic cell 10 operates as an AND gate.
The illustrated logic cell 10 comprises an upper section 25 and a lower section 26 which operate independently of each other and which are of complementary form in the illustrated embodiment. The section 25 comprises a diode 27 having an anode connected to ground and a cathode connected to the input wire 13, a diode 28 having an anode connected to the input wire 13 and a cathode connected to the output wire 11, and a bias current source 30 which is connected to effect flow of normalized current from the output wire 11 to ground. The section 26 comprises a diode 31 having a cathode connected to ground and an anode connected to the input wire 14, a diode 32 having a cathode connected to the input wire 14 and an anode connected to the output wire 12 and a bias current source 34 which is connected to effect flow of a normalized current from ground to the output wire 12.
The upper and lower sections 25 and 26 have the same mode of operation. First consider the operation with the currents flowing as depicted by arrows in Figure 1. In this condition, the current in the input wire 13 has a magnitude equal to twice the magnitude of each of the two • normalized currents applied in the same direction from the circuits 19 and 20 and is applied through the diode 28 which operates as a summing diode. One-half of this current is drawn off through the bias source 28 to ground. The remaining half, a current equal to the normalized current, flows out through the output wire 11 and through the resistor 17 of the receiving circuit 16 to ground.
Under other conditions, a normalized current flows in the reverse direction through the output wire 11, i.e. from the receiving circuit 16 and toward the logic cell 10 thence through the bias source 30 to ground, there being no current through the summing diode 28. For example, if both currents applied from circuits 19 and 20 to wire 13. are reversed, the diode 28 cannot conduct, and both currents will be conducted by the diode 27. The diode 27 thus operates as a return diode, insuring a return path for input currents applied in a direction opposite the direction in which they would be conducted through the summing diode 28. If the currents applied from only one of the circuits 19 and 20 are reversed while the currents applied from the other are the same as depicted, the two currents applied to wire 13 cancel each other and there is no net current flow therein or in either of the diodes 27 and 28.
The operation of the lower section 26 is independent of the operation of the upper section 25, and is the same except that the diodes 31 and 32 and the bias current source 34 are connected to conduct in directions which are the reverse of the conductions of the diodes 27 and 28 and the bias current source 30. The corresponding directions of flow of input and output currents are therefore reversed.
The combination of the two processing sections 25 and 26 and associated input wires 11 and 12 and output wires 13 and 14 has very important advantages. An invertor for use with the cell 10 requires no parts and represents no delay. An invertor is made by simply reversing or transposing wires in connecting the cell 10 to another cell or to input or output circuits. All basic types of logic gates can use the same basic cell, using readily implemented combinations of normal and reversed connections of the pairs of input and output wires, without any propagation delay. These advantages are illustrated in Figures 2-5.
Figure 2 illustrates a method of representing the logic states of circuits of the invention which may be uniformly applied and which is useful in showing advantages of the current-based push-pull operation of circuits of the invention. As indicated in the foregoing discussion of Figure 1, a logic "1" may represented by the combination of a current flow to the right in one of the upper wires 11, 13, 21 or 23 and to the left in the corresponding lower wire 12, 14, 22 or 24 while logic "0" is represented by a combination of current flows in the opposite direction. Figure 2 provides a more generalized representation, in which one wire in a pair is identified as a "TRUE" wire, the other is identified as a "FALSE" wire and a reference direction of current flow is also identified. A logic "1" is defined as a current flow in the "TRUE" wire in the reference direction accompanied by a current flow in the "FALSE" wire opposite the reference direction. A logic "0" is defined as a current flow in the "TRUE" wire in a direction opposite the reference direction accompanied by a current flow in the "FALSE" wire in the reference direction. Thus, the output wire 11 and input wire 13 of the illustrated cell 10 and wires 21 and 23 of circuits 19 and 20 are "TRUE" or "T" wires, while output wire 12 and input wire 14 of cell 10 and wires 22 and 24 of circuits 19 and 20 are "FALSE" or "F" wires.
Figures 3-5 show use of transposed or reversed connections to implement different forms of logic gates. Figure 3 shows the cell 10 with "T" and "F" output wires 11 and 12 connected through transposed or reversed connections to a "T" wire 35 and a "F" wire 36 for connection to a receiving circuit, the "T" output wire 11 being connected to the "F" wire 36 and the "F" output wire 12 being connected to the "T" wire 35. The connections of the input wires 13 and 14 to the signal-applying circuits 19 and 20 are "normal" connections which are the same as in Figure 1. With such connections, a NAND gate is provided. A logic "0" is produced on the "T" and "F" wires 35 and 36 in response to input currents as indicated by the arrows. Figure 4 shows the cell 10 with "T" and "F" output wires 11 and 12 connected through transposed or reversed connections to "F" and "T" wires 36 and 35, respectively, in the same way as in Figure 3. In addition, a pair of "T" and "F" wires 37 and 38 are shown connected to the "T" and "F" wires 21, 23 and 22, 24 of the signal applying circuits 19 and 20 and also through transposed or reversed connections to the "F" and "T" input wires 14 and 13, respectively. With such connections, an OR gate is provided. A logic "1" is produced at the "T" and "F" wires 35 and 36 when a logic "1" is applied by either or both of the signal applying circuits 19 and 20, a logic "0" being produced only when both circuits 19 and 20 apply a logic "0" to the wires 37 and 38.
Figure 5 shows the cell 10 with normal connections between the output wires and the signal- receiving circuit 16 but with transposed or reversed connections of the input wires 13 and 14 to the wires 37 and 38, the same as in Figure 4. With such connections a NOR gate is provided, a logic "1" being produced when neither the signal-applying circuit 19 nor the signal- applying circuit 20 applies a logic "1" to the wires 37 and 38.
Although the combination of the two processing sections 25 and 26 and associated input and output wires has very important advantages, there is a redundancy in providing more than one section and associated input and output wires, since a logic gate function can be performed independently by each processing section and associated output and input wires. In many applications, cells may be used in the form of single sections. For example, Figure 6 shows the implementation of a three-input AND gate using two cascaded single-section cells 41 and 42 as shown, the cell 41 is the same as the section 25 of the cell 10 and comprises diodes 43 and 44 and a current source 46, respectively corresponding to the diodes 27 and 28 and current source 30 of the section 25.
Output and input wires 47 and 48 correspond to output and input wires 11 and 13 of the cell 10. The circuit of the cell 42 is not shown but it will be understood that it is a single section cell which is the same as that of the cell 41 and it has one output wire 49 and one input wire 50. The output wire 49 of the cell 42 is connected to a signal-receiving circuit 52 which may provide a single resistance 53 to ground, as diagrammatically shown.
Three signal-applying circuits 54, 55 and 56 are shown in Figure 6, having output wires 57, 58 and 59. Each of the output wires 57-59 may supply a normalized current flowing out of the circuit or a normalized current flowing into the circuit. The output wire 57 of the circuit 54 and the output wire 58 of the circuit 55 are connected directly to the input wire 48 of the cell 41. The output wire 47 of the cell 41 and the output wire 59 of the cell 56 are connected to the input wire 50 of the cell.42. With these connections, a logic "1" current signal is applied through the wire 49 to the signal- receiving circuit 52 when logic "1" currents are applied by all three of the signal-applying circuits 54-56.
Connections such as shown in Figure 6 may be used to implement a three input AND gate with push-pull logic cells. Two push-pull cells such as the cell 10 may be cascaded, using the connections such as shown in Figure 6 for the "TRUE" sections of the two cells and using complements of such connections for the "FALSE" sections of the two cascaded cells.
Figure 7 shows another method of providing a three input AND gate which is shown being implemented using the single section cell 41 but which may alternatively be implemented using the push-pull cell 10. The single section cell 41 is usable as shown with its output wire 47 connected to the signal-receiving circuit 52 and with its input wire 48 connected directly to the . output wires 57, 58 and 59 of the signal-applying circuits 54-56. In addition, a bias current source 60 is connected between the input wire 48 and ground and applies a current in a direction to flow from the wire 48 to ground. With this arrangement, a current signalling a logic "1" is produced in the output wire 47 only when all three signal- applying circuits 54-56 apply the logic "1" current signal.
To implement a three input push-pull AND gate with the single push-pull logic cell 10, the bias source 60 and a set of connections such as shown in Figure 7 may be used in connection with the section 25 of the cell 10 and an additional bias source and a complementary set of connections may be used in connection with the section 26 of the cell 10.
Cells such as cells 10 and 41 which use diodes can operate at high speeds and use a small number of components, but cannot easily provide for increased fan- *out. In Figure 8, reference numeral 62 generally designates another preferred form of logic cell constructed in accordance with the invention and which provides for increased fan-out and other advantages. The cell 62 utilizes current mirrors to provide output currents to a plurality of additional cells or other forms of signal-receivers. Fan-out is increased by adding more output transistors to the current mirrors.
The cell 62 includes two sections 63 and 64 which, like the sections 25 and 26 of cell 10, are independent but which provide a plurality of outputs. Two outputs are provided in the circuit as shown but it will be understood that a number of additional outputs may be added. It should also be understood that the circuit may be used to advantage when using a single output in that a current mirror provides isolation and insures development of output currents such that any number of cells may be cascaded.
As shown, the sections 63 and 64 have two "T" output wires 67 and 68 and two "F" output wires 69 and 70, shown connected to two signal receiving circuits 71 and
72. The sections 63 also have upper and lower "T" and "F" input wires 73 and 74 which are connected to two signal- applying circuits 75 and 76 which apply logic signals in the form of currents, each of which may, for example, be another current based logic cell or an input or interface circuit operative to supply current-based signals in response to voltage-based signals. As shown, both upper and lower input wires 73 and 74 of cell 62 are directly connected to upper and lower output wires 77 and 78 of signal-applying circuit 75 and also to upper and lower output wires 79 and 80 of signal-applying circuit 76. Each of the signal-applying circuits 75 and 76 may be assumed to be operative to effect flow of a normalized current of a certain magnitude in one direction through its upper output wire while effecting flow of a normalized current of the same magnitude but in the opposite direction through its lower output wire. The input wires 73 and 74 are connected to ground through a pair of diodes 81 and 82 which operate as return diodes in a manner similar to the diodes return diodes 27 and 31 of the cell 10. The input wires 73 and 74 are also connected to ground through a pair of diodes 83 and 84 which are in parallel with the base-emitter junctions of a NPN transistor 85 and a PNP transistor 86. The collectors of transistors 85 and 86 are connected through diodes 87 and 88 to voltage supply terminals 89 and 90 to which positive and negative supply voltages are respectively applied. A first pair of PNP and NPN output transistors 91 and 92 have bases connected to the collectors of transistors 85 and 86, emitters connected to terminals 89 and 90, collectors connected to output wires 67 and 69 and also through bias current sources 93 and 94 to ground. A second pair of PNP and NPN output transistors 95 and 96 have bases connected to the collectors of transistors 85 and 86, emitters connected to terminals 89 and 90, collectors connected to output wires 68 and 70 and also through bias current sources 97 and 98 to ground.
In the operation of the upper section 63 of the cell 62 of Figure 8, current is conducted through the base-emitter junction of transistor 85 in proportion to the sum of currents supplied from the sources 75 and 76 to cause conduction of a corresponding current through the collector-emitter path of transistor 85 and the base- emitter junctions of transistors 91 and 95 so as to cause conduction of corresponding "mirrored" currents through the collector-emitter paths of transistors 91 and 95 to the "T" output wires 67 and 68. Portions of such mirrored currents are drawn off through the bias current sources 93 and 97 while the remaining portions flow through out through the output wires 67 and 68 to the current signal- receiving circuits 71 and 72. When the output transistors 91 and 95 of the upper section 63 are conductive in response to logic "l" currents applied to the input wire 65 of the section, they preferably conduct currents equal to twice the current used to represent a logic "1" while currents equal to the logic "1" current are drawn off through the bias current sources 93 and 97, the currents in the output wires being thereby equal to the logic "1" current.
The operation of the lower section 64 of cell 62 is complementary to that of the upper section 63 and characteristics of the PNP and NPN transistors are preferably matched so as to produce substantially the same "T" and "F" output currents. The characteristics of the diodes 83, 84, 87 and 88 are also matched to the characteristics of the transistor base-emitter junctions with which they are in parallel to obtain accurate and reliable operation in mirroring the input currents and in insuring reliable development of output currents of substantially constant magnitude. In addition to fan-out advantages, the circuit 62 allows operation of as many cells in cascade as may be desired.
Figure 9 is a circuit diagram of another logic cell 100 which is constructed in accordance with the invention. The illustrated cell 100 includes emitter coupled transistors which operate in a manner similar to those of ECL circuits to obtain advantages similar to those obtained from ECL circuits and which, in addition, respond to input currents to obtain the advantages of the above described circuits of the invention.
The illustrated cell 100 is a three input, two output cell which receives push-pull inputs from three current signal-applying circuits 101, 102 and 103, an input wire 105 of the circuit 100 being connected to "TRUE" outputs of the circuits 101-103 and a second input wire 106 being connected to "FALSE" outputs of the circuit 101-103.
The two outputs of cell 100 are connected to two current signal-receiving circuits 107 and 108. As shown, two "TRUE" outputs are connected through wires 109 and 110 to circuits 107 and 108 and two "FALSE" outputs are connected through wires 111 and 112 to the circuits 107 and 108.
The input wires 105 and 106 are connected through resistors 115 and 116 to voltage supply terminals 117 and 118 and are also connected through level shifter circuits 119 and 120 to base electrodes of a first pair of transistors 121 and 122 and base electrodes of a second pair of transistors 123 and 124. The collectors of transistors 121 and 122 are connected to the "FALSE" output wires 111 and 112 and are also connected through current sources 125 and 126 to a voltage supply terminal 128. The collectors of transistors 123 and 124 are connected to the "TRUE" output wires 109 and 110 and are also connected through current sources 129 and 130 to the voltage supply terminal 128. The emitters of all four transistors 121-124 are connected together and through a current source 132 to a voltage supply terminal 134.
Operation of the cell involves the generation of a small voltage difference between the voltage at the bases of the pair of transistors 121 and 122 and the voltage at the bases of the pair of transistors 123 and 124, to cause conduction of one pair and to cut off conduction of the other pair. When one pair of transistors conducts, each collector of the conducting pair sinks a current equal to 2i0, where i0 is a normalized current which comes from the corresponding one of the bias current sources 125, 126, 129 or 130 and where another cuurent equal to i0 comes from the corresponding one of th output wires 109-112. This corresponds to a logic 0.
On the other side, where a pair of transistors are cut off, the corresponding pair of the bias current sources 125, 126 or 129, 130 supplies a current to the next gate which represents a logic 1.
The voltage difference across the emitter coupled transistors is generated from the input currents in wires 105 and 106 and is shifted in level by the level shifters 119, 120 before application to the base electrodes of the emitter coupled transistors. Input currents which correspond to "TRUE" inputs are summed together and are used to generate a small voltage of one polarity on one side of the emitter coupled pair of transistors while input currents corresponding to "FALSE" inputs are summed together and used to generate another small voltage of the opposite polarity on the other side of the emitter coupled pair.
The resistors 115 and 116 are connected to the voltage supply terminals 117 and 118 to supply small negative and positive bias voltages, so chosen that the voltage generated by the "FALSE" input currents is greater than that generated by the "TRUE" input currents except for the case when all the currents on the "TRUE" side are directed into the circuit and all the "FALSE" input currents are directed out of the circuit. This case corresponds to an input of all logic l's and is the only valid logic input which will cause the transistors 123 and 124 of the illustrated circuit to conduct while cutting off conduction of the transistors 121 and 122 on the left side. The two-level shifters 119 and 230 translate the voltage generated by the summed input currents, operating to subtract a constant from the voltage on each side. They operate to keep the emitter coupled resistors from going into saturation to insure high speed operation of the circuit.
It will be understood that the circuit of Figure 9 may be extended to provide four outputs, rather than two, or as many additional outputs as may be desired. It is also noted that multiple collector transistors may be used. The internal mirror arrangement is such as guarantee substantially equal distributions of bias currents. Very small voltage swings are required, and the corresponding required bias voltages are also small.
The level shifters are advantageous in providing protection to insure that the collector voltages stay out of saturation. Figures 10, 11 and 12 illustrate three representative level shifter circuits 140, 141 and 142 which may be used as the level shifters 119 and 120 in the circuit of Figure 9.
In Figure 10, an input wire 143 is connected through a Zener diode 144 to an output wire 145. The input wire is also connected through a resistor 147 to a voltage supply terminal 148 while the output wire 145 is connected through a resistor 149 to a voltage supply terminal 150. The voltage supply terminals 148 may,' for example, be tied to the voltage supply terminals 128 and 134 when the circuit 140 is used as the level shifter 119 or level shifter 120. The input wire 143 may be connected to the wire 105 or wire 106 while the output wire 145 may be connected to the base electrodes of the transistors 121 or 122 or the base electrodes of the electrodes 123 and 124. A substantially constant voltage drop is produced across the Zener diode to down-shift the level of the voltage applied to the input wire 143 to that developed at the output wire 145.
The level shifter circuit 141 of Figure 11 is the same as in Figure 10 except that a simple resistor 152 is substituted for the Zener diode 144. With a substantially constant current being applied to the circuit, the voltage drop across the resistor 152 is also substantially constant.
In the circuit 142 of Figure 12, a transistor 154 and a pair of diodes 155 and 156 are used in place of the resistor 147 and Zener diode 144 or resistor 152 of the circuits of Figures 10 and 11. The base of the transistor 154 is connected to the input wire 143, the collector of the transistor 154 is connected to the voltage supply terminal 148 and the diodes 155 and 156 are • connected in series between the emitter of the transistor 154 and the output wire 145. In this circuit, a "long emitter-follower" is provided in which the diodes provide a subtantially constant current and which operates to produce a substantially constant voltage drop while passing the input current from the input wire 143 to the output wire 145. The diffusion capacitances of the diodes act like speed-up capacitors.
With the current-based and directly connectable logic cells of the invention, very high operating speeds can be obtained, primarily as a result of the fact that they use very small voltage swings in combination with relatively large currents to obtain effective shunt impedances which are quite low to minimize delays from capacitances. The cells do not operate in the saturation region. Operating speeds are further enhanced from the two wire push-pull configurations of the invention which require no cascaded inverters in implementing all logic functions. The circuits of the invention are quite simple and can be advantageously incorporated in integrated circuits. They can be readily interfaced with input and output circuits or with ECL or other types of logic circuits located either on the same chip or externally located. The design of the cells is such as to promote stable, reliable operation and to obtain other advantages which will be apparent from the foregoing descrition, taken in conjunction with the drawings.
It will be understood that modifications and variations may be effected without departing from the spirit and scope of the novel concepts of the invention.
We claim:

Claims

1. A current-based logic cell, comprising: input means, output means, and processing means coupled to said input and output means, said input means including an input wire arranged for direct application of a plurality of input signals thereto, each input signal being a current, and said processing means being responsive to an algebraic summation of currents flowing in one direction in said input wire to control development at said output means of one or the other of first and second forms of output signals.
2. A current-based logic cell as defined in claim 1, wherein said output means includes an output wire and wherein said output signal includes a current having a magnitude which is a function of said algebraic summation of current flows in said input wire.
3. A current-based logic cell as defined in claim 2 arranged for connection to a second cell having input means of similar form and including an input wire, wherein said output wire is directly connectable to said input wire of said second cell to directly apply an input current thereto.
4. A current-based logic cell as defined in claim 1, further including biasing means associated therewith for applying a biasing current component to said input wire.
5. A current-based logic cell as defined in claim 1, wherein said output means includes an output wire, said processing means including biasing means for applying a biasing current component to said output wire.
6. A current-based logic cell as defined in claim 5, said output signal being a current which is an algebraic summation of said biasing current and said algebraic summation of currents in said input wire.
7. A current-based logic cell as defined in claim 1, said processing means including first means responsive to the net current flow in said input wire in one direction to control development of one or the other of said forms of output signals, and second means for providing a path for current flow in said input wire in an opposite direction.
8. A current-based logic cell as defined in claim 7, wherein said output means includes an output wire, said first means comprising first unidirectional conduction means connected between said input and output wires, and said second means comprising unidirectional conduction means connected to said input wire.
9. A current-based logic cell as defined in claim 1 further including means for operation as a push- pull cell, wherein said input wire of said input means forms a first input wire for direct application of a plurality of input signals thereto and wherein said input means includes a second input wire arranged for direct application of a second plurality of input signals thereto with each input signal of said second plurality of input signals is a current applied in a direction opposite the direction of application of a corresponding current forming the input signal to said first input wire, said processing means being responsive to an algebraic summation of currents flowing in said opposite direction in said input wire to control development at said output means of a second output signal of one of first and second forms.
10. A current-based push-pull logic cell as defined in claim 9, wherein said output means operate in push-pull and include first and second output wires with an output current signal of said first form being provided by a current flow through said first wire away from said processing means and a simultaneous current flow through said second output wire toward said processing means and with an output current signal of said second form being provided by a current flow through said first wire toward said processing means and a simultaneous current flow through said second output wire away from said processing means.
11. A current-based push-pull logic cell as defined in claim 10 arranged for connection to a following cell having input means of a similar form and including first and second input wires, wherein said output wires are directly connectable to said input wires of said following cell to directly apply input currents thereto.
12. A current-based push-pull logic cell as defined in claim 11, wherein said first and second input wires are respectively connectable directly to first and second output wires of a preceding cell and wherein said first and second output wires are respectively connectable directly to first and second input wires of said following cell to perform a logic AND function.
13. A current-based push-pull logic cell as defined in claim 11, wherein said first and second input wires are respectively connectable directly to first and second output wires of a preceding cell and wherein said first and second output wires are respectively connectable directly and in crossed relation to second and first input wires of said following cell to perform a logic NAND function.
14. A current-based push-pull logic cell as defined in claim 11, wherein said first and second input wires are respectively connectable directly and in crossed relation to second and first output wires of a preceding cell while said first and second output wires are respectively connectable directly and in crossed relation to second and first input wires of said following cell to perform a logic OR function.
15. A current-based push-pull logic cell as defined in claim 11, wherein said first and second input wires are respectively connectable directly and in crossed relation to second and first output wires of a preceding cell while said first and second output wires are respectively connectable directly to first and second input wires of said following cell to perform a logic NOR function.
16. A current-based logic cell as defined in claim 2 , wherein said output means includes at least one additional output wire to provide a plurality of output wires, and wherein said processor means is responsive to an algebraic summation of currents flowing in one direction in said input wire to control development of an output signal at each of said output wires as a function of said algebraic summation of current flows into said input wire.
17. A current-based logic cell as defined in claim 16, wherein said processing means includes mirror circuit means for developing each output signal in each of said plurality of output wires.
18. A current-based logic cell as defined in claim 16, wherein said mirror circuit means includes first transistor means providing a base-emitter path responsive to the current in said input wire and additional transistor means controlled by said first transistor means and providing a plurality of output electrodes connected to said output wires.
19. A current-based push-pull logic cell as defined in claim 9, wherein said output means operate in push-pull and include a plurality of pairs of output wires each pair of output wires including a first output wire and a second output wire with an output current signal of said first form being provided by a current flow through said first wire away from said processing means and a simultaneous current flow through said second output wire toward said processing means and with an output current signal of said second form being provided by a current flow through said first wire toward said processing means and a simultaneous current flow through said second output wire away from said processing means.
20. A current-based push-pull logic cell as defined in claim 19 arranged for connection to a plurality of following cells having input means of a similar form and including first and second input wires, wherein said output wires of each of said pairs of output wires are directly connectable to said input wires of one of said following cells to directly apply input currents thereto.
21. A current-based push-pull logic cell as defined in claim 20, wherein said processing means includes mirror circuit means for developing each output signal in each output wire of each of said plurality pairs of output wires.
22. A current-based push-pull logic cell as defined in claim 21, wherein said mirror circuit means includes first transistor means providing a base-emitter path responsive to the current in said input wire and additional transistor means controlled by said first transistor means and providing a plurality of output electrodes, each output wire of each of said plurality of pairs of output wires being connected to one of said output electrodes.
23. A current-based push-pull logic cell as defined in claim 19, wherein said processing means include output transistor means providing a plurality of output electrodes, each output wire of each of said plurality of pairs of output wires being connected to one of said output electrodes, and input transistor means responsive to currents flowing in said first and second input wires to control conduction of said output transistor means.
24. A current-based push-pull logic cell as defined in claim 23, wherein said output transistor means include first output transistor means providing output electrodes connected to said first output wires of said plurality of pairs of output wires and second output transistor means providing output electrodes connected to said second output wires of said plurality of pairs of output wires, and wherein said input transistor means include first and second input transistor means for respectively controlling conduction of said first and second output transistor means.
25. A current-based push-pull logic cell as defined in claim 20, wherein said processing means include first and second transistor means having input and output electrodes, and control means coupling said input wires to said input electrodes to control conduction of said first and second transistor means, said first transistor means providing a first plurality of output electrodes connected to said first output wires of said plurality of pairs of output wires, and said second transistor means providing a second plurality of output electrodes connected to said second output wires of said plurality of pairs of output wires.
26. A current-based push-pull logic cell as defined in claim 25, wherein said control means include coupling means between said first and second input electrodes and said first and second input wires.
27. A current-based push-pull logic cell as defined in claim 26, wherein said coupling means include first and second level shift circuits for shifting the levels of the voltages at said first and second input electrodes in relation to the levels of the voltages at said first and second input wires while applying currents to said electrodes corresponding to the currents in said first and second input wires.
28. A current based push-pull logic cell as defined in claim 27, wherein said first and second level shift circuits include Zener diode means in series between said first and second input wires and said first and second input electrodes. 29. A current based push-pull logic cell as defined in claim 27, wherein said first and second level shift circuits include resistance means in series between said first and second input wires and said first and second input electrodes.
29. A current based push-pull logic cell as defined in claim 27, wherein said first and second level shift circuit include level shift transistor means and diode means, said level shift transistor means including base electrodes coupled to said input wires and emitter electrodes coupled to said input electrodes of said first and second transistor means.
30. A method of forming computer logic architecture, comprising the steps of providing a plurality of current-based push-pull logic cells each cell including first and second input wires, at least one pair of first and second output wires and processing means for controlling current flows in said first and second output wires of each pair in accordance with currents flowing in said first and second input wires, and providing direct conductive connections between output wires of one cell and input wires of a following one of said cells which are either in the form of direct conductive uncrossed connections of said first and second output wires of one cell to first and second input wires of said following cell or in the form of direct conductive crossed connections between said first and second output elecrtrodes of one cell and said second and first input electrodes of the following cell.
PCT/US1990/002554 1989-05-05 1990-05-07 Current-based computer logic architecture WO1990013944A1 (en)

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Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, Volume 20, No. 4, September 1977, F.W. OLSEN: "Digitally Controlled Precision Current Source", see pages 1330 and 1331. *

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