WO1990007849A1

WO1990007849A1 - Communication adapter

Info

Publication number: WO1990007849A1
Application number: PCT/EP1988/001213
Authority: WO
Inventors: Hans Johan Jozef Busschaert; Dirk Herman Lutgardis Cornelius Rabaey; Peter Paul Frans Reusens
Original assignee: Alcatel N.V.; Bell Telephone Manufacturing Company, Naamloze Vennootschap
Priority date: 1988-12-24
Filing date: 1988-12-24
Publication date: 1990-07-12
Also published as: EP0408561A1; AU624658B2; AU4578489A

Abstract

A multi-standard communication adapter (MSRA) for interfacing a low speed communication device (TP), e.g. a user station, and a high speed communication device (NP), e.g. an Integrated Services Digital Network (ISDN). Both these communication devices are allowed to transmit signals having electrical and functional interface characteristics which may be chosen amongst a wide variety of possible electrical and functional interface characteristics. The communication adapter is integrated in an electronic chip and is able to perform the different rate adaptation schemes owing to its programmable constituent parts (TXFR, TXUS, RXUS, RXFR, BUSA, BAUDA). The programmation of the communication adapter is realized by means of a host microprocessor external (PP) to the chip and which may also be used to temporarily store data transmitted between the two communication devices as well as to transmit information to or receive information from these devices. The communication adapter further includes a Baudrate generator (BAUDA) to control the clock signal on the low speed side (TP) and means to perform a self-test.

Description

COMMUNICATION ADAPTER.

The present invention relates to a communication adapter including a conversion device able to convert first signals received from a first communication device

connected to said conversion device and transmitting said first signals according to first electrical and functional interface characteristics into second signals to be sent to a second communication device also connected to said conversion device and able to receive said second signals according to second electrical and functional interface characteristics.

Such an adapter is already known, e.g. from the article entitled "Subsets, Terminals, and Terminal Adapters for the public ISDN" by D. Adolphs et al, published in "Electrical Communication" VOLUME 61, No 1, 1987, pages 72 to 80. Therein, the communication adapter is built on an interface printed circuit board and two of such boards may be inserted in a so-called "terminal adapter". Each of these two communication adapters is able to operate

according to one rate adaptation scheme, i.e. to convert first signals with first interface characteristics into second signals with second interface characteristics. One of these known communication adapters is for instance able to convert the interface characteristics X.21 class 4 or 2. A kilobit/ second data rate of a user station into 64 kilobit/ second B-channel signals of an Integrated Services Digital Network (ISDN) interface, whilst another communication adapter is able to convert the interface characteristics X.21 class 30 or 64 kilobit/ second data rate of another user station into the same 64 kilobit/ second B-channel signals of this ISDN interface. Both these conversions correspond to the rate adaptation scheme based on the International Consultative Committee for

Telegraphy and Telephony (CCITT) Recommendation X.30.

A drawback of this known communication adapter is that it can only perform one rate adaptation scheme and that the interface board onto which it is built has thus to be replaced each time the user station or at least the interface characteristics of the signals thereof are modified. Furthermore, the described solution of including two communication adapters in a same terminal adapter box necessarily increases the power dissipation and the volume occupied by this adapter.

This is avoided by the solution described in the article entitled "THE UNIVERSAL ISDN TERMINAL ADAPTER" by P.E. Weston published as "Conference Record" of "GLOBECOM '86: IEEE Global Telecommunications Conference.

Communications Broadening Technology Horizons.", Ref.

(Cat. No 86CH2298-9), Houston, TX, USA., 1-4 Dec. 1986 (New York, USA: IEEE 1986), pages 1434 to 1438, VOL.3.

Therein, the conversion device is integrated in a Very Large Scale Integration (VLSI) device or electronic chip and may be programmed in accordance with parameters which define said first electrical and functional interface characteristics amongst a plurality of different possible first electrical and functional interface characteristics.

However, this last known conversion device is only able to handle one type of said second electrical and functional interface characteristics.

An object of the present invention is to provide a communication adapter of the last mentioned known type but which is even more universal, i.e. a single communication adapter which is able to convert first signals with first interface characteristics into second signals with second interface characteristics, these being selected out of at least two sets of first or of second electrical and functional interface characteristics.

According to the invention, this object is achieved due to the fact that said conversion device includes, connected between said first and said second communication devices, the cascade connection of first programmable converter means to which the first mentioned parameters are applied and second programmable converter means which are able to be programmed in accordance with second parameters which define said second electrical and functional

interface characteristics amongst a plurality of different possible second electrical and functional interface

characteristics.

In this way, by a suitable choice of the first and the second parameters the same communication adapter may operate according to different rate adaptation schemes, i.e. the first and/ or the second communication devices connected thereat may be changed whilst only the

programmation of the first and/ or the second programmable converter means of the communication adapter has then respectively to be modified and the communication adapter itself has not to be changed.

Another characteristic feature of the present invention is that said second electrical and functional interface characteristics at least consist in transmitting said second signals as standard information channels of a Time Division Multiplex (TDM) link.

Still another characteristic feature of the present invention is that said first and second parameters are stored into said first and second programmable converter means respectively under the control of processor means.

Still another characteristic feature of the present invention is that said communication adapter further includes a second conversion device of the same type as the first mentioned conversion device, operating independently thereof and connected in the opposite direction between said second and first communication devices.

In this way, the above universal communication adapter operates in a fully bidirectional way.

Yet another characteristic feature of the present invention is that an output of said second converter means is interconnectable with an input of said third converter means and that said communication adapter includes internal test means able to generate a random test signal having one of said first electrical and functional interface

characteristics, said test means being also able to

transmit said test signal to an input of said first

converter means and to compare said test signal with a return signal received in response at the output of said fourth converter means, said test signal being successively transmitted through said first, second, third and fourth converter means via said interconnection.

In this way, a self test of at least the

communication adapter may be easily performed at any moment and without requiring external test devices.

Still another characteristic feature of the present invention is that said communication adapter is integrated in an electronic chip.

The integration of a multi-standard communication adapter in a single electronic chip reduces substantially the volume occupied thereby. Moreover, the use of, e.g., the known CMOS technology allows such an integration since the power dissipated is limited to acceptable values.

The above mentioned and other objects and features of the invention will become more apparent and the

invention itself will be best understood by referring to the following description of an embodiment taken in conjunction with the accompanying drawings wherein :

Fig. 1 shows a block diagram of a communication adapter MSRA according to the invention;

Fig. 2 shows a telecommunication system using two communication adapters MSRA of Fig. 1; and

Fig. 3 shows other applications of the

communication adapters MSRA of Fig. 1 in a

telecommunication system.

The communication adapter MSRA shown in Fig. 1 is a bidirectional Multi-Standard Rate Adapter for digital telecommunication systems. It is a 3-port device connected to the outside world via:

- a terminal port TP including a data input terminal TXD, a data output terminal RXD, signalling input terminals generaly indicated by TXS, signalling output terminals generaly indicated by RXS, a transmitter clock input terminal TCI, a transmitter clock output terminal TCO and a receiver clock output terminal RCO;

- a 64 kilobit/ second network port NP including a

transmit terminal TX, a receive terminal RX, a clock terminal CL and a frame terminal FR; and

the microprocessor port PP including a microprocessor data bus terminal PD and control terminals generally indicated by UT.

It is also provided with two clock reference terminals CRI and CRO across which an external crystal XTAL may be connected to control an internal oscillator as will be described later.

It mainly comprises three basic sections:

- a transmit path circuit TXP which couples the data input terminal TXD to the transmit terminal TX;

- a receive path circuit RXP which couples the receive terminal RX to the data output terminal RXD; and

- a control section CRTP which is connected to the clock terminals TCI, TCO, RCQ, CRI, CRO, CL, the frame terminal FR and the signalling terminals TXS and RXS.

The transmit path circuit TXP includes, between the terminals TXD and TX, the series connection of a first Universal Synchronous/ Asynchronous Receive/ Transmit

(USART) device TXUS, a transmit buffer TXFI and a transmit framer TXFR. TXUS, TXFI and TXFR are interconnected by unidirectional internal busses and, as will be described later, TXUS and TXFR are programmable in order to be able to operate according to various electrical and functional interface characteristics of the signals handled thereby.

The receive path circuit RXP, analogous to TXP, includes, between the terminals RX and RXD the series connection of a receive framer RXFR, a receive buffer RXFI and a second Universal Synchronous/ Asynchronous Receive/ Transmit (USART) device RXUS. RXFR, RXFI and RXUS are interconnected by internal unidirectional busses and, as for TXFR and TXUS, RXFR and RXUS are also programmable.

On the one hand_* the transmit path circuit TXP of the communication adapter MSRA is able to convert data signals transmitted from a user station, such as TEM or TES shown in Fig. 2 and connected to the data input terminal TXD of the, terminal port TP, via a low speed link., such as LSM or LSS respectively of Fig. 2, into information signals which are loaded in information channels

transmitted to a network which is for instance an

Integrated Services Digital Network (ISDN), such as DSN shown in Fig. 2 and connected to the transmit terminal TX of the network port NP, via a high speed link, such as HSM and HSS of Fig. 2.

On the other hand, the receive path circuit RXP of the MSRA is able to perform the inverse operation, i.e. to convert information signals contained in information channels received from the network DSN to the receive terminal RX of the network port NP via a high speed link HSM or HSS, into data sάgnals transmitted to the user station TEM or TES respectively via the data output terminal RXD of the terminal port TP and the corresponding low speed link LSM or LSS.

The low speed side of the communication adapter MSRA, including the USARTs TXUS and RXUS, is able to handle different signals to be send (RXUS) to. or received (TXUS) from the user station having for instance as main

electrical and functional interface characteristics :

- a bitrate ranging from 75 bit/ second up to 64 kilobit/ second synchronous or up to 19.2 kilobit/ second

asynchronous, and

- a format corresponding to a 7 bit or an 8 bit

synchronous or asynchronous (with start and stop bits) communication protocol or the HDLC (High level Data Link Control) protocol.

The high speed side of the MSRA, including the framers TXFR and RXFR, is able to handle, i.e. to generate (TXFR) or to analyze (RXFR), different information channels having for instance as main electrical and functional interface characteristics a bitrate of 64 kilobit/ second and of which the format corresponds for instance to the rate adaptation scheme :

- ECMA 102 recommended by the European Computer

Manufacturers Association (ECMA) or its equivalent CCITT X.30/ X.31 recommended by the International Consultative Committee for Telegraphy and Telephony (CCITT);

- DMI (Digital Multiplex Interface) modes 0 to 3; or

- other byte synchronous based data communication

protocols or rate adaptation schemes.

As will be described below, the high speed link is able to transmit a carrier signal having a frequency of, e.g., 64, 256 or 2,000 kilohertz and the 64 kilobit/ second information channels are transmitted thereon as part of a frame of a Time Division Multiplex (TDM) signal. The type of TDM signal, i.e. with 1, 4 or 32 information channels per frame, used to transmit these information channels between the MSRA and the network may also form part of the electrical and functional interface characteristics

thereof.

The control section CRTP includes a transmit handshake control circuit TXHA, a receive handshake control circuit RXHA, a bus adapter BUSA, a clock synchronization device and Baudrate generator BAUDA, a microprocessor interface circuit UPIF and an internal mode register or parameter storage circuit INMR of which the functions are described below.

Signalling from the user station to the network occurs via the series connection of the low speed link, the signalling input terminals TXS of the terminal port TP, the transmit handshake control circuit TXHA of the control section CRTP, an unidirectional internal bus linking TXHA and the transmit buffer TXFI, this latter buffer TXFI and the transmit framer TXFR both of the transmit path circuit TXP and via the internal bus linking them, the transmit terminal TX of the network port NP and the high speed link.

In the other direction, signalling is received from the network and transmitted to the user station via the series connection of the high speed link, the receive terminal RX of the network port NP, the receive framer RXFR and the receive buffer RXFI both of the receive path circuit RXP and via the internal bus linking them, another unidirectional internal bus linking RXFI and the receive handshake control circuit RXHA of the control section CRTP, this latter circuit RXHA, the signalling output terminals RXS of the terminal port TP and the low speed link.

It is to be noted that the USARTs TXUS and RXUS only handle data whilst the buffers TXFI and RXFI and the framers TXFR and RXFR handle both data and signalling.

The bus adapter BUSA of the control section CRTP is connected to both the dock terminal CL and to the frame terminal FR of the network port NP and receives

therethrough respective clock and frame signals from the network connected thereat. These clock and frame signals control the operation of BUSA which is further connected to the framers TXFR and RXFR via respective internal busses. More in detail, the bus adapter BUSA controls the moment at which the 64 kilobit/ second channel information - or any sub-channel of 32, 16 or 8 kilobit/ second or super-channel of 128 kilobit/ second - may be loaded onto or unloaded from the high speed link by the transmit TXFR or by the receive RXFR framers respectively. The bus adapter BUSA is programmable and is able to handle a TDM carrier signal as mentioned above and which has for instance a frame

frequency of:

- 64 kilohertz according to standards currently used in codec interfaces;

- 256 kilohertz compatible with interfaces currently available from Mitel; or

- 2 Megahertz compatible with V* interfaces currently available from Alcatel.

Each frame of the TDM signal is subdivided into either 1 (codec), 4 (Mitel) or 32 (Alcatel) channels of 64 kilobit/ second and only one channel out of each frame of this TDM signal is handled by the MSRA.

Up to 256 multi-standard rate adapters MSRAs may be connected to a same high-speed link or TDM highway without requiring any additional hardware therein and under the control of a single host microprocessor (not shown)

connected to the microprocessor port PP of each of these MSRAs.

As will also be described later, when two MSRAs MSRAM and MSRAS are interconnected through a network DSN such as shown in Fig. 2, the clock synchronization device and Baudrate generator BAUDAM of the control section CRTP of one of these MSRAs, rsay MSRAM, generates Synchronous Clock Adjust information SCA which is sent to the Clock synchronization device and Baudrate generator BAUDAS of the remote MSRA, say MSRAS, which analyzes this received information SCA.

To this end_* the clock synchronization device and

Baudrate generator BAUDA is connected to both the transmit framer TXFR of the transmit path circuit TXP and to the receive framer RXFR of the receive path circuit RXP via internal links. The clock synchronization device and Baudrate generator BAUDA is further connected to the transmitter clock input terminal TCI, the transmitter clock output terminal TCO and the receiver clock output terminal RCO of the terminal port TP through which it may send (TCI, TCO)/ receive (RCO) clock signals to/ from the user station connected to this terminal port TP. These clock signals are used on the low speed link and control the transmission of the data signals flowing through the data terminals TXD and RXD of the terminal port TP . BAUDA is also connected to the above mentioned clock reference terminals CRI and CRO.

The MSRA further interfaces with a host

microprocessor (not shown) via a microprocessor bus

connected to the microprocessor port PP. This host

microprocessor may be of a suitable commercially available type, e.g. 8088 of Intel, 6502 of Motorola or any

compatible thereto - the type being selected by means of straps (not shown) - with its data transmitted/ received via the microprocessor data bus terminal PD and its control signals via the microprocessor control terminals UT of the microprocessor port PP. The control terminals UT are connected to the microprocessor interface circuit UPIF of the control section CRTP which, by means of interrupts, controls the operation of other constituent parts of the MSRA to which UPIF is connected via a network of internal busses shown in Fig. 1 : The microprocessor data bus terminal PD is also connected to this internal network of busses. As will be indicated below the microprocessor port PP is mainly used to transmit parameters from the host microprocessor to the parameter storage circuit INMR, data between this host microprocessor and the buffers TXFI and RXFI and signalling between this host microprocessor and the handshake control circuits TXHA and RXHA.

The parameter storage circuit INMR of the control section CRTP of the MSRA stores the above parameters received from the host microprocessor under control of the microprocessor interface circuit UPIF. These parameters define the electrical and functional interface

characteristics of both the user station and the network, i.e. on the rate adaptation scheme to be performed by the MSRA. More in detail, they control the operations of the programmable framers TXFR and RXFR, of the programmable USARTs TXUS and RXUS, of the clock synchronization device and Baudrate generator BAUDA, and of the programmable bus adapter BUSA to which they are transmitted via an internal network of control lines (not shown) linking these elements to the parameter storage circuit INMR. In a preferred embodiment, the parameter storage cicruit INMR is

distributed over the elements which then only store

corresponding parameters so that this circuit INMR does not exist as such.

The parameters indicate :

- to the framers TXFR and RXFR which rate adaptation scheme (ECMA 102, DMI 0, DMI 1, DMI 2, ...) is used;

- to the USARTs TXUS and RXUS which communication protocol (synchronous, asynchronous, HDLC, ...) is used;

- to the clock synchronization device and Baudrate

generator BAUDA which bitrate (19.2 to 64 kilobit/ second) is used by the user station; and

- to the bus adapter BUSA which kind of TDM highway

(codec, Mitel, Alcatelc ...) is used. In this way, when for instance the user of the multi-standard rate adapter MSRA changes the configuration (characteristics) of his telecommunication system (user station, network, protocol, ...), the same MSRA may still be used in the new configuration. The user only has to change, via his host microprocessor, the parameters stored in the parameter storage means, and the constituent parts (TXFR, RXFR, BUSA, TXUS, RXUS) of the MSRA will operate according to this new configuration indicated thereto by these parameters.

Data and signalling flows are possible in both directions between the terminal port TP and the network port NP via TXFR/ RXFR, TXFI/ RXFI and TXUS/ RXUS, between the terminal port TP and the microprocessor port PP via TXUS/ RXUS, and data flow only between the microprocessor port PP and the network port NP via TXFR/ RXFR and TXFI/ RXFI. It is also possible to send information

simultaneously from the terminal port TP to both the network port NP and the microprocessor port PP as well as from the network port NP to both the terminal port TP and the microprocessor port PP.

The buffer TXFI/ RXFI is able to request for transmitting/ receiving data to/ from the host

microprocessor. In that case, they operate with. a certain hysteresis. More in detail, the capacity of a buffer TXFI/ RXFI is of 16 bytes and for instance TXFI will only request for transmitting data from the host microprocessor when it is almost empty, i.e. when its content is less than or equal to 4 bytes, and this request is stopped when it is full, i.e. when it contains 16 bytes. In this way, the occupancy (load) of the host microprocessor is reduced.

In case the rate adaptation scheme used requires more data storage than that available in the buffers TXFI and RXFI, data may by temporarily transferred via the microprocessor data bus terminal PD to an external RAM memory (not shown) under control of the host

microprocessor.

Summarizing, the transmit buffer TXFI of the communication adapter MSRA receives data signals from the USART TXUS and signalling or control signals from the transmit handshake control circuit TXHA. This transmit buffer TXFI latches all these received signals and

transmits them to the transmit framer TXFR at a suitable moment.

The transmit framer TXFR then arranges these signals and those received from the the clock synchronization device and Baudrate generator BAUDA according to a

predetermined 64 kilobit/ second information channel format corresponding to the required rate adaptation scheme.

Under the control of the bus adapter BUSA the transmit framer TXFR "writes" this information channel onto the high speed link via the transmit terminal TX. This writing occurs at a suitable moment which is for instance function of the channel number allocated to this adapter MSRA when a multi- channel TDM transmission is realized.

In the other direction the receive framer RXFR "reads", under the control of the bus adapter BUSA, an information channel in each incoming frame of the TDM signal arriving at the receive terminal RX of the MSRA.

The information contained in this channel is extracted therefrom by RXFR which transmits it either to the receive buffer RXFI (data and signalling) or to the the clock synchronization device and Baudrate generator BAUDA (clock synchronous adjust information SCA). RXFI then distributes the data signals to the USART RXUS and the signalling to the receive handshake control circuit RXHA.

Due to the MSRA being bidirectional, it can readily perform a self test using a built-in random signal

generator able to send a test data signal to an input of the USART TXUS and to rreceive in return a test data signal from an output of the USART RXUS. Indeed, one merely has to establish a temporary internal test connection between an output of TXFR and an input of RXFR to complete the necessary loop.

By comparing the sent and the returned test signals, one can detect malfunctions of the MSRA. Moreover, the test loop may even be extended through the high speed link to a remote device connected thereto instead of a direct connection between TXFR and RXFR.

The operation of the communication adapter MSRA and more particularly of the clock synchronization device and Baudrate generator BAUDA thereof is described more in detail hereafter by means of an example illustrated by Fig. 2 which shows an application of MSRA in a communication system. In this example, two communication adapters MSRAM and MSRAS are used to allow the communication between a user station TEM and a remote user station TES via a common digital switching network DSN of the ISDN type. The user station TEM is connected to MSRAM via its low speed link LSM and the remote user station TES is connected to the remote MSRAS via the low speed link LSS of the latter. The switching network DSN is connected to both MSRAM and MSRAS via the high speed links HSM and HSS thereof respectively.

The user station TEM is provided with a local clock generator which supplies a clock signal CLKM, e.g. of 19.2 kilohertz, on the part of the low speed transmission link LSM connected to the transmitter clock input terminal TCI of MSRAM. Because of its local clock generator, the user station TEM may be considered as being the master user station for the signals transmitted therefrom to the user station TES, whilst the latter TES, which is not provided with any local clock generator, is the slave user station for these signals. As will be described below, a clock signal CLKS identical to the clock signal CLKM will be applied on the part ofzthe low speed link LSS connected to the receiver clock output terminal RCO of the remote MSRAS.

This concerns only the signals transmitted from the user station TEM to the user station TES. For the signals transmitted in the other direction, i.e. from the user station TES to the user station TEM, the clock signal on the low speed links LSM and LSS connected to MSRAM and to MSRAS respectively must not necessarily be generated in the same way. Indeed, TES may then for instance be the master user station whilst TEM is the slave user station, or other systems (given later) to generate this clock signal may be used.

To simplify the following description, only the signals transmitted from the master user station TEM to the slave user station TES are considered hereafter.

The clock synchronization device and Baudrate generator BAUDAM of the communication adapter MSRAM

receives the local clock signal CLKM from the master user station TEM via the transmitter clock input terminal TCI of MSRAM and receives a master clock signal CLKN, e.g. of 4 Megahertz, from the switching network DSN via the clock terminal CLM of MSRAM to which part of the high speed link HSM is connected. BAUDAM then derives an exact 19.2 kilohertz reference clock signal from the received master clock signal CLKN and checks the accuracy of the local clock signal CLKM by comparing it with this reference clock signal. Any deviation of the frequency of CLKM from the exact 19.2 kilohertz reference clock signal is detected by BAUDAM which then generates a corresponding Synchronous Clock Adjust information SCA. This information SCA is transmitted via the transmit terminal TX of MSRAM and the high speed link HSM to the switching network DSN. From there, the information SCA is transmitted further to the clock synchronization device and Baudrate generator BAUDAS of the remote MSRAS via the high speed link HSS and the receive terminal RX of MSRAS. On the other hand, BAUDAS also receives the master clock signal CLKN from the

switching network DSN via the high speed link HSS and the clock terminal CLS of MSRAS. By combining SCA and CLKN, BAUDAS generates a clock signal CLKS which is identical to the above clock signal CLKM. The clock signal CLKS is supplied to the slave user station TES via the receive clock output terminal RCO of MSRAS and the low speed link LSS. In this way, a same clock signal CLKM = CLKS is used on both the low speed links LSM and LSS of the master user station TEM and of the slave user station TES respectively.

When, for instance, the clock signal CLKM is f aste r than the re f eren ce c lock signal o f 19 . 2 ki lo hertz, the rate of data bits transmitted from the master user station TEM to the slave user station TES is also larger than the one which normally appears on the low speed links of LSM and LSS. To avoid loss of data in the MSRAM and thus also at the slave user station TES due to this too fast clock signal CLKM (and thus also CLKS), the channel format used on the high speed links HSM and HSS is such that it carries, additionally to the normal number of data bits, e.g. 48, an extra data bit which will be transmitted from MSRAM to MSRAS. From MSRAS, these 48 + 1 bits of data are transmitted to the slave user station TES according to the clock signal CLKS. On the low speed link LSS, the rate of data bits is increased owing to this extra data bit so that no data is lost during the transmission from TEM to TES.

In the above example, the communication system operates in a so-called "network independent clock mode". However, when neither the user station TEM nor the remote user station TES is provided with a local internal clockgenerator, the clock signal on the low speed links LSM and LSS is directly derived from the master clock signal CLKN supplied by DSN to both MSRAM and MSRAS and the

communication system operates in a so-called "network dependent clock mode". When the master clock signal CLKN has a frequency which is too low, e.g. less than 4 Megahertz, to allow the operation of the communication system in either the network clock dependent or independent mode, another master clock signal may be produced by an internal oscillator connected to the external crystal XTAL mentioned above via the two clock reference terminals CRI and CRO. The frequency, e.g. of 8,192 kilohertz, of the crystal XTAL need not be very accurate since the internal oscillator forms part of a Digital Phase Locked Loop DPLL (not shown) which is

controlled by an accurate frame signal of 8 kilohertz provided by the network at the frame terminal FR of MSRA.

In another application, the multi-standard rate adapter MSRA may be used to connect a Digital Data Set (DDS) or a Digital Feature Set (DFS) to an S-interface bus of an Integrated Services Digital Network ISDN. As shown in Fig. 3, such a digital set or terminal equipment TE is connected to the switching network DSN of the ISDN via the series connection of a terminal adapter TA including the MSRA in series with a S-interface line circuit SIFC the

S-interface bus S, a network termination NT, an U-interface line UI of the ISDN and a line termination LT1 of DSN. It is to be noted that a host microprocessor MPU1 controlling MSRA is also included in the terminal adapter TA.

The same Fig. 3 shows also an application wherein two multi-standard rate adapters MSRAl and MSRA2 form part of a U-interface modem UM. MSRAl and MSRA2 have their high speed links connected in parallel to a single chip

U-interface line circuit UILC which is itself connected to a line termination LT2 of the switching network DSN via a U-interface line U2 of the ISDN. The low speed links of MSRAl and MSRA2 are connected to data terminals DT1 and DT2 via low speed interface circuits INTF1 and INTF2

respectively. The latter INTF1 and INTF2 are also included in the modem UM which turther includes a host microprocessor MPU2 connected to both MSRA1 and MSRA2 and to a keyboard/ display terminal DSPL. The latter terminal DSPL allows to control the host microprocessor MPU2 and thus also MSRAl and MSRA2. Such a modem UM allows Time Division Multiplexing (TDM) of 16 data terminals onto one full duplex 2-wires 144 kilobit/ second link.

Still another application (not shown) of the adapter MSRA is to interface existing analog networks or modem equipments of analog telephone networks with the 64

kilobit/ second B-channel of an ISDN network.

A commercial embodiment of the described MSRA has been realized as a 54-pin electronic chip built on a 68-pin package, with a die size of 54 square millimeter and comprising about 38,000 transistors. It was realized in a 2 micron CMOS technology and a supply voltage of 5 Volts is applied thereto. Remote feeding of the MSRA is possible since its power consump ti on is of only 80 milliWatt.

While the principles of the invention have been described above in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the invention.

Claims

1. Communication adapter (MSRA) including a conversion device (TXP) able to convert first signals received from a first communication device (TEM/ TES) connected to said conversion device and transmitting said first signals according to first electrical and functional interface characteristics into second signals to be sent to a second communication device (DSN) also connected to said conversion device and able to receive said second signals according to second electrical and functional interface characteristics, said conversion device being able to be programmed in accordance with parameters which define said f irst electrical and functional interface characteristics amongst a plurality of different possible first electrical and functional interface characteristics, characterized in that said conversion device (TXP) includes, connected between said first (TEM/ TES) and said second (DSN)

communication devices, the cascade connection of first programmable converter means (TXUS) to which the first mentioned parameters are applied and second programmable converter means (TXFR) which are able to be programmed in accordance with second parameters which define said second electrical and functional interface characteristics amongst a plurality of different possible second electrical and functional interface characteristics.

2. Communication adapter according to claim 1, characterized in that said first converter means (TXUS) are connected to said second converter means (TXFR) through first latching means (TXFI) also included in the first mentioned conversion device (TXP) and able to latch said first signals during their transmission from said first to said second converter means.

3. Communication adapter according to claim 2, characterized in that said signals transmitted between said first (TEM/ TES) and said second (DSN) communication devices are successively loaded into and unloaded from a memory associated to processor means via said first (TXFI) latching means so as to unload these latching means.

4. Communication adapter according to claim 3, characterized in that said signals are only transmitted from said first (TXFI) latching means into said memory when a predetermined maximum amount of signals is latched into said first latching means, and in that said signals are only transmitted from said memory back to said first latching means when a predetermined minimum amount of signals is latched into said first latching means so as to reduce the operation load of said processor means.

5. Communication adapter according to claim 1, characterized in that said second electrical and functional interface characteristics at least consist in transmitting said second signals as standard information channels of a Time Division Multiplex (TDM) link.

6. Communication adapter according to claim 5, characterized in that said standard information channels have a bitrate of 64 kilobit/ second.

7. Communication adapter according to claim 5, characterized in that said second electrical and functional interface characteristics at least consist in transmitting said second signals as information channels which have a bitrate which is a multiple of that of said standard information channels.

8. Communication adapter according to claim 7, characterized in that said first signals are received from said first communication device (TEM/ TES) according to a first clock signal having a first clock frequency, whilst said information channels of said second signals are transmitted on said Time Division Multiplex link which operates at a second clock frequency equal to or higher than said first clock frequency, and in that said

communication adapter (MSRA) includes control means (CRTP) wherein a bus adapter (BUSA) controlled by said second clock frequency indicates to said second (TXFR) converter means the moment at which said information channels may be sent to said second communication device (DSN).

9. Communication adapter according to claim 8, characterized in that said bus adapter (BUSA) is

programmable and operates under control of third parameters which define said moment.

10. Communication adapter according to claim 9, characterized in that said third parameters are stored into said programmable bus adapter (BUSA) under the control of processor means.

11. Communication adapter according to claim 1, 9 or 10, characterized in that all said parameters are stored (UPIF) into parameter storage means (INMR) included in said communication adapter (MSRA) and controlled by processor means.

12. A plurality of communication adapters (MSRA) according to claim 9, characterized in that they are connected in parallel to a same Time Division Multiplex link, each of said communication adapters being programmed to handle a distinct one of said information channels transmitted on said link.

13. Communication adapter according to claim 8, characterized in that said communication adapter (MSRA;

MSRAM, MSRAS) includes clock synchronization means (BAUDA; BAUDAM, BAUDAS) able to generate said first clock signal by means of a digital phase locked loop (DPLL) controlled by said second clock frequency.

14. Communication adapter according to claim 13, characterized in that said clock synchronization means (BAUDA; BAUDAM, BAUDAS) are able to detect any deviation of said first clock frequency with respect to a reference first clock frequency derived from said second clock frequency by said clock synchronization means, and to transmit said detected deviation to a remote communication adapter (MSRAS) via said second converter means (TXFR).

15. Communication adapter according to claim 1, characterized in that said first (TXUS) converter means are constituted by an Universal Synchronous and Asynchronous Receive and Transmit (USART) device.

16. Communication adapter according to claim 1, characterized in that said first and second parameters are stored into said first (TXUS) and second (TXFR)

programmable converter means respectively under the control of processor means.

17. Communication adapter according to claim 1, characterized in that said communication adapter (MSRA; MSRAM, MSRAS) further includes a second conversion device (RXP) of the same type as the first mentioned conversion device (TXP), operating independently thereof and connected in the opposite direction between said second (DSN) and first (TEM/ TES) communication devices.

18. Communication adapter according to claim 17, characterized in that said second conversion device (RXP) includes third (RXFR) and fourth (RXUS) programmable converter means of the same type as said second (TXFR) and first (TXUS) programmable converter means respectively.

19. Communication adapter according to the claims 14 and 18, characterized in that said clock synchronization means (BAUDA; BAUDAM, BAUDAS) are also able to receive said detected deviation from another communication adapter (MSRAM) via said third converter means (RXFR) and to generate a third clock signal at a third clock frequency corresponding to the frequency according to which said first signals are transmitted to said first communication device (TEM/ TES) and which is based on a reference third clock frequency derived from said second clock frequency by said clock synchronization means and which includes said received deviation.

20. Communication adapter according to claim 19, characterized in that said reference first and reference third clock frequencies are identical, and in that said first and third clock frequencies are also identical.

21. Communication adapter according to claim 18, characterized in that an output of said second converter means (TXFR) is interconnectable with an input of said third converter means (RXFR) and that said communication adapter (MSRA) includes internal test means able to

generate a random test signal having one of said first electrical and functional interface characteristics, said test means being also able to transmit said test signal to an input of said first converter means (TXUS) and to compare said test sigvύ vith a return signal received in response at the output of said fourth converter means

(RXUS), said test signal being successively transmitted through said first (TXUS), second (TXFR), third (RXFR) and fourth (RXUS) converter means via said interconnection.

22. Communication adapter according to claim 21, characterized in that when said output of said second converter means (TXFR) is not interconnected with said input of said third converter means (RXFR), said test signal is also transmitted through at least said second communication device (DSN).

23. Communication adapter according to the claims 8 and 17, characterized in that said control means (CRTP) are common to said first (TXP) and second (RXP) conversion devices.

24. Communication adapter according to the claims 13 and 17, characterized in that said clock synchronization means (BAUDA; BAUDAM, BAUDAS) are common to said first (TXP) and second (RXP) conversion devices.

25. Communication adapter according to any of the claims 1 to 24, characterized in that said communication adapter (MSRA) is integrated in an electronic chip.

26. Communication adapter according to claim 25, characterized in that said processor means of claim 3, 4, 10, 11 or 16 are external to said electronic chip and connected to said communication adapter (MSRA) integrated therein via a microprocessor port (PP).

27. Communication adapter according to claim 26, characterized in that, after being programmed, said communication adapter (MSRA; MSRAM, MSRAS) is able to transmit all said signals between said first (TEM, TES) and said second (DSN) communication devices without control of said processor means.

28. Communication adapter according to claim 26, characterized in that said clock synchronization means (BAUDA; BAUDAM, BAUDAS) of claim. 13 operates independently of said processor means.