WO1990003611A2

WO1990003611A2 - Computer memory backup system

Info

Publication number: WO1990003611A2
Application number: PCT/GB1989/001117
Authority: WO
Inventors: Henry Jamieson Riddoch; Neal George Stewart; Gordon Dall
Original assignee: Henry Jamieson Riddoch; Neal George Stewart; Gordon Dall
Priority date: 1988-09-23
Filing date: 1989-09-22
Publication date: 1990-04-05
Also published as: EP0426764A1; JPH03502144A; WO1990003611A3

Abstract

A computer memory backup device (25) for a computer (10), wherein the computer (10) includes a volatile random access memory (RAM) (13), a nonvolatile memory device (15), a central processing unit (11), and a main power source (20) for converting external power into one or more DC voltage levels needed by the computer. The device (25) comprises a backup DC power source (50), including batteries in one embodiment, and control logic (30) for detecting a drop in external power level below a predetermined minimum and for outputting a first signal in response to said detected drop. A switching means (40) acts responsive to the first signal to couple the backup DC power source (50) to the volatile RAM (13), nonvolatile memory device (15), and central processing unit (11). Control logic (30) acts responsive to the first signal to direct the central processing unit (11) to store the contents of the computer's open data files and volatile RAM (13) in the nonvolatile memory device (15), and to output a second signal indicating that this storage function is complete. Switching means (40) acts responsive to the second signal to decouple said backup DC power source (50) from the central processing unit (11), the volatile RAM (13), and the nonvolatile storage device (15). The device (25) re-establishes the state of the computer's volatile RAM (15) and open data files once the power level is restored after the detected drop. A discriminator circuit (55) may also be included for recognizing write-only code data to one of a plurality of peripheral devices (24). The discriminator (55) stores the addresses of the write only data of the peripheral devices (24) and the data stored at each address for later recall when the power level is restored.

Description

COMPUTER MEMORY BACKUP SYSTEM

BACKGROUND OF THE INVENTION The valuable role which computers play in our society and the ever increasing value of the data stored in single user computers makes loss of such data costly. Data loss problems are related to the use of volatile random access memory (RAM) in the majority of modern personal computers which is sensitive to a drop or loss in the power level input to the computer.

The invention relates to a system for saving the data stored in a computer's volatile memory when the power input to the computer system is interrupted, including means for storing the contents of the computer's volatile memory in a nonvolatile memory.

Computers usually have their own power supply for providing the necessary DC voltages to run various circuits, operating elements, and peripheral devices incorporated into the computer system. This power supply is usually driven from an external AC power source. The AC power source is converted by the power supply into one or more DC voltage outputs which supply power to the computer. Generally, these computer power supplies provide only immediate power and thus have no reserve power if the external AC power source supply is interrupted or fails altogether.

The occurrence of a failure or drop on the external AC supply or a failure of the computer's own internal power supply thus results in the loss of the data stored in the volatile memory of the computer. - That is, the volatile memory in the computer typically contains application programs and open data files. To the extent such programs or data files are not also stored on a non-volatile memory device when the power is interrupted, this data will be lost. Further, many personal computers such as the IBM Personal Computer and the Apple Macintosh II are equipped with interface "slots" for plugging in peripheral devices mounted on printed circuit cards of a predetermined size. These peripheral devices include modems, monitor adapters, additional memory chips, or additional non-volatile storage media. Many of these peripheral devices contain programmable integrated circuits which are programmed by various application software in use in the computer. Many of these peripheral devices contain programmable IC's which are "write only", meaning that while the software can input data to them they may not read data from them. If an AC power failure or interruption occurs, the data contained in these programmable IC's may also be lost, or may result in incorrect operation of the peripheral device when the computer is restarted.

In larger computer installations, a stand-by power source may be available to take over immediately if there is any form of external AC supply interruption to the computer. This arrangement is not practical for smaller installations or personal computers.

Other prior art memory backup systems have been devised wherein a backup power source is provided when an interruption of the AC input to the computer's power supply occurs. Generally these systems provide an AC backup power supply for input to the computer's power supply for conversion by the computer's supply into various low voltage DC outputs for the computer's use. The backup supply-for these systems generally comprises a DC backup battery which is converted by a DC-AC converter in an external unit. This backup AC power output power is then input to the computer for reconversion by the computer's internal supply into one or more low voltage DC outputs. Thus, a "double conversion" of the original backup DC power source occurs .

An example of such a system is U.S. Patent No. 4,757,505 for COMPUTER POWER SYSTEM, issued to Marrington, et al. Marrington, et al. shows a backup power supply for a computer that is positioned between an AC power source and a computer. The backup power supply supplies DC power from a backup battery to an inverter which connects this power into AC for coupling to the computer. The computer's internal supply then reconverts this backup AC into multiple DC outputs for use by the computer's internal components. Marrington, et al. also provides software instructions in the computer which cause the computer to automatically save any open data files and current operations in the computer and the later retrieval and re-establishment by the computer of such open files and operational state once external AC power has been restored.

An example of a similar system is shown in U.S. Patent No. 4,611,289 for COMPUTER POWER MANAGEMENT SYSTEM, issued to Coppola. Coppola teaches the use of another external backup power supply wherein an inverter is used to convert DC power supplied by a battery into AC power for use by the computer. The battery power also powers an external microprocessor which provides status and command instructions to one or a number of computers connected to the power backup system to enable the computer or computers to transfer data to nonvolatile media to prevent data loss. The microprocessor also monitors the AC main power source and the remaining battery energy during a backup operation.

A further example of a computer backup system is U.S. Patent No. 4,763,333 for WORK-SAVING SYSTEM FOR PREVENTING LOSS IN A COMPUTER DUE TO POWER INTERRUPTION, issued to Byrd. Byrd teaches an external uninterruptable power supply for a computer system including a control unit mounted internally in the computer having nonvolatile storage mounted thereon. Again, the external backup power supply includes a DC battery coupled to an inverter for providing AC power to the computer's power supply.

Marrington, Coppola and Byrd all provide inef icient means for providing backup power to a computer on failure of the external AC input in that the backup power is converted twice: once from the battery backup DC power source into AC in an external unit and then back from AC to DC in the computer's internal power supply.

Further, none of these systems would function to provide backup of the computer functions should a failure of the components of the computer's internal power supply occur. Both prior art systems are arranged to sense only the failure of the external AC power source rather than a failure in the output power of the computer's internal power supply. In addition, none of the above described systems provide means for selecting write only addresses of peripheral devices and for monitoring the ongoing computer operations to enable backup storage of data stored at such storage locations. This is important, where, for example, a video card installed in the computer contains storage locations wherein video format commands are stored in a volatile memory. The contents of such storage locations would therefore also be lost in a power failure and the known prior art devices do not have the ability to restore these storage locations to their prepower failure state since there is no means available for reading the storage locations at the time of a power failure.

It is an object of the present invention to provide a memory backup device and method which can give security against loss of data from a computer, whether the computer is in the form of an individual personal computer or a terminal in a larger installation.

It is a further object of the invention to provide means for selecting those addresses and associated addresses of peripheral devices which contain programmable, write only storage and for recording the data written into those addresses by the computer during its operation for use in reloading this data at those addresses during the restarting of the computer after a power failure.

It is a further object of the invention to provide means for providing backup DC power to a number of peripheral devices during the backup period.

It is a further object of the invention to achieve the objects of the invention in a device capable of fitting entirely in existing computers.

It is a further object of the invention to have the device be capable of being built into the power supply of the computer. It is a further object of the invention have the device be capable of being implemented on a standard add in printed circuit card for a personal computer.

It is a further object of the invention to have the RAM backup, power failure, and backup control detection'portion of the apparatus located within the physical confines of the computer itself while having the backup power supply positioned externally from the computer.

It is a further object of the invention to provide a computer memory backup system wherein the backup DC power source is supplied directly to the computer's internal components without requiring that this backup DC be coupled through the computer's internal power supply. It is a further object of the invention to provide a means for sensing and responding to a failure in a DC output power line of the computer's internal power supply.

SUMMARY OF THE INVENTION The invention comprises a backup system for backing up the contents of volatile memory in a computer which also includes a plurality of other internal components including a main power source for converting external AC power into one or more DC voltage levels needed by the computer, a nonvolatile memory device, and a central processing unit. The backup system includes a backup DC power source preferably comprising one or more batteries and means for detecting a drop in the power supplied to said components below a predetermined minimum level, either through monitoring one or more of the computer power source's DC output levels or by directly monitoring an external AC power source supplying the computer's power source. The detecting means includes means for outputting a first signal in response to a drop in the power level and means responsive to said first signal for coupling said backup DC power source to the computer components. In accordance with the invention, the backup DC power source may supply DC power to the computer components directly, without coupling through the computer's main power supply or may supply a DC voltage input to the computer power supply for conversion into one or more desired different DC voltage levels.

The system further includes instruction means responsive to said first signal for directing the central processing unit to store the contents of the computer's volatile random access memory (RAM) , including the computer's open data files, in the computer's nonvolatile memory device. The instruction means also includes means for directing said central processing unit to output a second signal, indicating that this backup storage has been completed, and means for decoupling the backup DC power source from the computer in response to said second signal. The instruction means optionally includes means for variably delaying said backup storage by the central processing unit responsive to said first signal. Said variable delay option further includes maintaining the coupling of power to the computer components for a predetermined length of time and for decoupling the backup DC power source in response to a signal that the main power has been restored.

A further aspect of the invention, for a computer which includes a data bus, an address bus and a plurality of peripheral devices coupled to said computer's central processing unit via said address and data busses, includes a discriminator means coupled to said data and address busses. The discriminator means includes means for detecting one or more predetermined peripheral device port addresses on the address bus wherein write-only access is provided to the computer. The discriminator further includes recording means responsive to the detection means for storing the detected address and the associated data appearing on the data bus that is being stored at the detected address by the computer. The discriminator means further includes means for storing both the detected addresses and the associated data for each said address in nonvolatile memory upon detecting of power loss, and for retrieving said stored addresses and associated data responsive to a signal that the main power input to said computer components has been restored and for reloading at the predetermined peripheral device addresses the stored data.

BRIEF DESCRIPTION OF THE DRAWINGS FIGURE 1 illustrates an exemplary computer and associated internal components.

FIGURES 2A - 2D are block diagrams of various embodiments of the computer memory backup system according to the present invention.

FIGURE 2A is a block diagram of the basic computer memory backup system shown in an embodiment mounted on an internal add-in slot card.

FIGURE 2B is a block diagram of the computer memory backup system wherein the backup DC supply is incorporated into the computer's internal power supply. FIGURE 2C is a block diagram of the computer memory backup system wherein the external backup batteries are external of the computer with control hardware for the backup system mounted internally to the computer.

FIGURE 2D is a block diagram of the computer memory backup system mounted on an internal add in slot card and including a discriminator circuit improvement.

FIGURE 3 is a logic diagram of the hardware address circuit portion of the control logic according to the present invention used for enabling the host computer to access and control the computer memory backup functions.

FIGURE 4 is a logic diagram of the control logic used for sensing a failure of the DC outputs of the computer's power supply and for controlling the memory backup functions according* to the present invention.

FIGURE 5 is a schematic diagram of the switching means used in the preferred embodiment of the computer memory backup system for coupling the backup DC power source to the computer components.

FIGURE 6 is a logic diagram of a discriminator circuit according to the present invention.

FIGURE 7 is a flow chart describing the operation of the discriminator circuit of FIGURE 6 during normal operations of the computer.

FIGURE 8 is a flow chart describing the operation of the discriminator circuit of FIGURE 6 on detection of a loss of input power to the computer.

FIGURE 9 is a schematic diagram of a backup battery charging circuit controller according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

With reference to the figures, the invention is hereinafter described.

FIGURE 1 shows.a conventional computer 10 comprising a motherboard 12, power supply 20 and two types of non-volatile storage media 15 comprising a floppy disk drive 14 and a hard disk drive 16. The figure also shows a multiplicity of standard add-in slots 22 into which standard size add-in device cards 25 may be inserted. The slots enable easy installation of peripheral devices such as a modem, a video monitor controller card or additional non-volatile storage media which may be configured to fit on such standard size add-in cards. FIGURE 2A is a block diagram of a preferred embodiment of the invention. FIGURE 2A shows the computer 10, with a motherboard 12, power supply 20 and non-volatile storage device 15 incorporated therein. The motherboard 12 will generally include a central processing unit 11 and a volatile RAM 13. Also shown are peripheral devices 24, the computer data bus 26, and the computer address bus 28. The data bus 26 and address bus 28 connect the various elements of the computer system. FIGURE 2A also shows the apparatus of the invention embodied on a single add-in slot card such as that shown in FIGURE 1. The computer memory backup system comprises control logic 30 which monitors the +12 volt and +5 volt outputs of the computer's own internal power supply 20. Computer power supplies generally also provide -12 volt and -5 volt outputs as shown and the invention contemplates that these outputs may also be monitored by the control logic 30. Some computer power supplies also output a power good signal (PWG) 21 which may also be coupled to the control logic 30. The PWG 21 is generally used by the computer to stop operations if the DC power output is unsatisfactory. The control logic 30 is also coupled to data bus 26, address bus 28 and to switching means 40 via one or more control lines 35. The switching means 40 is coupled to a backup battery means, preferably comprising one or more backup batteries 50, via power lines 51, the switching means 40 is also coupled to the

12 and 5 volt outputs of the computer's power supply 20.

In operation, the control logic 30 monitors the power good, 12-volt, and 5-volt outputs of the computer power supply 20. In the event that one or more of the power supply 20 output voltages fails or falls below a certain predetermined level, the control logic 30 causes the switching means 40 to connect the backup battery 50 into the system to supply power to the computer 10.

Control logic 30 also outputs a signal via the data bus 26 to software resident in the computer's volatile RAM

13 which thereafter causes the total contents of the volatile RAM to be saved in nonvolatile memory 15 and closes any open files.

The control logic 30 continues to monitor the power supply 20 outputs during the saving of the volatile RAM 13 contents and before the closing of any open files. If the power supply 20 output level returns to a satisfactory level within a predetermined time period, the backup battery 50 will be deactivated and any open files will not be closed. In other words, if the normal power supplied by the computer's own power supply 20 should be restored during the time that the software backup procedure according to the present invention are in progress, the computer can continue its nor al operations, almost without interruption and without the necessity of re-booting the system. The latter course would be required if any open files had been already closed. Thus, in such a case, the user is enabled to continue progressing precisely from the point at which the power failure occurred.

The present invention minimizes the size of the backup battery 50 by having a system that does not need to power the computer for a long period of time. The capacity of the battery means 50 should merely be sufficient to power the computer for a time long enough to enable the system's software to close down operations in such a way that loss of data or damage to the software is prevented. Therefore, the backup battery 50 can comprise one or more small storage batteries.

Thus, the hardware for the device can be arranged on a full-size or half-size IBM card that fits in a standard slot in an conventional IBM personal computer or the like. The backup battery 50 may also comprise a rechargeable battery. The switching circuit 40 can provide for continuous or software controlled charging of the backup battery 50 from one of the DC outputs of the computer power supply 20. The backup battery 50 may also be designed to be the same physical size as a one half height floppy disk drive. Most personal computers provide a vacant space where an additional one half height disk drive may be installed. Thus the backup battery may be installed in this space to leave more room on the add-in slot card on which the apparatus 25, according to the present invention, is mounted, or free up this slot in the computer 10 if all of the apparatus 25 is installed in said disk drive space. Further, the software means may provide for a delay between when the output signal from the control logic 30 is generated and when the memory backup function is initiated according to the present invention. In this manner, external AC power source interruptions of short duration, commonly known as "drop-outs", will not cause the computer backup system to initiate RAM storage,thereby allowing the user to continue to use the system without interruption. During the "drop out", the backup battery 50 provides power to the computer system for a selected period, as determined by the software. At the conclusion of this delay period, if the "drop out" is still occurring, the software means begins the backup storage of the data stored in volatile memory 13 to the nonvolatile storage device 15. If the power were to return prior to the end of this delay period, the backup batteries would be decoupled and the power supply 20 re-coupled by control logic 30 and switching means 40.

FIGURE 2B shows an alternative embodiment of the invention disclosed in FIGURE 2A wherein the backup battery 50 and switching means 40 are included as part of the computer 10's internal power supply 20. Means may also be provided for generating a backup AC power signal and for coupling this generated AC power signal to an external peripheral device such as a video monitor. FIGURE 2B shows the computer 10 and its associated components as shown in FIGURE 2A except for the computer power supply 20, which is shown in greater detail. The conventional computer DC power supply 20 generally includes a noise filter and AC to DC converter 33 which connects the external AC in a conventional manner into a high voltage DC output. This is fed to a conventional DC to DC switching regulator 31 which converts the high output DC voltage to the regulated +12 volt and +5 volt DC outputs for use by the computer 10 components. The output of AC to DC converter 33 is coupled via a switch 47 to the input of the DC to DC switching regulator 31.

The backup battery 50 typically supplies a low voltage DC output. The backup battery 50 is therefore preferably coupled to regulator 31 via a DC to DC converter 39. Converter 39 converts the low voltage battery supplied DC to a high voltage DC output for use by the DC-DC switching regulator 31 in supplying regulated voltage outputs to the computer 10. The backup battery 50 via DC-DC converter 39 is coupled to DC-DC switching regulator 31 by means of switch 47 under the control of control logic 30.

Low power DC-AC converter 37 is provided to convert the high voltage DC output of converter 39 to supply an AC output power signal for powering peripheral devices. This AC output power signal is selectively output via a switch 49 under the control of control logic 30. Switch 49 thus bypasses normal coupling of external AC power to the monitor of any other device powered by the AC output power signal. Additionally, a conventional trickle charge means 36 is provided to charge the low voltage DC battery 50 during normal operation of the computer 10. Preferably, the trickle charge means draws current from the external AC power source and operates only while external AC is being coupled to computer 10.

In normal operation of the backup power circuitry of the present invention, on the occurrence of a failure in the internal circuitry of the power supply 20, or a failure of the external AC power input to the computer 10, the control logic 30 operates switch 47 to couple the low voltage DC battery 50 via converter 39 to switching regulator 31 to power the components of the computer 10. The output of DC-DC converter 39 is also coupled to DC-AC converter 37 for generation of the AC backup power signal. The control logic 30 may selectively couple the DC-AC converter 37 to the external AC output via switch 49 for use by external peripheral devices.

In another embodiment according to the present invention, as shown in FIGURE 2C, the computer memory backup system contemplates the backup battery 50 as being located outside of the computer 10, with power lines 51 connecting the external backup battery to switching means 40. This arrangement of the invention will allow for the use of a larger capacity backup battery or batteries while still allowing for the batteries to be rechargeable from the DC output of the computer's own power supply. In such an embodiment, the battery recharging could also be accomplished using a separate external charger 36 connected to the backup battery 50. Such a separate external charger would preferably include an AC to DC converter for charging the backup batteries from the external AC input.

FIGURE 2C is also similar to the embodiment shown in FIGURE 2B wherein means are provided for generating an AC output to power a peripheral device such as a monitor. In FIGURE 2C, the batteries and DC- AC converters are located external to said computer 10.

FIGURE 2C shows the control logic 30 and switching means 40 located on an internal add-on card 25. FIGURE 2C also shows an external backup battery portion of the system at 45. The external AC power source is coupled through backup battery portion 45 to computer 10 and power supply 20. The external backup battery portion 45 includes a conventional battery trickle charge 36, a second switching control 42, and a low power DC-AC converter 41.

The external AC power source is coupled to trickle charger 36. The output of the trickle charger is coupled to the external backup battery 50. The output of external backup battery 50 is coupled to the DC-AC converter 41 which operates a backup AC power source. The backup AC power source is generated under the output control switching control 42 and switch 43. An external control line 53 from the control logic 30 located on the card 25 in computer 10 operates to control switching control 42 when a power failure detect of power supply 20 occurs.

In normal operation, the external AC power source is coupled to power supply 20 and allows power supply 20 to provide the low voltage DC outputs for use by the computer. In addition, the trickle charger 36 provides charge to the external batteries 50.

On detection of a power supply failure by the control logic 30, it generates a signal on the external control line 53 which causes switching control 42 to enable the DC-AC converter 41 and direct switch 43 to couple the DC-AC converter 41 output to an externally powered monitor or the like. The output of the external battery 50 provides the DC voltage for the DC-AC converter 41. In addition, the external battery 50 is coupled by switching means 40 under the control of control logic 30 to provide direct power to the components in computer 10 to provide backup power therefor.

FIGURE 2D shows a further embodiment of the apparatus of the invention wherein pre-selected peripheral device 24 port addresses and their associated data are detected and recorded when the computer system 10 outputs data to such port addresses.

The embodiment of FIGURE 2D for purposes of illustration is described with reference to the computer 10 components and inventive elements arranged substantially as shown in FIGURE 2A wherein the control logic 30, switching means 40, and backup battery 50 are mounted on an expansion add-in slot card. Other arrangements of this embodiment including application thereof to the embodiments shown in FIGURES 2B and 2C are within the scope of the present invention.

As seen in FIGURE 2D, the expansion slot card 25 may further include a peripheral address/data discriminator circuit 55 comprising three 2K x 8 static RAM's 60, 62, and 64, a gate 66, and a counter 68. Static RAM (SRAM) 64 is coupled to the data bus of computer 10. Decoder static RAM (SRAM) 60 is coupled to the address bus of computer 10. Static RAM (SRAM) 62 is coupled to decoder static RAM 60 and gate 66 via an internal data bus 65. SRAM 60 and 62 are also coupled by control line 63 to counter 68. A second group of control lines 67, output by control logic 30, are coupled in common to SRAM's 60, 62 and 64, counter 68 and gate 66. Operation of this circuit is described herein with reference to FIGURES 6-8.

FIGURE 3 is a schematic diagram of a preferred embodiment of an addressing circuit in the control logic 30 for enabling control and information to be coupled to and from the present invention and computer 10. The circuit of FIGURE 3 allows the user to define a peripheral device address for the card 25, shown in FIGURE 2A, by manually selecting a number of switches

161 through 168 in the DIP switch 160 to a configuration representing any address in a range of default addresses specified by the computer manufacturer. For example, the IBM Personal Computer specifies a number of default addresses in_^a range from 300 to 360, any of which are usable by peripheral devices. FIGURE 3 shows the host computer address bus 28 coupled to an address decoder 170. DIP switch 160 is also coupled to the address decoder 170. Address decoder 170 is selected by means of the following circuit that also generates the RAM enable (RAMEN) signal. Three NOR gates.171 and 172 and 174 are coupled to address bus 28. The address bus line A17 is also coupled via inverter 176 to a NAND gate 178. The outputs of NOR gates 171 and 172 are further inputs to NAND gate 178. The output of NAND gate 178 comprises the RAMEN signal used to control the operating parameters of SRAM 60 as described below.

The outputs to NOR gates 171, 172 and 174 are coupled to NAND gate 179. The output of NAND gate 179 activates the gate signal on the address decoder 170. A low signal in the output NAND gate 179 indicates that one of the default addresses defined by the computer manufacturer is being accessed on the address bus. This output from NAND 179 further causes address decoder 170 to compare the inputs address on the address bus 28 to the DIP switch 160 setting. If the addresses match, a signal is output on line 180.

The address decoder 170 output signal 180 comprises inputs for OR gates 181 and 182. The second inputs for OR gates 181 and 182 comprise the outputs of OR gates 183 and 184 respectively. The system input/output signals IOW and IOR are connected to the OR gates 183 and 184. The other two inputs of OR gates 183 and 184 are connected to the system control line AEN. The outputs of 183 and 184 generate a true port input/output (10) signal, as the AEN line differentiates between the status of the IOW and IOR being used as a "real" 10 signal and when these lines are being used to update system dynamic memory. The output of OR gate 183 also comprises the "port write" (PORTWR) signal which is used to indicate to the SRAM 60 that a port address is being written to by the computer. The outputs of OR gates 181 and 182 are coupled to the enable inputs of decoders 190 and 192 respectively. The select inputs of decoders 190 and 192 are coupled to the address bus 28, specifically address lines A0 and Al.

The output of decoders 190 and 192 comprises the write control and read control signals, respectively, which are used by the system to control the rest of control logic 30 and the input and output of^{^}S-RAM's 60, 62, and 64 and gate 66.

In operation, the user defines a DIP switch address on DIP switch 160 which correlates to any of the selected default addresses which are specified by the computer manufacturer. In addition, the user specifies this address to the backup system software. Thus, when the software is interested in accessing the computer memory backup system, it will access the programmed ]address thereby outputting a signal on line 180 and activating either the read signals ARO through AR3 or the write signals AW0-AW3. Referring again to FIGURE 3, the outputs of OR gates 183 and 184 are OR'd with the output of the address decoder 170. In operation, when an output is present either at the OR gate 181 or 182 it generates a low signal output indicating that a port read (in the case of OR gate 182) or a port write (in the case of OR gate 181) has been requested at the correct port address set upon the dip switch as mentioned previously. The output of OR gate 183 generates the signal PORTWR (port write, active low) which is a signal that goes active regardless of address. The two least significant address lines A0, and Al are not included in the address decoder 170 input. Those address lines are connected to decoders 190 and 192 together with the enable signals generated by the OR gates 181 and 182. The circuit thus gives the option of 4 port write addresses and 4 port read addresses by using the two least significant address lines, A0 and Al to control decoders 190 and 191.

FIGURE 4 is a schematic diagram of the portion of control logic 30 used for sensing a failure in the DC output of the power .supply 20 and for controlling the memory backup functions according to the present invention. FIGURE 4 shows the PWG signal 21, and the I2^*-volt and 5 volt DC outputs of the computer's power supply 20. The 12 volt and 5 volt outputs of the computer power supply are input to the inverting input σf comparators 70 and 72 respectively. The non- inverting input of comparator 70 is a 12 volt reference voltage and the non-inverting input of comparator 72 is a 5 volt reference voltage. In operation, the output of comparators 70 and 72 will remain high until either the 12 volt or 5 volt output from the computer power supply 20 drops below the respective reference voltages of comparators 70 and 72. Likewise the output of the power good signal 21 will also be high unless a failure of the power input has occurred. The outputs of comparators 70 and 72 and the power good signal are coupled to a three input NAND gate 80.

The data bus 26 is connected to a latch register 75 and a tri-state buffer 77. The outputs of latch register 75 comprise the control signals used to enable proper operation of the control logic 30 and the discriminator circuit 55. These control signals include a CARD ENABLE signal* 90, a CARD RESET signal 92, and a CHARGE ENABLE signal 94. The card enable signal 90 is input to a NAND gate 82 along with the output of NAND gate 80. The output of NAND gate 82 is input to a single cell latch 85 comprised of cross-coupled NAND gates 84 and 86. The CARD RESET signal 92 comprises a second input to latch cell 85. The inverted output of latch cell 85 is coupled to the input of a NAND gate 88. The second input to NAND gate 88 is the control signal CHARGE ENABLE 94. Latch register 75 also outputs five other control signals: ADC; BATTERY SELECT; PROGRAM ENABLE; CNTCLR; and READ ENABLE, whose functions will be hereinafter described with reference to other aspects of the present invention.

Buffer 77 enables selective gating onto the computer data bus 26 of the PWG signal 21, the outputs of comparators 70 and 72, and the BATTERY and EOC signal outputs from the analog/digital converter described in FIGURE 9. Buff r 77 thus allows the software portions of the memory backup system according to the present invention to monitor the control signals from the system hardware during normal operation, to thereby detect a power failure and initiate the computer memory backup software instruction sequence for storing the volatile RAM and open data files in nonvolatile memory. That is, should the PWG signal 21 or the comparator 70 or 72 outputs go low, this will be detected by software in the computer 10 and the backup sequence will be initiated in response thereto.

In operation, the CARD ENABLE signal 90 is active high and functions through NAND gate 82 to enable comparators 70 and 72, and the PWG signal 21 to trigger a backup of the system by generating a BACK-UP signal 96 as an output from latch cell 85. The CARD RESET signal 92 is active low to ensure that, when the CARD ENABLE signal 90 is low and the system is initialized, the BACK-UP signal output will be deactivated. After a BACK-UP is triggered by a low output of comparators 70 or 72 or the power good signal 21, the CARD RESET signal goes momentarily low to reset the latch 85 and the BACK¬ UP signal 96.

The CHARGE ENABLE signal 94 is active high and allows the software to control the charge cycle of the system batteries. Means are provided in the hardware and software to determine the charge pattern of the battery. This determination of the charge pattern enables the software to control the CHARGE ENABLE signal 94 and thus the CHARGE signal 98 via NAND gate 88. The CHARGE signal 98 is used to enable and initiate the trickle charging circuit in the switching means 40 as a function of latch 85 being in a non-backup state. That is, the CHARGE signal 98 is the opposite output line of latch 85 to the BACKUP signal 96, and is never active if BACK-UP 96 is active. The BACKUP signal 96 controls the switching means 40 to couple the backup batteries 50 to the +5 volt and +12 volt DC power lines in the computer 10. FIGURE 5 illustrates the switching circuit 40 for controlling backup battery 50 charging and coupling in the preferred embodiment as shown in FIGURE 2A where the apparatus of the invention is provided on an internal expansion slot card for a computer. FIGURE 5 shows the backup battery 50 comprised of two smaller low voltage DC batteries 101 and 103. The BACK-UP signal 96 and CHARGE signal 98 output from the control logic 30 comprise control line 35 shown in FIGURE 2A. The 12 volt output from the computer's power supply 20 is coupled via resistor 120 and a switch 110 to battery 101. The negative terminal of battery 101 is connected via switch 116 to ground. The 12 volt output of the computer's power supply 20 is also connected via resistor 122 and a switch 112 to the positive terminal of battery 103. The negative terminal battery 103 is connected to ground.

In the charge mode, the CHARGE signal 98 is high and activates switches 110, 112 and 116 to cause a current path across resistors 120 and 122 to provide a charge current to batteries 101 and 103. Since the BACK-UP 96 signal is low at this point, voltage regulators 124 and 126 will be off and switch 114 will be open, thus causing batteries 101 and 103 to charge.

In the backup mode, the BACK-UP signal 96 is high, (and charge signal 98, low) causing switch 114 to be closed and voltage regulators 124 and 126 to be activated to generate output voltages, at 12 and 5 volts respectively, to the computer components for powering these components during the backup procedure.

FIGURE 6 is a block diagram of the improvements shown in FIGURE 2D above. FIGURE 6 discloses an apparatus for monitoring the data written to selected peripheral device port addresses used by the system under normal operations, storing the data written to the selected addresses during the system operation, and providing a means for recalling of the selected data written to the addresses if a shutdown or power failure of the computer occurs.

FIGURE 6 shows three 2k X 8 static RAM's (SRAM) 60, 62, and 64. SRAM 60 is connected to the address bus 28 of the computer 10. Data input/output (10) lines from SRAM 60 are coupled via internal data bus 65 to

SRAM 62. This internal data bus is also connected to a bi-directional buffer 66 which allows reading of SRAM 62 onto the data bus 26 and writing to SRAM 60 from the data bus 26. The most significant data output line from SRAM 60 is also coupled via inverter 201 to the count input an 8-bit counter 68. The output -of counter 68 is used to generate internal address bus 65 and address SRAM's 62 and 64. The internal data bus 65 connecting static RAM 60 and static RAM 62 are also coupled to a bi-directional buffer 66 which is coupled to the data bus 26. SRAM 64 is also coupled to data bus 26. Control lines of counter 68 are coupled to SRAM 62 and SRAM 64.

The control inputs of SRAM 60 are coupled to signal outputs from the control logic 30. The RAMEN signal is coupled via OR gate 202 whose second input is comprised of the PROGRAM ENABLE output from latch cell 75. The output of OR gate 202 is coupled to the output enable (OE) control input of SRAM 60. The function of OR gate 202 operates to ensure that the OE of SRAM 60 is only activated when the RAMEN signal is active and when the PROGRAM ENABLE signal is inactive. The PROGRAM ENABLE signal is also coupled via inverter 204 to AND gate 206. The second input to AND gate 206 is the port write (PORTWR) signal described with reference to FIGURE 5. The PORTWR signal is generated when an input/output write (IOW) signal is supplied by the computer indicating an output of data on data bus 26. This allows SRAM 60 to be selected via the output of AND gate 206 and the SRAM 60 control line CS (chip select) either when there is a port write or when PROGRAM ENABLE is low. The PROGRAM ENABLE also serves to input via the inverter 204 to input OR gate 208. The second input is coupled to the external control signal MEMWR and input to OR gate 208. The output of OR gate 208 is coupled to the write enable (WE) control input of static RAM 60. The output of OR gate 208 also comprises the read/write (RW) signal which is used to control bi-directional buffer 66. The output of the OR gate 208 generates the internal signal RW and generates an output only when a memory write is being performed together with the

PROGRAM ENABLE signal being active. This enables SRAM 60 to be programmed with the addresses that are of interest to the discriminator circuit.

The RW signal is input to AND gate 210 whose second input is the AR1 signal output from the hardware addressing circuit described with reference to FIGURE 3. The output of AND gate 210 is connected to the enable (E) input of the bi-directional gate 66. The control signal input/output read (IOR) is coupled to the directional control input of the bi-directional gate 66. The PORTWR and read enable signals are also coupled to OR gate 212 whose output is coupled to the write enable inputs of SRAM 62 and 64. The output enable control inputs of SRAM 62 and 64 are coupled to control signals AR1 and AR2, respectively, which are output from the addressing circuit of the backup system hardware shown in FIGURE 5. The RAMEN signal is coupled to the chip selected control input of SRAM 62 and 64.

Operation of the circuit described in FIGURE 6 is hereinafter described with reference to FIGURES 7 and 8. FIGURE 7 shows the selection and storage procedure of the circuit described in FIGURE 6. The operation begins at 220 where the computer user configures the system software by inputting data relating to the configuration of the computer 10. Such data might include the type of monitor adapter card in use, the amount of expanded or extended memory available for use by the central processing unit, and the number and type of nonvolatile storage devices in use. Once the software has been programmed with this information, the program software will load this information into SRAM 60 at 222. The software contains specific information as to which port addresses of the user defined configuration contain write only data storage locations and which are therefore of interest to the system. The software assigns each of these addresses of interest a code in the range from 1 to 127 and retains this code assignment for use during the recall procedure. Loading of the data relating to code-address assignments is accomplished by activating control signal PROGRAM ENABLE high to allow the information to be input from the data bus 26 via the bi-directional buffer gate 66. Gate 66 is enabled by the RW signal output from OR 208 and the data flow direction is set by the IOR signal. This allows the data to be written into SRAM 60. The RAMEN signal is used in conjunction with the PROGRAM ENABLE signal via OR 202 to ensure that the programming of SRAM 60 is limited to port addresses in the range from 0 to 7FF hex (i.e., the memory capacity of SRAM 60) .

Referring to FIGURE 3, the input of address lines A11-A17 controls the state of NAND gate 178 and thus the RAMEN signal. When all inputs on address line A11-A17 are low, RAMEN is low, and enables the SRAM 60 outputs. Address line A10 can be either high or low, allowing the address bus to select an address in the range from 0-7FF(hex) as the output of NAND gate 178 will be low with an address in that range.

After SRAM 60 is programmed with the relevant code-address information, any data written by the computer system to any port address at 224 will be read by the SRAM 60 and written to SRAM's 62 and 64. Decoder SRAM 60 tests whether the address is one of interest to the software. If the address is one that is not of interest to the software at 228, the code assignment to that address (and stored in SRAM 60) will be greater than or equal to 128. The output of SRAM 60 will cause the most significant data line to be high and counter 68 will not be incremented to control storage of the data in SRAM 62 and 64. If the address is one of interest to the software at 228, the code assigned to that address will be less than 128, and the most significant data line output from SRAM 60 will be low, thereby causing inverter 201 to increment counter 68. Counter 68 will then act to cause the code data written in SRAM 60 to be stored into SRAM 62 and the data bus data corresponding to the code in SRAM 60 to be written to SRAM 64 at 230, at the address of SRAM 62 and 64 corresponding to the counter output.

In operation, any time any port address is written to via the data and address busses, the data will be input to SRAM's 62 and 64. However, only when the counter is incremented by the output of SRAM 60 will SRAM's 62 and 64 store the input information.

In other words, any time any port address of interest, as determined by the software, is written to via the host address bus 28 and data bus 26, the circuit of FIGURE 6 operates to also store the data written to that address in SRAM 64 and further stores a software assigned code representing the address which the data was written to in SRAM 62. This information may then be used later by the software after a power failure to first transfer this data and stored addresses to nonvolatile memory, and later to rewrite the data to the assigned addresses once power has been restored, thereby facilitating a more accurate restart of the system. The operation of the circuit upon a power failure is described with reference to the flow chart of FIGURE 8. A power failure is detected at 240 by the software via the PWG signal (21) , or the comparators 70 and 72 coupled to latch cell 77 as hereinbefore described. The software then needs the information in

SRAM's 62 and 64. Specifically the software generates a signal on the IOR control line to change the direction of data flowing through the bi-directional gate 66. In addition, the software generates control signals AR1 and AR2 to enable the data stored in SRAM 62 and 64 to be output on the data bus 26 to the software. The COUNTER CLEAR signal (CNTRCLR) input to the counter reset control, is also generated, clearing the counter to 0 and enabling the software to read the SRAM 62 and 64 data. The software then stores the coded data in the nonvolatile memory for later use. When a power-up signal is detected or during the restart procedure at 244, the software then recalls the data stored in SRAM 62 and SRAM 64 and based on the code-address assignment and the code-data assignment, all stored by the software in the nonvolatile memory at 242, the software then writes at 246 the data stored in SRAM 60 to the selected address which it occupied prior to the power failure detect. In addition, since the improvement circuit will be reactivated on restart of the computer, the port addresses will be written into the circuit of FIGURE 6 as per the flow chart description of FIGURE 7, thus restoring the information to SRAM 62 and SRAM 64.

FIGURE 9 is a schematic/block diagram of an analog/digital converter means used in the preferred embodiment of the system to monitor the terminal voltage of the backup battery 50.

FIGURE 9 shows an analog/digital converter means 250 in the form of an integrated circuit chip coupled to data bus 26. The read (RD) and write (WR) control inputs of the analog/digital converter means 250 are coupled to the PORTRD and PORTWR control signals. The input to analog/digital (A/D) converter means 250 is coupled to the positive terminal of the backup battery 50 via a voltage potential divider comprised of a 100 kOhm resistor 262 and a 50 kOhm variable resistor 264. It is within the scope of the invention to couple a switching means (not shown) at terminal 260 to allow the software to selectively couple a multiplicity of battery means to the A/D converter means 250 in those embodiments of the invention utilizing more than one backup battery, to allow the software to monitor the terminal voltage of each of the plurality of batteries. A reference voltage (Vref) is provided by a +5 volt reference voltage coupled to a voltage divider comprised of 1 kOhm resistors 266 and 268 parallely coupled to 1 μF capacitor 270. The clock reset (CLKR) and clock in (CLKIN) inputs of A/D converter 250 are coupled via 10 kOhm resistor 272 to 150 pF capacitor 274 which is coupled to ground. The INTR output of the A/D converter 250 is coupled to the EOC signal which is read via tristate buffer 77. Address lines AR3 and AW3 are input via NOR gate 280 to the conversion select (CS) control input of the A/D converter 250.

In operation, the software initiates conversion of the analog battery 50 positive terminal voltage signal to an 8-bit digital format. This digital signal is output on data bus lines 26 by performing a "false" port write to the A/D converter 250. The software outputs a "write" signal to the A/D converter's unique address via decoder 192 as described with reference to FIGURE 3. The software is then able to read the contents of the A/D converter 250 when the EOC output goes low. The software reads the digital data output on data bus 26 from the A/D converter 250, whereby instruction means contained in the software can then use this information to regulate the charging current to the battery means 50. Charge regulation by the software is performed by selectively switching the charging of the battery means 50, as for example by controlling the switching means as described with reference to . In addition, the software means may instruct the user as to the status of the battery by outputting a signal such as "battery low - no backup cover provided" or "batteries not charging - suggest replacement".

Although various embodiments of the present invention have been disclosed herein, the present invention is not limited thereto, and modifications and variations may by resorted to without departing from the scope of the invention as understandable by those skilled in the art. Thus, the scope of the invention is to be determined by reference to the appended claims.

Claims

WHAT IS CLAIMED IS:

1. In a computer having a main power source for converting external power into one or more DC voltage levels needed by the computer, a volatile RAM, a nonvolatile memory device, and a central processing unit, a computer memory backup device comprising: a backup DC power source; means for detecting a drop in external power level below a predetermined minimum and for outputting a first signal in response thereto; means responsive to said first signal for coupling said backup DC power source to said volatile RAM, said nonvolatile memory device, and said central processing unit; instruction means responsive to said first signal for directing said central processing unit to store the contents of said computer's open data files and the contents of said volatile RAM in said nonvolatile memory device, and for directing the central processing unit to output a second signal indicating that said storage has been completed; and means for decoupling said backup DC power source from said central processing unit, said volatile RAM, and said nonvolatile storage device in response to said second signal.

2. The computer memory backup system of Claim 1 wherein said detecting means includes means, for detecting a drop in a selected one of said DC voltage levels below a predetermined level.

3. The computer memory backup system of Claim 1 further comprising means for detecting the restoration of said external power level after said drop but before completion of said storage and for outputting a third signal in response thereto and wherein said instruction means further includes means in response to said third signal for directing said central processing unit to terminate said storage and to re-establish the contents of said RAM and the contents of said open files as of the point when said first signal was received by said instruction means.

4. The computer memory backup system of Claim

1 wherein said computer includes a data bus, an address bus and a plurality of peripheral devices coupled to said computer's central processing unit via said address and data busses, said system further comprising: means for detecting one or more predetermined peripheral device addresses on said address bus; and recording means responsive to said detection means for storing said detected addresses and the data appearing on the data bus that is being stored at that address.

5. The computer memory backup system of Claim

4 wherein said instruction means further includes means responsive to said first signal for directing said central processing unit to store in said nonvolatile storage device said detected addresses and said data appearing on the data bus that was stored at that address.

6. The computer memory backup system of Claim

5 further comprising means for detecting the restoration of said external power level after said drop and after the completion of said storage and for outputting a fourth signal in response thereto and wherein said instruction means further includes means responsive to said fourth signal for directing said central processing unit to re-establish the contents of said RAM and the contents of said open files as of the point when said first signal was received by said instruction means.

7. The computer memory backup system of Claim

6 further including means responsive to said fourth signal for coupling said main power source to said volatile RAM, said nonvolatile memory device, and said central processing unit.

8. The computer memory backup system of Claim 6 further including means responsive to said fourth signal for decoupling said backup DC power source from said volatile RAM, said nonvolatile memory device, and said central processing unit.

9. The computer memory backup system of Claim 6 wherein said recording means includes means for retrieving said stored addresses and data responsive to said fourth signal and for storing at said predetermined peripheral device addresses said stored data in an order determined by the order which the addresses and data were originally written to the peripheral addresses.

10. The computer memory backup system of Claim

I further comprising means for detecting the restoration of said external power level after said drop and after the completion of said storage and for outputting a fourth signal in response thereto and wherein said instruction means further includes means responsive to said fourth signal for directing said central processing unit to re-establish the contents of said RAM and the contents of said open files as of the point when said first signal was received by said instruction means.

11. A computer memory backup system of Claim 1 wherein said backup DC power source comprises one or more batteries.

12. The computer memory backup system of Claim

II further including means for regulating the voltage output of said battery or batteries.

13. A computer memory backup system of Claim 11 wherein said battery or batteries are rechargeable.

14. A computer memory backup system of Claim 13 wherein said battery or batteries are of a capacity limited to that necessary to power said central processing unit, volatile RAM and nonvolatile storage device for a sufficient duration to complete said storage procedure.

15. The computer memory backup system of Claim

1 wherein said backup DC power source, detecting means, coupling means, and decoupling means are contained on a printed circuit card insertable in a standard internal card slot in said computer.

16. The computer memory backup system of Claim

1 wherein said main power source includes an AC-DC converter for converting said external power into a first DC voltage, and a DC-DC switching regulator for converting said first DC voltage into said one or more DC voltage levels needed by the computer.

17. The computer memory backup system of Claim 16 wherein said detecting means is contained on a printed circuit card insertable in a standard internal card slot in said computer.

18. The computer memory backup system of Claim

16 wherein said main power source further includes a DC- DC converter means for converting the output of said backup DC power source into said first DC voltage level.

19. The computer memory backup system of Claim 18 wherein said coupling means responsive to said first signal couples said DC-DC converter to said DC-DC switching regulator.

20. The computer memory backup system of Claim

19 wherein said main power supply further includes means coupled to said external power source and to said backup

DC power source for providing a charging current to said backup DC power source.

21. The computer memory backup system of Claim

20 wherein said means for providing a charging current includes means for disabling said means in response to said first signal.

22. The computer memory backup system of Claim 19 further including a DC to AC converter for output of backup AC power to one or more selected external devices and wherein said coupling means also includes means for coupling said backup DC power source to said DC-AC converter.

23. The computer memory backup system of Claim 19 wherein said backup DC power source is mounted within said main power source.

24. The computer memory backup system of Claim 19 wherein backup DC power source includes one or more batteries located external to said computer.

25. The computer memory backup system of Claim

1 wherein said coupling means and said detecting means are contained on an add-in slot card coupled to said main power source.

26. The computer memory backup system of Claim 25 wherein said backup DC power source is located external to said computer.

27. The computer memory backup system of Claim

26 including means coupled to said external power source •and to said backup DC power source for providing a charging current to said backup DC power source.

28. The computer memory backup system of Claim

27 including a DC-AC converter for converting said backup DC power source into an output AC power source for one or more selected external devices.

29. The computer memory backup system of Claim

28 including a second coupling means responsive to said first signal for selectively coupling said DC-AC converter to said backup DC power supply and selectively decoupling said means for supplying charging current.

30. The computer memory backup system of Claim 29 wherein said second coupling means includes means responsive to said instruction means for selectively coupling said DC-AC converter to said selected external device or devices.

31. The computer memory backup system of Claim 1 wherein said instruction means includes means for variably delaying the point in time after a drop in external power has been detected when said central processing unit is instructed to store said open data files and said RAM contents.

32. In a computer having a main power source for converting external power into one or more DC voltage levels needed by the computer, a volatile RAM, a nonvolatile memory device, an address bus, a data bus, one or more peripheral devices connected to said address and data busses, and a central processing unit, a computer memory backup device comprising: a backup DC power source; means for detecting a drop in said external power below a predetermined minimum and for outputting a first signal in response thereto; means responsive to said first signal for coupling said backup DC power source to said volatile RAM, said nonvolatile memory device, and said central processing unit; instruction means responsive to said first signal for directing said central processing unit to store the contents of said computer's open data files and the contents of said volatile RAM in said nonvolatile memory device, and for directing the central processing unit to output a second signal indicating that said storage has been completed; means for detecting the restoration of said output level of said main power source after said drop and after the completion of said storage and for outputting a third signal in response thereto; means for detecting one or more predetermined peripheral device addresses on said address bus; and recording means responsive to said detection means for storing said detected address and the data appearing on the data bus in conjunction with said detected address, wherein said recording means includes means for retrieving said addresses and data responsive to said third signal and for storing at said predetermined peripheral device address said stored data in an order determined by the order which the addresses and data were originally written to the peripheral port addresses.

33. The computer memory backup system of Claim 32 further including means responsive to said first signal for storing said detected addresses and data to said nonvolatile memory device.

34. The computer memory backup system of Claim 32 wherein said recording means includes said nonvolatile memory device.

35. The computer memory backup system of Claim 32 wherein said backup DC power source, detecting means, coupling means, and decoupling means are contained on a printed circuit card insertable in a standard internal card slot in said computer.

36. The computer memory backup system of Claim 32 wherein said backup DC power source, coupling means, and decoupling means are included within said main power source.

37. The computer memory backup system of Claim 32 wherein said main power source includes an AC-DC converter for converting said external power into a first DC voltage, and a DC-DC switching voltage regulator for converting said first DC voltage into said one or more DC voltage levels needed by the computer.

38. The computer memory backup system of Claim 37 wherein said detecting means is contained on a printed circuit card insertable in a standard internal card slot in said computer.

39. The computer memory backup system of Claim 37 wherein said main power source further includes a DC- DC converter means for converting the output of said backup DC power source into said first DC voltage level.

40. The computer memory backup system of Claim

39 wherein said coupling means responsive to said first signal couples said DC-DC converter to said DC-DC switching regulator.

41. The computer memory backup system of Claim

40 wherein said main power supply further includes means coupled to said external power source and to said backup DC power source for providing a charging current to said backup DC power source.

42. The computer memory backup system of Claim

41 wherein said means for providing a charging current includes means for disabling said means in response to said first signal.

43. The computer memory backup system of Claim 40 further including a DC to AC converter for output of backup AC power to one or more selected external devices and wherein said coupling means also includes means for coupling said backup DC power source to said DC-AC converter.

44. The computer memory backup system of Claim 40 wherein said backup DC pwer source is mounted within said main power source.

45. The computer memory backup system of Claim

40 wherein backup DC power source includes one or more batteries located external to said computer.

46. The computer memory backup system of Claim 32 wherein said coupling means and said detecting means are contained on an add-in slot card coupled to said main power source.

47. The computer memory backup system of Claim

46 wherein said backup DC power source is located external to said computer.

48. The computer memory backup system of Claim

47 including means coupled to said external power source and to said backup DC power source for providing a charging current to said backup DC power source.

49. The, computer memory backup system of Claim

48 including a DC-AC converter for converting said backup DC power source into an output AC power source for one or more selected external devices.

50. The computer memory backup system of Claim 49 including a second coupling means responsive to said first signal for selectively coupling said DC-AC converter to said backup DC power supply and selectively decoupling said means for supplying charging current.

51. The computer memory backup system of Claim 50 wherein said second coupling includes means responsive to said instruction means for selectively coupling said DC-AC converter to said selected external device or devices.

52. The computer memory backup system of Claim 32 wherein said backup DC power source is a battery or batteries.

53. The computer memory backup system of Claim 52 wherein said battery or batteries are rechargeable.

54. The computer memory backup system of Claim 52 further including an analog/digital converter means coupled to said data bus for digitizing the voltage generated by said battery or batteries.

55. The computer memory backup system of Claim 51 wherein said instruction means further includes means for monitoring said digitized voltage generated by said battery or batteries.

56. The computer memory backup system of Claim

55 wherein said instruction means further includes means for varying the amount of charge current to said battery or batteries responsive to said monitoring means.

57. The computer memory backup system of Claim

56 further including means for notifying the user of the status of said battery or batteries responsive to said monitoring means.

58. The computer memory backup system of Claim 32 wherein said instruction means includes means for variably delaying the point in time after a drop in external power has been detected when said central processing unit is instructed to store said open data files and said RAM contents.

59. In a computer having a main power source for converting external power into one or more DC voltage levels needed by the computer, a volatile RAM, a nonvolatile memory device, and a central processing unit, a computer memory backup device comprising: a backup DC power source; means for detecting a drop in one or more DC outputs of the main power source below respective predetermined minimum voltages and for outputting a first signal in response thereto; means responsive to said first signal for coupling said backup DC power source to said volatile RAM, said nonvolatile memory device, and said central processing unit; instruction means responsive to said first signal for directing said central processing unit to store the contents of said computer's open data files and the contents of said volatile RAM in said nonvolatile memory device, and for directing the central processing unit to output a second signal indicating that said storage has been completed; means for decoupling said backup DC power source from said central processing unit, said volatile RAM, and said nonvolatile storage device in response to said second signal.

60. The computer memory backup system of Claim

59 further comprising means for detecting the restoration of said output of said main power source ' after said drop but before completion of said storage and for outputting a third signal in response thereto and wherein said instruction means further includes means in response to said third signal for directing said central processing unit to terminate said storage and to re-establish the contents of said RAM and the contents of said open files as of the point when said first signal was received by said instruction means.

61. The computer memory backup system of Claim 59 wherein said computer includes a data bus, an address bus and a plurality of peripheral devices coupled to said computer's central processing unit via said address and data busses, said system further comprising: means for detecting one or more predetermined peripheral device addresses on said address bus; recording means responsive to said detection means for storing said detected address and the data appearing on the data bus that is being stored at that address.

62. The computer memory backup system of Claim 59 further comprising means for detecting the restoration of said external power level after said drop and after the completion of said storage and for outputting a fourth signal in response thereto and wherein said instruction means further includes means responsive to said fourth signal for directing said central processing unit to re-establish the contents of said RAM and the contents of said open files as of the point when said first signal was received by said instruction means.

63. The computer memory backup system of Claim

62 further including means responsive to said fourth signal for coupling said main power source to said volatile RAM, said nonvolatile memory device, and dais central processing unit.

64. The computer memory backup system of Claim

63 further including means responsive to said fourth signal for decoupling said backup DC power source from said volatile RAM, said nonvolatile memory device, and dais central processing unit.

65. The computer memory backup system of Claim 61 further comprising means for detecting the restoration of said external power level after said drop and after the completion of said storage and for outputting a fourth signal in response thereto and wherein said instruction means further includes means responsive to said fourth signal for directing said central processing unit to re-establish the contents of said RAM as of the point when said first signal was received by said instruction means, and wherein said recording means includes means for retrieving said stored addresses and data responsive to said fourth signal and for sto,ring in said predetermined peripheral device addresses the data stored in said recording means having corresponding addresses.