WO1990002373A1

WO1990002373A1 - Merge select decode checking

Info

Publication number: WO1990002373A1
Application number: PCT/US1989/003670
Authority: WO
Inventors: Michael Eugene Mayer; Paul Lawrence Peirson; James Herman Scheuneman
Original assignee: Unisys Corporation
Priority date: 1988-08-30
Filing date: 1989-08-25
Publication date: 1990-03-08

Abstract

A partial write portion of a memory system is disclosed in which start and end codes are utilized that define the start and end bits of an error corrected read word that is to be overwritten during a partial write operation. The start and end codes are stored in registers and are decoded in a decoder. The output of the decoder is coupled to a parity generator. The least significant bits of the start and end codes are also coupled to an Exclusive-OR gate. The outputs of the parity generator and the Exclusive-OR gate are sent to a comparator to detect errors if these outputs do not match.

Description

/ MERGE SELECT DECODE CHECKING

BACKGROUND OF THE INVENTION Field of the Invention. The present invention is related to- the field of error detection and correction for memories of data processing systems, and, in particular, it relates to checking the start and end codes employed in merge writing of data in a partial write operation.

General Description of the Prior Art. It has been a consistent goal in data processing to achieve faster and faster computing rates. Coupled with this goal of faster computing rates is a parallel goal of providing system architecture that provides for general purpose computing operations. In the past, it has been common for data processing systems to have system architectures that are designed for a fixed data word length. Often, the data word length is selected to be compatible with the data word storage register capacity of the main memory system. For example, if 36-bit memory registers are employed, it was common to have the data processing systems also function on a 36-bit basis.

At a relatively early time in the development of binary computing systems, it was recognized that a more efficient utilization of the main memory could be accomplished by providing for half-word access to the main memory system for reading and writing operations. Such systems usually were operated on a whole-word basis in arithmetic operations, even though access could be made to the memory on a half-word basis. As system architecture and memory systems were further improved and refined, systems were developed that permitted access for reading and writing in the main memory selectively on the basis of quarter-words, third- words, as well as half-words on a fixed bit-arrangement basis. These binary data processing systems were normally arranged with the memory register capacity being fixed at some multiple of two power. These fractional arrangements were relatively easy to define and implement. In U.S. Patent 4,520,439, issued May 28, 1985 in the name of Arnolds E. Liepa, which is assigned to the assignee of the present invention, provision was made for providing the capability of writing variable length bit¬ fields, where the bit-field length could vary anywhere from a single bit to the full memory word.

Many logical and data manipulate operations now require the ability to read and write various variable length bit-fields. Such operations are often accomplished by logical instructions coupled with shifting of data words to accomplish the insertion of variable bit-fields in data words to be recorded. Checking of the operation of the partial write function in such systems is vital. Although parity and check bits are generated for merged data and stored in memory in prior partial write operations, it is possible in such systems for errors to occur in the start and end code registers and logic sections. The present invention provides for the detection of merge errors due to start and end code errors.

BRIEF DESCRIPTION OF THE DRAWING Fig. 1 represents a block diagram of the merge select decode checking system of the present invention. Fig. 2 is a block diagram of the decoder of Fig. 1.

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^'DESCRIPTION OF THE PREFERRED EMBODIMENT The Figure illustrates a block diagram of a portion of a data processor which incorporates the merge select decoder checking feature of the present invention. The Memory 12 includes an array of addressable memory cells, together with the necessary associated addressing and accessing circuitry, which is not shown in detail since such circuitry may conform to well known circuit design techniques. The Memory 12 functions to store instruction words and operand words, which are collectively referred to herein as "data words." Control Section 14 operates in a conventional manner through signals on the Bus 13 to control reading operations or writing operations requested by the elements (not shown) of the data processing system, and to correlate the timing for reading and writing operations in- the Memory 12. It should be understood that there may be more than one data processor or requestor in the data processing system operating under the supervision of the Control Section 14. In the event that more than one requestor is utilized, a priority arrangement must be utilized. The Control Section 14 first issues a Read Request when a data word stored in the memory is required for a Partial Write operation. When the error-corrected data word is called from memory, it is supplied on the Bus 58 and is stored in a Read Section 11 of Merge Register 17. The Merge Register 17 is controlled by signals on the Bus 44 from the Control Section 14. Write Data is then provided on the Bus 56 for storage in the Write Data Register 57. Register 57 supplies the Write Section 13 on Bus 80. The requesting processor also specifies the Start Bit position of the variable field that is to be written by a coded signal on Bus 46, and the End Bit, or the last bit to be written in the variable field, by a coded signal on Bus 48. This information is stored in the Start Register 47 and the End Register 49, respectively, and is supplied as Start and End codes to the Decoder 78 and the Buses 51, 53, respectively. Mask signals are generated by the Decoder 78 and are transmitted on Bus 52 for storage in the Selection Section 15. These signals define the bit positions in the memory address registers that will be altered during the Partial Write operation. The Read Data stored in the Read Section 11 is merged with the Write Data in the Write Section 13 under the control of the Selection Section 15. The' Merged Data is transmitted to the Memory 12 via the Buses 77 and 72.

The Write Data in the Write Data Register 57, the Start Code in the Start Register 47 and the End Code in the End Register 49 are all preferably subjected to parity checks by the Parity Check Circuits 70, 72 and 74, respectively, which are connected to the input Bus 81 to the Control Section 14. This minimizes the transmission of errors into the Merge Register 17 and the Decoder 78. The selection lines 52 supply the Mask Merge Code to the Merge Register 17 to specify the Merge Code function bits. The merged data from the Merge Register 17 is supplied to a Parity Generator 82, where parity is checked to determine if it is even or odd parity in accordance with the type of parity that has been selected for use.

The portion of the system described thus far corresponds generally to known techniques for partial write merge field generation and verification. The remainder of this description is directed to the improvement of the present invention which adds additional verification capability, which in combination with the previously described elements enhanced reliability and verification potential while utilizing a very small amount of additional circuity.

In the implementation of the present invention, the start and end codes, which are stored in the Selector Portion 15 of the Merge Register 17, represent memory addresses that are either odd or even addresses. For example. Start and End codes may contain 5 bits and there may be 36 output lines from the Decoder 17 on the Bus 52 for each of the Start and End decode functions. A Parity Generator 94 is coupled to receive combined start and end codes on the bus 53 to provide a parity for the combined start and end codes. For example, assuming odd parity is employed, if the start code represents an even address and the end code represents an odd address, the parity generator should always generate a "1" output bit. Correspondingly, if the start code represents an odd address and the end code represents an even address, the Parity Generator 94 will again output a "1." On the other hand, if both the start and the end codes reference either even addresses or odd addresses, the Parity Generator 94 will generate a "0" bit output.

To further illustrate the operation of the system, reference is made to Fig. 2 where it will be assumed that the merged data word is 36 bits long. Bits 0-35 of the Decoded Start Code are associated with bits 0-35 of the resulting Merged Data Word, while bits 0-34 of the Decoded End Code are associated with bits 1-35 of the Merged Data Word. The Start Decode Section 78a of the Decoder 78 provides 36 bits of Decoded Start Code while the End Decode Section 78b provides 36 bits of Decoded End Code.

The Selection Section 15 of the Merge Register is constructed with AND and OR gates as shown in Fig. 2. The lowest ordered bit of the Start Code STR[0] is supplied to the OR gate 15a which provides the MERGE[0] bit that is applied to the Bus 53. The output of the OR Gate 15(a) is also supplied to an input of the OR Gate 15(b) which is also supplied an input of the STR[1] bit. OR Gate 15(c) receives the lowest ordered bit END[0] of the Decoded End Code which is inverted as indicated by the semi-circle on the input line before it is applied to the OR gate. The outputs of the OR Gates 15(b) and 15(c) are coupled to an AND Gate 15(d) which supplies the MERGE[1] bit to. the Bus 53. Thus the MERGE[1] bit will be a "1" only if END[0] is a "0" and either STR[0] or STR[1] are at a "1" leyel. The output of the AND Gate 15(d) is coupled to an input of the OR Gate 15(e) associated with the merge selector bit MERGE[2].

It is, therefore, seen that a single merge bit can be selected if both of the Start and End code bits coupled to the OR gates that are directly connected to the AND gate that supplies the merge bit (for example, OR Gates 15(b) and 15(c) connected to AND Gate 15(d) both supply "1" outputs). However, if the End Code points to one bit, such as MERGE[2] which is controlled by the END[1] bit, and the Start Code points to a preceding bit, such as MERGE[0], the Start and End decoded bits will cause the merge bits MERGE[0] and MERGE[1] to both be "l"'s. This is because STR[0] will be a "1" resulting in MERGE [0] being a one, and this signal is carried to OR Gate 15(b). Since END[1] is a "0" then END[0] is a "1", and the MERGE [1] bit will be a "1". However, although the input to OR Gate 15(e) is a "1", the END[1] bit will be a "1", which results, because of the inversion on the input to OR Gate 15(f), on a MERGE [2] "0" output from AND Gate 15(g).

It can thus be seen that all of the merge bits from the starting merge bit through the ending merge bit will be at a "1" level when applied to Bus 53. The Parity Generator 94 counts the number of merge bits that are "1" and, if these are odd (which represent the number of bits from an even start bit to an even end bit, or from an odd start bit to an odd end bit) , the Parity Generator 94 will generate "1" parity bit output. If the number of merge bits from the start bit to the ending bit is even, (which occurs when going from an odd starting bit to an even end bit, or from an even start bit to an odd end bit), the Parity Generator 94 will provide a "1" parity output bit. In addition to the Parity Generator 94, an Exclusive- OR Gate 98 (XOR) is coupled to receive the least significant bit of both the start code from the Start Register 47 and the end code from the End Register 49. The Exclusive-OR output of the XOR Gate 98 and the generated parity output from the Parity Generator 94 are coupled to the Parity Co paritor 100. The output of the XOR 98 should be equal to the output of the Parity Generator 94 since when both the start codes and end codes are either even or odd, the XOR Gate 98 should provide a "0" output. When either the start code is for an odd address and the end code is for an even address, or the start code is for an even address and the end code is for an odd address, the XOR 98 will provide a "1" output.

The output of the XOR Gate 98 should match the output from the Parity Generator 94. As long as the parities compare from the inputs to the Parity Compare Circuit 100, the output line 102 will indicate that no error has occurred. However, if these inputs fail to compare, the output line 102 will indicate a merge select decode error has occurred. It is preferred that the decoded signals from the Decoder 78 be coupled to the Parity Generator 94 to provide a check on the Decoder 78, although the start and end codes could be obtained from the output of the Start Register 46 and the End Register 47, if desired.

Although the present invention provides only approximately 50% failure detection of the actual start and end code decoders, it is a very desirable improvement since the amount of logic required is minimal, and thus the addition of this circuitry, which may be utilized in conjunction with additional checking circuitry, tends to improve the operation of the memory with a minimum amount of overhead.

Despite the fact that the present invention is described by reference to a partial write start end code checking system, the broad aspects of the invention are useful for other applications which are intended to be included within the scope of the broadest claims of the invention. These include, among other applications that will be apparent to those skilled in the art, the checking of^" even and odd address errors for memory interleaving apparatus and methods and the block transfer of memory words utilizing even and odd address accessing techniques.

Claims

CL °A[IMS

1. A method of detecting errors in a system that utilizes first and second address codes comprising generating* a combined total parity for said first and second address codes, comparing in an Exclusive-OR manner the least significant bits of said first and second address codes and comparing said total parity with the resultant bit of said least significant bit comparison.

2. A method as claimed in claim 1 wherein said first and second address codes identify even and odd addresses, respectively.

3. An address code error detection system in a system that utilizes first and second address codes comprising parity generator means coupled to receive said first and second address codes for generating a combined parity bit that is in one logical state when both said first and second address codes represent either even or odd addresses and is in its other state when one of said first and second addresses represented by said codes is odd and the other is even, Exclusive-OR means coupled to receive the least significant bits of said first and second address codes and parity comparator means coupled to said parity generator means and to said Exclusive-OR means for comparing their outputs.

4. An error detection system as claimed in claim 3 wherein said system is a memory and said address codes are memory address codes.

5. A method of detecting errors in a memory system that comprises partial write means for merging error corrected read data and write data under the control of a start code and an end code, which respectively define the start bit of said read data and the end bit of said read data which is to be overwritten with said write data, comprising generating a combined total parity bit for said start and end code, comparing in an Exclusive-OR manner the least significant bits of said start and end codes and comparing said total parity with the resultant bit of said least significant bit comparison.

6^". A memory system comprising error detection and correction means and partial write means for merging error corrected read data and write data under the control of a start code and an end code which respectively define the start bit of said read data and the end bit of said read data which is to be overwritten with said write data, decode means which receives and decodes said start code and said end code, merge storage means coupled to said decode means for storing said read data, said write data, and a selection code, parity generator means coupled to said merge storage means for generating a total parity bit that is one logical state when both said start and said end codes represent either even or odd address, and is in its other logical state when one of said start and end codes is odd and the other of said codes is even, Exclusive-OR means which compares the least significant bits of said start and end codes and provides an output representative thereof and parity comparator means coupled to said parity generator means and to said Exclusive-OR means for comparing their outputs.

7. A memory system as claimed in claim 6 wherein said parity generator means comprises merge code generating means having a number of stages equal to the number of decoded start bits which in turn is equal to the number of decoded end bits, for providing an output nth merge code bit at each stage, except the least significant bit stage, by forming the Boolean logical AND equivalent of the nth start bit and logical inverse of the (n-l)th end bit and for providing the least significant start code bit for the least significant stage merge bit and means for determining if said merge code bits provide a total even or odd parity.