WO1990001252A1 - Detection de blocage de processeurs multiples - Google Patents

Detection de blocage de processeurs multiples Download PDF

Info

Publication number
WO1990001252A1
WO1990001252A1 PCT/US1988/002651 US8802651W WO9001252A1 WO 1990001252 A1 WO1990001252 A1 WO 1990001252A1 US 8802651 W US8802651 W US 8802651W WO 9001252 A1 WO9001252 A1 WO 9001252A1
Authority
WO
WIPO (PCT)
Prior art keywords
processor
processors
waiting
instruction sequence
machine instruction
Prior art date
Application number
PCT/US1988/002651
Other languages
English (en)
Inventor
Thomas J. Teixeira
Maxim G. Smith
Original Assignee
Stellar Computer Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stellar Computer Inc. filed Critical Stellar Computer Inc.
Priority to PCT/US1988/002651 priority Critical patent/WO1990001252A1/fr
Publication of WO1990001252A1 publication Critical patent/WO1990001252A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/524—Deadlock detection or avoidance

Definitions

  • This invention relates to detecting deadlocks between multiple processors that are simultaneously executing one or more different parts of a machine instruction sequence.
  • One of the processors may reach a point in execution where it must wait until the occurrence of some condition, for example the completion of a calculation of a data value by another processor. It is known to cause the processor to wait by having the compiler insert at that point in the instruction sequence a special purpose "wait" instruction which has the effect of preventing the processor from proceeding until the needed data value is calculated.
  • One way to indicate to the waiting processor when it may proceed is to have the other processor clear a bit in memory when it has completed the needed calculation; the waiting processor tests the bit and if it finds the bit set, waits until it becomes clear; when the bit becomes clear, the waiting process proceeds to the next portion of the instruction sequence.
  • a situation in which every processor is waiting for a condition to be satisfied and there is no other work available to be done within the instruction sequence is called a hard deadlock, and reflects an error in the algorithm underlying the machine instruction sequence.
  • Such hard deadlocks cannot be resolved.
  • a so-called soft deadlock in which other available work remains to be done elsewhere in the instruction sequence, may be resolved by having one of the waiting processors proceed to that other work.
  • the computer includes special purpose logic hardware that can detect when a number of processors are simultaneously waiting and then can interrupt the operating system, which deals with the deadlock.
  • a general feature of the invention provides a method for controlling the simultaneous work of multiple processors at different places in a machine instruction sequence of the kind which includes points at each of which processing may need to wait for the occurrence of a predetermined event; a conditional branch is included at each such point in " -the instruction sequence which, when the event has not yet occurred, causes the processor executing the branch to enter and repeat a loop including the conditional branch, and causes the processing to continue outside the loop only when the event has occurred; a processor is identified as waiting at one of the points when it is executing such a conditional branch.
  • Another general feature of the invention is that a plurality of different types of events (e.g., including the setting or clearing of a bit) may be operated on by the conditional instruction.
  • the conditional branch has a single conditional branch instruction that branches to itself as long as the predetermined event has not occurred.
  • the conditional branch instruction is of the kind that is also used as part of the machine instruction sequence for purposes other than to indicate that the processor is waiting.
  • a group of processors whose processing activities are currently interrelated are all identified as waiting, at least one of the waiting processors is reassigned to another place in the machine instruction sequence.
  • the group of processors may include fewer than all of the multiple processors, for example all processors working on a single process.
  • the machine instruction sequence includes an operating system capable of interrupting the activities of each processor from time to time to reassign it to another place in the machine instruction sequence; processors that are waiting are interrupted before processors that are not waiting.
  • An other general feature of the invention is a method for determining the status of one of a plurality of processors simultaneously working on a machine instruction sequence, which includes separately detecting (i) a first condition in which a processor has been assigned to work at a location within said machine instruction sequence but is waiting to proceed until the occurrence of a predetermined event, and (ii) a second condition in which an idle processor has not been assigned to work at any location within said machine instruction sequence.
  • Preferred embodiments include the following features.
  • a value is stored corresponding to each processor indicating whether it is assigned to work at any location, and the first and second conditions are detected based on the value.
  • the operating system interrupts a processor in the second condition before interrupting any processor in the first condition.
  • the invention provides a simple, versatile, effective method for indicating that a processor is waiting, or detecting deadlocks among processors.
  • No special new instruction needs to be added to the machine instruction set executable by the processors.
  • Each processor determines immediately when the condition on which it is waiting has been satisfied. Only a single instruction, rather than several instructions, needs to be executed in order to maintain the processor in the waiting condition. The same instruction performs the functions of both causing the processor to wait, and providing the indication to the processor hardware that a waiting condition exists.
  • Deadlocks can be determined on the basis of only some group of the processors being in a waiting condition, for example processors working on a single process. Idle processors can be identified and treated differently from non-idle waiting processors. A wide variety of conditions can be used to trigger the waiting condition.
  • Fig. 1 is a block diagram of a multiple processor computer .
  • Fig. 2 is a diagram of parallel regions and blocks in a machine instruction sequence.
  • Fig. 3 is a diagram of shared register sets.
  • Fig. 4 is a diagram of a portion of a program status word.
  • Fig. 5 is a conditional branch instruction.
  • Figs. 6, 7 are block diagrams of portions of the circuitry of one of the processors.
  • Fig. 8 is a block diagram of deadlock detection logic.
  • Fig. 9 is an example of a portion of a machine instruction sequence. Structure and Operation
  • processors 12 (labeled respectively A, B, C, D) are available to execute the machine instruction sequence 14 held in a shared memory 16.
  • machine instruction sequence 14 may include one or more parallel regions 18 of machine instructions (representative parallel regions are labeled respectively W, X, Y, Z) .
  • a given parallel region X has 2 or more blocks 20 of machine instructions (representative blocks are labeled Q, R, S, T) which are independent in the sense that the same result is obtained whether one processor executes all blocks in the parallel region, or different processors execute different blocks (e.g. , processor A executes block Q, C executes R, and D executes S and T) .
  • Computer system 10 (Fig. 1) can execute from one to four processes simultaneously. (A process, as commonly defined, is a sequence of machine instructions together with information about the state of its execution) .
  • Each process may be capable of being split up for execution among more than one of the processors; the portion of a process executing on a given processor at a given time may be called a thread. Threads enter and leave parallel regions from time to time.
  • a means e.g., one of the processors for executing the instructions in a thread is called a stream.
  • a thread It may be necessary at various points within a thread to pause until another thread completes a calculation before proceeding.
  • a thread is said to be waiting when it reaches such a point and the other thread has not yet completed the calculation.
  • a stream is said to be waiting if it is currently executing instructions of a thread which is waiting.
  • a deadlock occurs when a set of streams (processors) are executing interrelated threads which are all waiting.
  • the invention provides a technique (described later) for detecting such a deadlock.
  • computer system 10 in order to regulate the work of the four processors within the machine instruction sequence 14, includes (as a shared resource) a pool 22 of high speed register sers shared in common by the four processors.
  • pool 22 includes as many register sets 24 as there are processors (in this case four, labeled respectively 0, 1, 2, 3). All of the register sets 24 have the same number (e.g, two in this example) of 32-bit registers 26.
  • the two registers in a set are called concurrency registers 0 and 1, i.e., CR0 and CR1. Any of the four register sets can be dynamically assigned to a processor as it enters a parallel region 18, as explained below.
  • a processor As a processor enters a parallel region it is assigned either a currently unused register set (if no processor is actively working in the region) or the register set already assigned to processors working in the region being entered. As a processor leaves a region the assignment of the register set to it is terminated. As long as at least one processor is actively working in a parallel region, the register set assigned to that processor is, of course, unavailable for reassignment. However, when no processor is currently active within a region, the register set previously associated with that region is free to be dynamically reassigned for use by other processors. The assignment and reassignment of register sets to processors is accomplished dynamically by the processors themselves in the course of (and without interrupting) the normal execution of the machine instruction sequence. To accomplish this, the compiler inserts assignment instructions at appropriate locations in the machine instruction sequence.
  • assignment instructions There are several types of assignment instructions.
  • One type of assignment instruction enables a processor to find an available currently unused register set and assign that set to itself, or to assign itself to the same register set currently in use by another processor so that those two processors can share the information in the register set.
  • Another allocation instruction causes a processor to terminate the assignment of a register set to that processor. When all processors to which a register set had been assigned terminate the assignment, the register set becomes freed for reassignment. Because all of the register sets have the same configuration it is irrelevant which particular register set becomes assigned to the processors working in a region at a given time.
  • the dynamic assignment and reassignment reduces overhead cost and permits a relatively small number of register sets to be used.
  • the dynamic assignment of shared register sets and the use of parallel regions is described more fully in United States Patent Applications S.N. 034,084 and S.N. 034,166, filed April 2, 1987, and assigned to the same assignee as this application.
  • each processor has an associated non-shared PSW register 40 which holds a program status word (PSW) .
  • PSW includes information pertinent to the thread currently executing on the associated processor.
  • the PSW 42 has both a protected (unaccessible to the user) portion 44 and an unprotected portion 46.
  • the protected portion 44 includes: a one-bit parallel region valid (PRV) field 48 (which is set when the CRI and PID fields, described below, are valid); a two-bit concurrency register indicator (CRI) field 50 which identifies the register set (0, 1, 2, or 3) assigned to this processor (CRI is valid only if PRV is set); a two-bit process identifier (PID) field 52 (which identifies the process on which the processor is working); and a WAIT bit 53 (indicating whether the processor is currently waiting) .
  • PRV parallel region valid
  • CRI concurrency register indicator
  • PID process identifier
  • WAIT bit 53 indicating whether the processor is currently waiting
  • Each of the four (or fewer) processes which may be executing concurrently on computer system 10 is assigned a unique PID.
  • the PSWs of all streams presently executing on behalf of a given process contain the PID of that process.
  • a wide variety of possible combinations of processes and threads executing in parallel regions may occur.
  • the invention makes use of the contents of the PSWs for detecting deadlocks.
  • the first is to determine when a given processor is waiting.
  • the second is to determine whether the waiting condition of one or more processors indicates a deadlock.
  • the compiler inserts one of the available standard conditional branch instructions that are part of the set of machine instructions which are normally used to define the computational algorithm, and are executable by each processor 12.
  • the inserted conditional branch instruction is arranged in such a way that it both causes the processor that executes it to wait and enables detection of the waiting condition.
  • a processor involves, in a conventional manner, first testing whether a certain condition Y is met.
  • conditional branch if the condition is met (89), the processor is directed back to and reexecutes the same conditional branch instruction xx. Thus the processor enters a tight (one instruction) loop where it (in effect) waits until condition Y is no longer met. When condition Y is not met, the processor falls out of the loop by proceeding (90) to the next instruction in the machine instruction sequence 14.
  • each processor 12 has circuitry for detecting the waiting condition of that processor, including a detector 92 which receives signals representative of every instruction 94 to be executed by processor 12.
  • Detector 92 identifies any conditional branch instruction that branches to itself in response to the existence of a given condition. When such a wait condition (conditional branch instruction) is identified, detector 92 signals a circuit 95 to set the WAIT bit 53 in the associated processor's PSW 40, indicating that the processor is waiting.
  • the PSW 40 WAIT bit is cleared again as soon as detector 92 detects the execution of an instruction other than a conditional branch that branches to itself. This could occur, for example, if the condition causing the waiting is satisfied, or if (after a deadlock is detected) processor 12 is reassigned to another place in the machine instruction sequence.
  • the detectors 92 for all processors 12 together assure that, at any given time, the WAIT bits 53 of the four PSWs 40 indicate the waiting status of all four processors. Deadlock determinations are based on the WAIT bits in the following way. Referring to Fig. 7, the PID values and the
  • WAIT bits of the four PSWs for processors A, B, C, and D are all delivered to logic 96 which analyses them to determine the sector * ce of a deadlock; when a deadlock is detected logic 96 issues a deadlock signal 97 that calls the operating system 98 (stored in shared memory 16, Fig. 1) and also provides operating system 98 with information about the waiting processors. Operating system 98 then responds to the deadlock signal, for example by reassigning at least one of the processors to another place in the machine instruction sequence.
  • Logic 96 declares a deadlock in accordance with the following rule. If all processors having the same PID i.e., all processors working on a given process are waiting, deadlock is declared. For example, suppose three processors (E, F, G) are working respectively on executing blocks U, V, and W, respectively, of a given process P. Suppose that processors E and F have reached points in blocks U and V where they must wait for data values to be computed in block W by processor G, and those values have not yet been computed. Then, while processors E and F wait, no deadlock condition is detected, because another processor, G, which is also assigned to process P, is not waiting.
  • the operating system removes processor G from working on process P and reassigns it to an unrelated process. Now all processors (E and F) assigned to process P are waiting; and logic 96 detects and signals a deadlock condition. In response to the deadlock condition, the operating system determines that either processor E or F would be better assigned to executing block W which is currently without a processor, than waiting in block E or F. Therefore, the operating system reassigns processor E, say, to executing block W. Then the deadlock condition no longer exists.
  • logic 96 includes four inequality comparators 110, 112, 114, 116 each of which has a J input connected to receive the PID bits (e.g., • P **--** ) A * > ° ⁇ one " ⁇ the ° ur PSWs ( °f processor A, B , C , or D) .
  • the other, K, input of each comparator receives (on a line 118) the PID bits (called PID i ) of the PSW of any processor which enters a waiting condition (i.e., is executing an instruction that branches to itself).
  • PID i the current processor
  • the outpur ⁇ of the comparators are fed respectively to OR gates 120, 122, 124, 126.
  • the other inputs of the OR gates are connected to receive respectively the WAIT bits from the PSWs of the four processors.
  • the outputs of the four OR gates are connected to an AND gate 128 whose output represents the existence or non-existence of a deadlock. Deadlock is indicated at the output of AND gate 128 if all either processors are waiting or if any processor that is not waiting has a different PID (i.e., is executing in a different process) from the current processor's PID appearing on line 118.
  • the output of AND gate 128 is delivered to the current processor whose PID is on line 118.
  • the output of AND gate 128 does not specify whether a deadlock is hard or soft. That is determined by the operating system.
  • Operating system 98 handles a deadlock by interrupting only those processors involved in the deadlock, while allowing the non-waiting processors to continue execution.
  • the operating system code determines which process P was involved in the deadlock condition by noticing which process was running at the time the deadlock occurred based on the PID bits of processor i. It then consults a scheduling table that indicates which processors are assigned to the different blocks of various processes to determine whether any blocks of process P where work remains to be done have no assigned processor.
  • the operating system reassigns one or more processors to those blocks from the waiting blocks. If the deadlock was soft, then eventually (possibly after a few more deadlocks) a block of instructions where progress may be made will have a processor assigned to it, and that block may generate values that other blocks await, thus resolving the soft deadlock.
  • the operating system .-eep ⁇ track of the number of deadlock signals generated by each process per unit time. When the number exceeds a configurable parameter, the operating system declares that process P is in a hard deadlock, and terminates execution of process P. 5 Note that a deadlock is detected and handled whenever the processors working on a given process are deadlocked even though other processors working or other processes may not be deadlocked. Furthermore, deadlocks can be detected with respect to two different processes
  • condition on which instruction 88 branches to itself may be any one of a wide variety of conditions (not limited to the set or clear condition of a particular bit) including conditions set up by other instructions inserted in the
  • concurrency registers 26 may be set by an instruction 102 placed by the compiler immediately after the instruction 104 where M is calculated.
  • a conditonal branch instruction 106 causes bit N to be tested and, if not set, branches to itself; and otherwise proceeds.
  • a readers/writers lock could be implemented by the following sets of instructions.
  • LOCK word stored in memory
  • NUMBER low order bits
  • BIT high order lock bit
  • the goal is to assure that no processor reads until there are no other processors writing at LOCATION, and that no processor is writing at LOCATION if any other processor is reading there.
  • the waiting condition of a processor waiting to write is indicated automatically by the execution of an already available conditional branch to self instruction that is part of the algorithm itself, based on a value (NUMBER) that is not simply a single bit
  • deadlock detection would not also be accomplished unless either special deadlock detection instructions were included or more complicated set up sequences were used.
  • BYTES a variable already stored in memory indicates an "empty" condition. Then a thread may determine when memory becomes available by loading BYTES into a register (REG) and testing it.
  • REG register
  • the hardware is able to detect when a processor is idle (i.e., is both waiting and nor currently assigned to any portion of the instruction sequence). In such a case, assigning the idle processor to an overhead task (e.g. , an input/output task) is better than preempting a waiting (but not idle) processor to the task, because another processor may be waiting for results from the non-idle waiting processor. Of course preempting a waiting processor (idle or not) is preferable to preempting one which is not waiting at all.
  • the operating system is able to determine whether a waiting processor is idle or not by observing, for example, the PRV bit of the processor's PSW. If the bit is set, then the processor has a work assignment, hence it is not idle.
  • the PRV bit is set by the processor executing a special instruction (one of the assignment instructions, called EPR, used to govern the execution of parallel regions) when its thread first enters a parallel region.
  • EPR assignment instructions
  • the PRV field in the PSW of the processor whose thread is entering the parallel region is set to indicate that it is executing within a parallel region.
  • Another type of assignment instruction (X?R) is executed by a processor that exits a parallel region. During execution of XPR, the PRV is cleared indicating that the thread is no longer working in a parallel region.
  • a dependency bit may have been stored to indicate, for example, whether the blocks within a parallel region are dependent such that they all should be completed before subsequent instructions following that parallel region are begun.
  • the compiler includes a TEST DEPENDENCY BIT instruction (that branches to itself until that bit is cleared) in the sequence following the XPR instruction. If an exiting processor finds the dependency bit set, it is then both waiting (its WAIT bit is set) and idle (its PRV bit is cleared) indicating to the operating system that it is available to work on a different thread. The last processor to exit the parallel region clears the dependency bit before executing the TEST instruction and then simply proceeds to the instructions that follow the parallel region. Other types of instructions may also be used to cause a processor to idle.

Abstract

Le travail simultané de processeurs multiples (12) à différents endroits dans une séquence d'instructions de machine (14) (d'un type comprenant des points au niveau de chacun desquels le traitement peut devoir attendre que se produise un événement prédéterminé) est régulé par le marquage de chaque point par un branchement conditionnel lequel, tant que l'événement prédéterminé ne s'est pas produit, fait pénétrer le processeur (12) exécutant le branchement dans une boucle comprenant le branchement conditionnel, la lui fait répéter, et fait poursuivre le traitement hors de la boucle uniquement lorsque l'événement s'est produit. On détermine qu'un processeur (12) est en attente lorsqu'il exécute un tel branchement conditionnel. Dans d'autres aspects, il existe une pluralités de différents types d'événements pouvant être déclenchés par l'instruction conditionnelle, un état inactif (non affecté) d'attente d'un processeur (12) étant détecté séparément d'un état non inactif d'attente.
PCT/US1988/002651 1988-08-03 1988-08-03 Detection de blocage de processeurs multiples WO1990001252A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US1988/002651 WO1990001252A1 (fr) 1988-08-03 1988-08-03 Detection de blocage de processeurs multiples

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1988/002651 WO1990001252A1 (fr) 1988-08-03 1988-08-03 Detection de blocage de processeurs multiples

Publications (1)

Publication Number Publication Date
WO1990001252A1 true WO1990001252A1 (fr) 1990-02-22

Family

ID=22208824

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1988/002651 WO1990001252A1 (fr) 1988-08-03 1988-08-03 Detection de blocage de processeurs multiples

Country Status (1)

Country Link
WO (1) WO1990001252A1 (fr)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3518413A (en) * 1968-03-21 1970-06-30 Honeywell Inc Apparatus for checking the sequencing of a data processing system
US3810119A (en) * 1971-05-04 1974-05-07 Us Navy Processor synchronization scheme
US4177514A (en) * 1976-11-12 1979-12-04 General Electric Company Graph architecture information processing system
US4189771A (en) * 1977-10-11 1980-02-19 International Business Machines Corporation Method and means for the detection of deadlock among waiting tasks in a multiprocessing, multiprogramming CPU environment
US4381182A (en) * 1979-07-27 1983-04-26 Lucas Industries Limited Fuel injection pump
US4445197A (en) * 1981-10-27 1984-04-24 International Business Machines Corporation Weak synchronization and scheduling among concurrent asynchronous processors
US4494193A (en) * 1982-09-30 1985-01-15 At&T Bell Laboratories Deadlock detection and resolution scheme
US4754398A (en) * 1985-06-28 1988-06-28 Cray Research, Inc. System for multiprocessor communication using local and common semaphore and information registers

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3518413A (en) * 1968-03-21 1970-06-30 Honeywell Inc Apparatus for checking the sequencing of a data processing system
US3810119A (en) * 1971-05-04 1974-05-07 Us Navy Processor synchronization scheme
US4177514A (en) * 1976-11-12 1979-12-04 General Electric Company Graph architecture information processing system
US4189771A (en) * 1977-10-11 1980-02-19 International Business Machines Corporation Method and means for the detection of deadlock among waiting tasks in a multiprocessing, multiprogramming CPU environment
US4381182A (en) * 1979-07-27 1983-04-26 Lucas Industries Limited Fuel injection pump
US4445197A (en) * 1981-10-27 1984-04-24 International Business Machines Corporation Weak synchronization and scheduling among concurrent asynchronous processors
US4494193A (en) * 1982-09-30 1985-01-15 At&T Bell Laboratories Deadlock detection and resolution scheme
US4754398A (en) * 1985-06-28 1988-06-28 Cray Research, Inc. System for multiprocessor communication using local and common semaphore and information registers

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
REINHARDT, STEVE, "A Data-Flow Approach to Multi-tasking on Cray X-MP Computers", pp. 107-114, 1985. *

Similar Documents

Publication Publication Date Title
US4809157A (en) Dynamic assignment of affinity for vector tasks
US4394727A (en) Multi-processor task dispatching apparatus
US4829422A (en) Control of multiple processors executing in parallel regions
US4074353A (en) Trap mechanism for a data processing system
RU2109333C1 (ru) Цифровой компьютер с возможностью параллельного выполнения двух и более команд
KR100616722B1 (ko) 수퍼스칼라프로세서내의파이프라인명령디스패치유닛
KR100388947B1 (ko) 실행 파이프라인 외부에 복수의 프로그램 카운터 및트레이스 버퍼를 구비한 프로세서
CA1242281A (fr) Traitement vectoriel
RU2224280C1 (ru) Механизм обнаружения исключительных ситуаций потери значимости при спекулятивном выполнении операций с плавающей точкой согласно стандарту ииэр
US4020471A (en) Interrupt scan and processing system for a data processing system
US6785887B2 (en) Technique for using shared resources on a multi-threaded processor
KR20010024750A (ko) 오예측 이후의 명령어 리플레이를 위한 파이프라인 외부의트레이스 버퍼
US6714904B1 (en) System for using rate of exception event generation during execution of translated instructions to control optimization of the translated instructions
KR20010024751A (ko) 비순서적 멀티스레드 실행을 수행하는 적재 및 저장명령어를 배열하기 위한 시스템
US4251859A (en) Data processing system with an enhanced pipeline control
KR100493126B1 (ko) 데이터정밀도모드표시기를구비한다중파이프라인형마이크로프로세서
JPH0793183A (ja) プログラム分析のためのフック命令実行方法及びデータ処理システム
US6934741B2 (en) Globally distributed load balancing
US4096564A (en) Data processing system with interrupt functions
EP0742517B1 (fr) Appareil de traduction de programmes et processeur achevant l'exécution à haute vitesse d'instructions de branchement à des sous-programmes
JP3793155B2 (ja) データ処理装置におけるソースレジスタのロッキング
EP0794488B1 (fr) Microprocesseur multi-pipeliné avec un indicateur du mode de précision de données et la méthode operatoire correspondante
WO1989000734A1 (fr) Detection de blocages entre de multiples processeurs
US8117425B2 (en) Multithread processor and method of synchronization operations among threads to be used in same
USRE38599E1 (en) Pipelined instruction dispatch unit in a superscalar processor

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AU BB BG BR DK FI HU JP KP KR LK MC MG MW NO RO SD SU

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE BJ CF CG CH CM DE FR GA GB IT LU ML MR NL SE SN TD TG