WO1989006069A1

WO1989006069A1 - Switched capacitor circuits

Info

Publication number: WO1989006069A1
Application number: PCT/AU1988/000486
Authority: WO
Inventors: Joseph Sylvester Chang; Yit Chow Tong
Original assignee: The University Of Melbourne
Priority date: 1987-12-24
Filing date: 1988-12-21
Publication date: 1989-06-29

Abstract

A Switched Capacitor circuit implemented by various hardware reduction techniques offering significant savings in chip area and power dissipation. The reduction techniques include Pole Sharing methodologies for multiplexed and unmultiplexed circuits; Full-Multiplexing which combines Time-Sharing and Time-Division-Multiplexing applied to circuits realized as a summation of poles; Capacitor Sharing techniques; a Full-Wave Rectifier having elements able to be shared in a Time-Multiplexed application and a DC offset reduction technique which minimizes additional hardware.

Description

SWITCHED CAPACITOR CIRCUITS

The present invention relates to Switched Capacitor (SC) circuits. In particular, the present invention relates to SC circuits which are implemented by various hardware reduction techniques thereby offering significant savings in chip area and power dissipation for integrated circuit and discrete component implementations.

The SC circuits of the present invention may be associated with developments disclosed in applicant's copending patent applications PI4081 (Shared Capacitor Circuit), PI6107 (Full Wave Rectifier), PI 8595 (Filter Bank) and PCT application AU88/00331 (Switched Capacitor Circuit) the specifications of which are incorporated by reference herein.

Techniques described in this specification may be advantageously applied towards design of SC Filter Bank (FB) circuits. A FB Spectrum Analyzer comprising a Bandpass (BP) FB, bank of Full-Wave Rectifiers (FWRs), and Lowpass (LP) FB is used in numerous speech applications as the front end processor. Several on-chip FB systems comprising a large number of SC filters have been reported in prior art literature. SC filters are used in these filter banks primarily for efficient chip area and power dissipation realizations, nevertheless chip area and power dissipation remain a problem due to the complexity of the hardware.

An object of the present invention is to address both the chip area and power dissipation problems in prior art SC circuits and FBs, and to offer a SC circuit design which at least alleviates these problems.

To facilitate understanding of the present invention, an introduction to circuit elements employed in realization of SC circuits is given. A SC circuit comprises a plurality of elements including operational amplifiers (op amps), capacitors, and switches controlled by switching (clock) signals. A capacitor and its associated switches is termed a Capacitor Switch Network (CSN) . A CSN array Z. comprises two or more capacitors and their associated switches. The transfer function or characteristics of a SC circuit may be specified by its switching signals, capacitor ratios and circuit topology.

A SC circuit may be unmultiplexed or it may be Time-Multiplexed (TM) . In a Time-Multiplexed SC circuit the switching signals facilitate sharing of elements in the SC circuit.

Several TM strategies are possible. Time-Sharing is 10 one TM scheme in which the switching signals comprise a multiphasic clock having two or more non-overlapping clock phases. Time-Sharing facilitates sharing of elements in an SC circuit within a multiphasic clock. In some TM SC filters (and most unmultiplexed filters) a biphasic clock comprising even (half) and odd (half) non-overlapping clock phases, may be used. One example of Time-Sharing is where an op amp services two different subcircuits during even and odd phases of a biphasic clock, permitting a saving of one op amp per pole pair in most cases. - ^„ 20 — Another TM scheme is Time-Division-Multiplexing. In -_^"_ ^{~ '} _Time-Division-Multiplexing the sampling period (inverse of the sampling frequency) of a SC circuit is divided into a number of non-overlapping local time or clock periods. In Time-Division-Multiplexing a different SC subcircuit may be serviced during each local clock period thus facilitating sharing of elements between local clock periods. Time-Division-Multiplexing may be used for implementing most SC TM filters. If a biphasic clock is used the odd phase (or even phase) of the biphasic clock 30 may coincide with the first half of the local clock period, while the even phase (or odd phase) may coincide with the latter half of the local clock period. If a triphasic (3 phase) clock is used, the first phase of the triphasic clock may coincide with the first time segment of local clock period, the second phase may coincide with the second time segment of the local clock period and the third phase may coincide with the third time segment of the local clock period. For simplicity, the embodiments described in this specification employ a. biphasic clock (instead of a multiphasic clock) .

Time-Division-Multiplexing may permit each filter channel of a m channel FB to be serviced during a local clock period. Each filter channel may comprise one or higher order filters. A second order filter, or equivalently a one pole pair filter, is termed a biquadratic filter section (biquad) . Hence, a m channel Time-Division-Multiplexed FB with n pole pairs per channel would require a biphasic clock, m local clock periods in each sampling period, 2n op amps for realizing biquads, and CSNs. A saving of 2n(m-l) op amps and some CSNs may therefore be possible.

It will be shown later that it may be possible to combine Time-Sharing and Time-Division-Multiplexing to provide a Fully-Multiplexed (FM) SC circuit.

SC circuits which employ subcircuits that do not demand high speed op amps are termed micropower compatible - These subcircuits comprise op amps that satisfy the following criterion: whe -an op amp samples an input, its output is not sampled by another op amp during the- same clock phase.

A filter bank according to the present invention may incorporate several aspects. According to a first aspect of the present invention TM may be applied to a SC filter realized as a summation of poles. Hitherto TM has been applied to cascade and ladder filter realizations only. The filter may additionally utilize an efficient filter approximation such as the non-minimum phase Lerner approximation to reduce the number of poles. The FB according to the present invention may comprise biquads and a Summer circuit.

According to a second aspect of the present invention Full-Multiplexing which combines Time-Sharing and Time-Division-Multiplexing may be adopted to a filter realized as a summation of poles; hence simultaneously exploiting the hardware advantages of Time-Sharing and h

Time-Division-Multiplexing. The clock signals used may be identical to that of a Time-Division Multiplexed case.

According to a third aspect of the present invention SC Pole-Shared methodology may be adopted for a m channel BP FB in which at least some poles of adjacent filter channels may be shared, hence achieving hardware reduction. To further enhance hardware saving, Full-Multiplexing methodology may be applied to a Pole-Shared filter bank, hence termed a "Fully-Multiplexed Pole-Shared SC FB" . Taking a 4 pole pair per channel, m channel (m _ 16 typically) FB as an example, two pole pairs which are common to two adjacent filter channels may be serviced in each local clock period (with the exception of the first filter channel) . Consequent hardware reduction may be substantial. For the FB just specified, according to the present invention, a 50% saving in the number of required op amps and CSNs, and an approximate 50% reduction in the number of required local clock periods may be achieved when compared to prior art TM FBs where 2 pole pairs-are serviced in a -local clock period. Where the - filter approximation used is the efficient (in terms of number of poles required to satisfy a given filter specification) non-minimum phase Lerner filter function, the saving may be even more substantial when compared to conventional FBs which usually employ less efficient filter approximations.

According to a fourth aspect of the present invention capacitor sharing techniques may be adopted which reduces the total number of (unit) capacitors required. This directly corresponds to chip area savings and hardware reduction.

According to a fifth aspect of the present invention the SC FB may incorporate a Full-Wave Rectifier (FWR) which features parasitic insensitivity, DC Offset compensation, jitter-free (delay-free), high sensitivity, and does not require a sample-and-hold input. In addition, when used in TM mode, all its components may be shared, hence achieving substantial chip area saving. According to a sixth aspect of the present invention, SC filters whose DC transfer functions are independent of capacitor ratios may be adopted. Employment of such SC filters may not require further hardware to reduce the effect of DC Offset.

In summary, the invention may provide in one particularly preferred embodiment a Fully-Multiplexed Pole-Shared SC BP FB with capacitor sharing and with active elements that have DC transfer functions independent of capacitor ratios and a TM SC FWR, which may be adopted for a spectrum analyzer realization.

According to one aspect of the present invention there is provided a Switched Capacitor circuit having at least one capacitor adapted to be switched by a multiphasic clock for realizing at least one transfer characteristic for said circuit, said at least one transfer characteristic being realized in said circuit as a summation of poles, said circuit being arranged such that at least one of said poles is capable of being shared by another Switched Capacitor circuit. - - - -- - -

_ According to a further aspect of the present invention there is provided a Switched Capacitor circuit having a multiplicity of capacitors, at least one of said capacitors being adapted to be switched into and out of said circuit during time periods defined by control signals, said circuit including an array comprising at least one capacitor and a common capacitor adapted to be switched into said circuit during one or more time periods such that said first common capacitor is shared by said array during said one or more time periods.

According to a still further aspect of the present invention there is provided a Switched Capacitor circuit adapted to perform input wave rectification substantially without delay and without requiring a sample-and-hold circuit, said circuit having an input and a multiplicity of elements including active and passive elements, means for generating a differential of said input, said circuit being further arranged such that, at least one of said active elements compares the input of said circuit with said differential to increase sensitivity of said circuit.

According to a still further aspect of the present invention there is provided, a Switched Capacitor circuit comprising at least one biquad, said biquad having at least one active element and at least one CSN, wherein the DC transfer^" function at an output of said active element from an input to said CSN is independent of capacitor ratios.

Preferred embodiments of the present invention will 10 now be described with reference the accompanying drawings wherein:

Figure 1(a) is a schematic diagram of a Fully- Multiplexed 4 pole pair BP Lerner filter embodying the present invention;

Figure 1(b) shows a biphasic clock and two local clock periods used in the filter realization of figure 1(a);

Figure 1(c) depicts the circuit diagram of the Fully- Multiplexed biquad employed in figure 1(a);

Figure 2(a) is a Laplace plane plot depicting the 20 pole pattern of -two Lerner filter channels where 2 pole

_ __ - pairs^"per^"channel are shared; __

-- Figure 2(b) is a circuit diagram of an unmultiplexed 2 channel 4 pole pair per channel Pole-Shared FB;

Figure 2(c) shows the unmultiplexed SC biquad employed for the FB of figure 2(b);

Figure 3(a) is a block schematic diagram showing the multiplexing sequence of a 2 channel, 4 pole pair per channel Fully-Multi lexed Pole-Shared Lerner BP FB;

Figure 3(b) shows a biphasic clock and three local 30 clock periods used in the filter realization of figure 3(a);

Figure 3(c) shows a circuit diagram of the Fully-Multiplexed Pole-Shared FB employed in the filter realization of figure 3(a);

Figure 4(a) depicts a circuit diagram of a Fully-Multiplexed biquad of a 16 channel 4 pole pair per channel Fully-Multiplexed FB;

Figure 4(bl) shows the 'F' CSN array of the Fully-Multiplexed biquad of figure 4(a) incorporating a capacitor sharing technique having a first common capacitor 'FO' ;

Figure 4(b2) depicts the 'F' CSN array of the Fully-Multiplexed biquad of figure 4(a) incorporating a capacitor sharing technique having a first common cap 'FO' and a further common capacitor 'FF'; and

Figure 5 is a circuit diagram of a Full-Wave Rectifier which may be used in a Time-Multiplexed application. The 4 pole pair Fully-Multiplexed SC BP Lerner filter depicted in figure 1(a) comprises 2 Fully-Multiplexed Biquads A and B, and a Summer circuit. Each Fully- Multiplexed Biquad A and B is as depicted in figure 1(c) and comprises op amp 1; 4 CSN arrays including 'Al, A2', 'Bl, B2', 'DI, D2' and 'Fl, F2' capacitors and associated switches; and 2 CSNs 'I' and 'U' . The CSN arrays and 'U' CSN are connected across the output and inverting input terminals of op amp 1. The 'I' CSN of the biquad has one terminal connected to the input of the Lerner filter and the other terminal connected to the inverting input node of op^" am ^"1. Biquads A and B may be modified such that each CSN array comprises more than two capacitors in a FB application (see later) .

Referring to figure 1(a) the Summer comprises op amp 2, 4 Input CSNs 'IA', 'IB', '2A' and '2B', a feedback capacitor C and a feedback CSN. Each input CSN has one terminal connected to the output of the preceding TM biquad and the other terminal connected to the inverting input terminal of Summer op amp 2. The feedback CSN and capacitor C are both connected between the output and inverting input terminals of Summer op amp 2. The outputs of biquads A and B are sampled by Summer Input CSNs 'IA, 2A' and 'IB, 2B' respectively. The output of Summer op amp 2 is the output of the Lerner filter. A biphasic clock and 2 local clock periods as depicted in figure 1(b) are used.

The multiplexing sequence commences with local clock period Pd 1 in a global clock period where Biquads A and B service the two lowest frequency pole pairs of the Lerner filter and their outputs are sampled by Summer Input CSNs ^•IA' and 'IB' respectively. CSNs 'Al', 'Bl', 'DI' and *F1' of the 4 CSN arrays in figure 1(c) are connected into the biquad circuit during this period.

In the following clock period Pd 2, CSNs 'Al', 'Bl', 'DI* and 'Fl' are disconnected and CSNs 'A2*, 'B2', 'D2' and 'F2* are connected. Biquads A and B now service the two highest frequency pole pairs, and their outputs are sampled by Summer Input CSNs '2A' and '2B* respectively. 10 Hence all pole pairs of the 4 pole pair Lerner filter are completely serviced. During this period Pd 2, Summer Input CSNs *1A" and *1B' are discharged to the inverting terminal of Summer op amp 2. The servicing sequence of the multiplexed biquads for one global clock period is now complete and is repeated with the subsequent local clock period Pd 1 in the following global clock period.

In period Pd 1 of the following global clock period. Summer Input CSNs '2A* and '2B' are discharged to the inverting node of Summer op amp 2. Summation of pole pairs 20— service -b -the multiplexed biquads of the previous global

^;_ _-_-_^r-^~clock period pertinent to, the. filter is now complete and - -the output of the Lerner filter is available at the output of Summer op amp 2 during period Pd 1. As before, the Fully-Multiplexed Biquads A and B service the two lowest frequency pole pairs of the filter during period Pd 1, and the multiplexing sequence continues.

It should be noted that as the single op amp 1 services two different subcircuits of a Fully-Multiplexed biquad during even and odd clock phases, it is Time-Shared 30 during a local clock period. In addition, as the single op amp 1 services different biquads during different local clock periods, it is also Time-Division-Multiplexed. The single op amp biquad is thus Fully-Multiplexed since it is Time-Shared in a local clock period and Time-Division- Multiplexed in a global clock period. This is a novel Time-Multiplexing strategy, in particular, when applied to a filter realized as a summation of poles. It may be apparent from figure 1(c) that capacitors

'I', 'U' , and 'Fl, F ' are discharged to either analog ground or op amp virtual ground before they sample a new voltage. Thus, these capacitors do not retain any charge pertinent to the state of the multiplexed biquads. As the capacitors of the 'I' and 'IT CSNs are of equal value for all channels (minimum sized due to capacitor scaling) , they may be conveniently shared within a multiplexed biquad as shown in figure 1(c) . The sharing of these CSNs reduces the total capacitance and simplifies the circuitry of the

Fully-Multiplexed biquads, thus permitting some area to be saved in an integrated circuit implementation. In general individual capacitors *A1, A2' , 'Bl, B2' , 'DI, D2' and 'Fl,

F2' are necessary due to the different transfer functions of the BP FB.

The hardware reduction achieved is significant for __ three reasons. First, due to the use of the Lerner filter approximation, the filtering function is more efficient. This reduces the number of poles required to meet a given filter-specification. Second, only two op amps are - - employed for realizing biquads compared to eight required -in an unmultiplexed implementation, or four required in a Time-Shared realization, or four required in a Time-Division-Multiplexed implementation using the same clock signals as in figure 1(b). This represents a substantial 50% reduction in the number of op amps required to realize the biquads compared to prior art multiplexing strategies using either Time-Sharing or Time-Division- Multiplexing. Third, the micropower compatible criterion may be satisfied. Hence the invention may provide a low power filter realization.

It has been shown in figure 1 that the Lerner filter is realized as a summation of biquads. Consequently, poles of two channels of a FB may be shared if they are on the same location in the frequency plane. This may be the case for the poles of the two extreme pole pairs (nearest and at the band edge) of two adjacent channels of a BP FB as depicted in figure 2(a) for channels .(M-l) and M in the Laplace plane. Thus, with the exception of the first filter channel, each n pole pair filter channel may be realized with only (n-2) pole pairs. A saving of 2 pole pairs per channel may therefore be achieved. In special degenerated cases, one pole pair per channel may be saved

(instead of two).

Consider an unmultiplexed 2 channel, 4 pole pair per channel Pole-Shared FB depicted in figure 2(b) which may utilize a biphasic clock. This FB comprises 6 unmultiplexed biquads and two unmultiplexed Summer circuits. Each biquad 1 to 6 in figure 2(b) comprises a biquad as shown in figure 2(c). The biquad of figure 2(c) comprises 2 capacitors, 4 CSNs and two op amps 12 and 13.

The *I* CSN of each biquad has one terminal connected to the input of the FB, and the other terminal connected to the inverting input of its respective op amp 13. The 'B' capacitor and 'F' CSN are connected across the output and inverting input terminals of op amp 13. The 'U' CSN has one terminal connected to output of op amp 13 and other - terminal connected to the inverting input-of op amp 12.

The. 'D'_ capacitor is connected between the output and inverting input terminals of op amp 12. CSN 'A' has one terminal connected to the output of op amp 12 and the other terminal connected to the inverting input of op amp 13.

Referring to figure 2(b), Summers 1,2 comprise op amps 14, 15 respectively, 2 Input CSNs, a feedback capacitor and feedback CSN. Each Input CSN of each Summer is shared by the two biquads. The left (two) terminals of the each input CSN are connected to respective outputs of two biquads and the right terminal is connected to the inverting input of the respective Summer op amp 14, 15.

The feedback capacitor and CSN are connected between the output and inverting input terminals of respective Summer op amp 14, 15. The two Summer Input CSNs of each Summer sample the outputs of four biquads and summation of 4 pole pairs pertinent to a filter channel is performed by each

Summer. In figure 2(b), Biquads 1 to 4 and Summer 1 form channel 1, and Biquads 3 to 6 and Summer 2 form channel 2 of the FB. It is evident that Biquads 3 and 4 are the two pole pairs shared by channels 1 and 2 due to Pole-Sharing.

To appreciate the significance of this Pole-Sharing methodology consider a typical 4 pole pair per channel, 16 channel BP FB for speech analysis. In a Pole-Shared design, the total number of biquads required is 34 (4 pole pairs for channel 1 plus 2 pole pairs for channels 2 to 16) compared to 64 (4 pole pairs x 16 channels) for a non Pole- Shared implementation. This represents an approximate 50% 10 saving in the number of pole pairs to be realized and hence a corresponding approximate 50% hardware reduction for realizing biquads. These savings may be achieved without the use of Time-Multiplexing.

Pole-Sharing may also be applicable to other filter types including Lowpass, Highpass and Band Reject. In some cases, single poles may also be shared.

Consider the application of Full-Multiplexing to a SC Pole-Shared FB to further increase hardware efficiency. A 2 channel 4 pole pair per channel FB is first considered. _„20 — he block schematic diagram of this FB is depicted in-. ^"~- ^". figure 3(a) which uses three local clock periods and a biphasic clock as shown in figure 3(b). The FB depicted in figure 3(c) comprises two Biquads A and B, each configured as a Fully-Multiplexed Biquad, and a Time-Multiplexed Summer. The Fully-Multiplexed biquads here are similar to that shown in figure 1(c) except that each CSN array now includes three capacitors (e.g. CSN array F comprises capacitors 'Fl, F2, F3') and associated switches pertinent to the relevant Time-Multiplexed biquads. The Summer 30 comprises op amp 3, a reset switch, a feedback capacitor C, and 8 Input CSNs 'IA, IB, 2A, 2B, 3A, 3B, 4A, 4B' which sample the output of the multiplexed biquads during the even phase of the local clock periods. One terminal of each Summer Input CSN is connected to the output of one of the two biquads and the other terminal is connected to the inverting input terminal of Summer op amp 3. The reset switch and feedback capacitor C are connected between the output and inverting input terminals of Summer op amp 3. With reference to figure 3(a) the multiplexing sequence of this FB is as follows. The sequence begins with the first local clock period Pd 1 of a global clock period where the two Fully-Multiplexed Biquads A and B service the two lowest frequency pole pairs of channel 1. The output of these biquads, or equivalently half the pole pairs of channel 1, are sampled by Summer Input CSNs 'IA' and 'IB* respectively during the even phase of Pd 1. In the following local clock period Pd 2, the multiplexed 10 Biquads A and B service the two highest frequency pole pairs of channel 1, and their outputs are sampled by Summer Input CSNs '2A' and '2B' respectively during the even phase of Pd 2. The pole pairs of channel 1 are now completely serviced. However, as a consequence of Pole-Sharing, Biquads A and B also simultaneously service the lowest frequency pole pairs of channel 2. These biquad outputs which are also relevant to channel 2 are sampled by Summer Input CSNs '3A' and *3B' during the even phase of Pd 2.

In the even phase of the final clock period Pd 3, the 20 Summer-Input CSNs-'1 ^, 'IB'-, '2A', and.'2B' which samp-led

\1 ^~ the biquad outputs pertinent to channel 1 are sampled and summed-by Summer op amp 3. The output of channel 1 is now available at the output of the Summer during the even phase of Pd 3» This multiplexed Summer is reset during the odd phase of the local clock periods. During Pd 3, the highest frequency pole pairs of channel 2 are serviced by the Fully-Multiplexed Biquads A and B, and are sampled by Input CSNs '4A' and '4B' respectively during the even phase of Pd 3. All pole pairs pertinent to channel 2 are now serviced 30 and the multiplexing sequence in the following global clock period is repeated.

During the even phase of Pd 1 of the following global clock period, the Summer Input CSNs '3A', '3B', '4A' and *4B' which sampled the output of biquads relevant to channel 2 are sampled and summed by Summer op amp 3. The output of channel 2 is now available. During this period Pd 1, the two multiplexed biquads again service the two lowest frequency pole pairs o^~£ channel 1 and the multiplexing sequence continues.

At this juncture, it may be appreciated that combined savings of an efficient filter approximation, micropower compatibility, Full-Multiplexing, and Pole-Sharing may be simultaneously achieved. To highlight the significance of the savings, consider the hardware requirements for a 16 channel, 4 pole pair per channel, BP FB tabulated in Table 1 for the present invention (Fully-Multiplexed and Pole- Shared) and prior-art unmultiplexed techniques (Direct) and TM techniques (Time-Shared and Time-Division Multiplexed) .

Table 1: Summary of Hardware Requirements for a 16 Channel Four pole pair per channel BP FB employing different techniques

Implementa- No. Biquads No. Op Amps No. Op Amps No. Local tion Realized for Biquads for Summer Clock ^: -- ---^■- Periods

16 Nil

16 Nil 1 32

32

16 Nil 1 17

It is evident that a FB embodying the invention achieves very substantial hardware reduction. In general, a m channel 4 pole pair per channel, Fully-Multiplexed Ik Pole-Shared BP FB would requite 2 op amps for the biquads, an op amp for the Summer, (m + 1) local clock periods, a biphasic clock signal, and CSNs.

The circuit diagram of a Fully-Multiplexed biquad for the FB embodying the invention tabulated in Table 1 is depicted in figure 4(a). This biquad is similar to that described previously in figure 1(c) with the exception of the increased number of capacitors in the CSN arrays. In some designs, capacitors 'F1-F24' of CSN array ^rF* may vary dramatically where their values become larger as the BP centre frequency approach the Nyquist limit. Generally, individual 'F' capacitors pertaining to different BP FB channels are required due to the different FB channel specifications.

In one example, the 'F' array may make up a substantial 34% of the total capacitance of the Fully- Multiplexed biquad. The capacitance of this array may be reduced by the following capacitor sharing techniques. First, as all 'F^r capacitors in this FB may be larger than 2 units, a first common capacitor- *FO* of 1 unit may be shared by all FB channels^^" With reference to figure 4(bl), the operation of this CSN array is as follows. During local clock period Pdl when channel 1 of the FB is serviced, capacitor 'Fl' is connected in parallel with common capacitor 'FO' so that 'FO' plus 'Fl* sums to the required value of the 'F' capacitor pertaining to the specifications of the TM biquad of channel 1. In the following clock period Pd2, 'Fl' is disconnected and 'F2' connected in parallel to 'FO'. This process is repeated for all channels concerned. To this end, it may be appreciated that all *F' capacitors of figure 4(bl) are reduced by 1 unit when compared to a prior-art case where 'FO' was absent such as that depicted in figure 4(a).

The capacitance of array 'F' may be further reduced by connecting a further common capacitor 'FF' in parallel with 'FO' and 'Fx' (x denoting the relevant multiplexed channel) for channels with large 'F' values, that is, channels 9 to 16 as depicted in figure 4(b2) . In other words, the 'F' capacitor fσr channels 9 to 16 is made up by a parallel combination of 'FO' plus 'FF' plus 'Fx'. In this manner, the residue 'Fx' capacitor for channels 9 to 16 is reduced by the combined value of 'FO' and 'FF' . In one design example, 'FF' assumes a value of 10 unit capacitors and the total reduction in the number of unit capacitors for the design embodying capacitor sharing is nearly 25%. This corresponds to a substantial 15% chip area reduction for the complete Fully-Multiplexed biquad in a modular layout.

The single penalty incurred in the employment of the capacitor sharing technique is the need for either a bank of switches or an additional clock signal to connect capacitor 'FF' into the circuit during the appropriate times. This penalty is insignificant as switches take up very little area, while the additional clock signal is easily derived from the available TM clock signals. In some applications, for example a spectrum analyzer, a FWR may be cascaded to the output of the BP FB. Figure 5 depicts a TM FWR which incorporates 3 CSNs comprising capacitors CI to C3 and their associated switches, op amp 4, comparator (op amp) 5, inverter 6, reset switches 7 and 8, comparator output switch 9, and two output switches 10 and 11. CSN 1 comprising capacitor CI has one terminal connected to the input of the FWR and the other connected to the inverting input terminal of op amp 4; reset switch 7 and CSN 2 comprising capacitor C2 are connected across the output and inverting input terminal of op amp 4; CSN 3 comprising capacitor C3 has one terminal connected to the output of op amp 4 and the other connected to the inverting input terminal of comparator 5; reset switch 8 is connected across the output and inverting input terminals of comparator 5; output comparator switch 9 has one terminals connected to the output of comparator 5 and the other to the input of inverter 6 and gate of output switch 11; output switch 11 is connected between the output of the FWR and the left plate of capacitor CI; and output Iβ switch 10 is connected between the output of the FWR and the top plate of capacitor C3.

Referring to figure 5, during the odd phase of a local clock period, capacitors CI and C2, and C3 sample the input referred DC Offset of op amp 4 and comparator 5 respectively; these active elements are therefore autozeroed (DC Offset compensated). In the following even phase, op amp 4 acts as a jitter-free (delay-free)^' unity gain (C1=C2) inverting amplifier and comparator 5 10 determines if the input of the FWR is positive or negative relative to analog ground. It does this by comparing the input with its inversion (or differential) obtained from the output of the inverting amplifier. The use of the differential signal increases the sensitivity of the FWR. If the input signal is positive, the output of the FWR is simply the input signal via path marked + in figure 5. On the other hand, if the FWR input is negative, the output of the inverting amplifier becomes the output of the FWR marked as path - in figure 5. The circuit thus - -2.0 functions as a FWR. - - --

_^~ . ^ ZT Jin some embodiments, the sensitivity of the FWR may be sacrificed for power saving. If the top plate of C3 is tied to analog ground, comparator 5 now compares the input of the FWR with analog ground (instead of its differential); reducing the sensitivity of the FWR. However, the output of comparator 5 during the even phase may be used to power down the biasing current of op amp 4 when the FWR input is above analog ground. In this manner, op amp 4 is only active when it is required to invert the 30 input signal, hence providing some power saving.

As the capacitors CI to C3 are autozeroed during the odd phase, they do not retain any charge information pertaining to the signals sampled by the FWR. Thus, when used in a TM application, all its components may be shared. For example when the FWR is cascaded to the output of the TM biquad of figure 3(c), it may be used to service TM channels 1 and 2 during clock periods Pd3 and Pdl respectively. It is evident that this FWR features parasitic insensitivity, DC Offset compensation, jitter-free, high sensitivity and does not require a sample-and-hold input. Furthermore, in a TM application, all its components are shared, achieving substantial hardware reduction. Prior-art SC FWRs lack one or more of these features.

One important consideration in the design of SC circuits, unmultiplexed or Time-Multiplexed, is the effect of DC offset due to non-idealities such as clock 0 feedthrough, input referred op amp offset, etc. In a FB application, unequal DC offsets of different BP filter channels would be inadvertently measured as energy of the bandlimited signal. The DC offsets may therefore introduce unequal errors. Prior art design methods to reduce the DC offsets include the use of a Highpass FB, resistive strings, complicated op amps, etc. These prior art techniques incur additional hardware and hence are hardware inefficient.

The DC offset at the output of an op amp may be 0 influenced by the DC (frequency) transfer function which T _may in Jturn be related to the ratio of capacitors. These capacitors may have one of its terminals tied to the inverting input of an op amp. The DC offset may be made independent of capacitor ratios by designing the DC transfer function to be independent of capacitor ratios. For example, consider the biquad shown in figure 2(c). The DC transfer function (Vout(z)/Vinl2(z)) , i.e. at z=l, from the input of CSN 'U* to the output of op amp 12 is shown to be independent of capacitor ratios. Similarly, the DC 0 transfer function (Vout(z)/Vinl3(z)) from the input of CSNs 'A', 'F' and 'I' to the output of op amp 13 is also shown to be independent of capacitor ratios. In this manner, the DC offsets of different biquads may have the same DC offset which may easily be accounted for. The DC offsets therefore may not be a problem and may not require additional hardware.

In conclusion, the present invention provides a novel Fully-Multiplexed Pole-Shared Switched Capacitor Filter , Bank. The FB may employ biquads whose DC transfer function at the output of op amps is independent of capacitor ratios and may also incorporate a Capacitor Sharing methodology and Full-Wave Rectifier as described herein. These circuits feature hardware efficiency which directly leads to reduced chip area and power dissipation requirements in their realization. Hence, the objectives of the invention to address the chip area and^' power dissipation problems of complex SC circuits, such as a spectrum analyzer, may be achieved.

While the preferred embodiments described above relates to circuits of a spectrum analyzer, it is to be appreciated that any circuit which incorporates an SC filter may usefully utilize the invention. Since modifications within the spirit and scope of the invention are readily effected by persons skilled in the art, it is to be understood that the invention is not limited to the particular embodiments described, by way of example, hereinabove.

Claims

THE CLAIMS DEFINING THE INVENTION ARE AS FOLLOWS: 1. A Switched Capacitor circuit having at least one capacitor adapted to be switched by a multiphasic clock for realizing at least one transfer characteristic for said circuit, said at least one transfer characteristic being realized in said circuit as a summation of poles, said circuit being arranged such that at least one of said poles is capable of being shared by another Switched Capacitor circuit. 10 2. A Switched Capacitor circuit according to claim 1 wherein said multiphasic clock comprises a biphasic clock having odd and even phases.

3. A Switched Capacitor circuit according to claim 1 or 2 wherein said circuit comprises at least one biquad and at least one Summer circuit.

4. A Switched Capacitor circuit according to any one of the preceding claims wherein said circuit is unmultiplexed.

5. A Switched Capacitor circuit according to claim 1, 2 or 3 wherein said circuit is Time-Multiplexed.

20 6.- A Switched Capacitor circuit according to claim-5 ^"_ wherein said circuit is Time-Shared. ._ _

7. A. Switched Capacitor circuit according to claim 6 including a plurality of components, said circuit being arranged such that at least one of said components is shared within a time period defined by said multiphasic clock.

8. A Switched Capacitor circuit according to claim 7 as appended to claim 2 wherein said at least one shared component is shared between said odd and even phases of

30 said biphasic clock.

9. A Switched Capacitor circuit according to claim 5 or 6 wherein said circuit is Time-Division-Multiplexed.

10. A Switched Capacitor circuit according to claim 9 having an associated sampling frequency, said sampling frequency defining global clock periods for said circuit, each global clock period being divided into two or more non-overlapping local time periods.

11. A Switched Capacitor circuit according to claim 10 including a plurality of components, said circuit being arranged such that at least one of said components is shared between two or more local time periods.

12. A Switched Capacitor circuit according to any one of the preceding claims including an array comprising at least one capacitor and a common capacitor adapted to be switched into said circuit during one or more time periods such that said first common capacitor is shared by said array during

10 said one or more time periods.

13. A Switched Capacitor circuit according to claim 12 including a further array comprising at least one capacitor and a further common capacitor adapted to be switched into said circuit such that said further common capacitor is shared by said further array.

14. A Switched Capacitor circuit according to any one of the preceding claims further including a Full-Wave Rectifier.

15. A Switched Capacitor circuit according to any one of 20 the preceding-claims wherein said circuit includes at-least ^~ one biquad having at least one active element and at least

—-- - one CSN, and wherein the DC transfer function at an output of said active element from an input to said CSN is independent of capacitor ratios.

16. A Switched Capacitor circuit according to any one of the preceding claims wherein said circuit comprises a filter, said at least one transfer characteristic corresponding to a frequency response of said filter.

17. A Filter Bank incorporating a plurality of Switched 30 Capacitor circuits according to claim 16, wherein each transfer characteristic corresponds to a channel of said Filter Bank.

18. A Switched Capacitor circuit having a multiplicity of capacitors, at least one of said capacitors being adapted to be switched into and out of said circuit during time periods defined by control signals, said circuit including an array comprising at least one capacitor and a common capacitor adapted to be switched into said circuit during one or more time periods such that said first common capacitor is shared by said array during said one or more time periods.

19. A Switched Capacitor circuit according to claim 18 including a further array comprising at least one capacitor and a further common capacitor adapted to be switched into said circuit such that said further common capacitor is

^' shared by said further array.

20. A Switched Capacitor circuit according to claim 18 or 19 wherein said circuit includes at least one biquad, having at least one active element and at least one CSN, and wherein the DC transfer function at an output of said active element from an input to said CSN is independent of capacitor ratios.

21. A Switched Capacitor circuit adapted to perform input wave rectification substantially without delay and without requiring a sample-and-hold circuit, said circuit having an input and a multiplicity of elements including active and passive elements, means for generating a differential of - said input, said-circuit being further arranged such that, - at least one of said active elements compares the input of said circuit with said differential to increase sensitivity of said circuit.

22. A Switched Capacitor circuit according to claim 21 wherein at least one of said active elements has a DC offset, said circuit being arranged such that said DC offset is sampled so that said at least one of said active element is DC offset compensated.

23. A Switched Capacitor circuit according to claim 21 or 22 wherein at least one of said elements does not retain charge information pertaining to the input of said circuit, said at least one of said elements that does not retain said charge information being adapted to be shared in a Time-Multiplexed application.

24. A Switched Capacitor circuit according to claim 21, 22 or 23 wherein at least one of said active elements is adapted to determine if the current to at least one other active element should be turned off to reduce power dissipation.

25. A Switched Capacitor circuit comprising at least one biquad, said biquad having at least one active element and at least one CSN, wherein the DC transfer function at an output of said active element from an input to said CSN is independent of capacitor ratios.

26. A Switched Capacitor circuit substantially as herein described with reference to figures 1(a) to 1(c), or figures 2(b) and 2(c) or figures 3(a) to 3(c) or figures

4(a) and 4(bl) or figures 4(a) and 4(b2) or figure 5 of the accompanying drawings.