WO1989003589A1 - Integrated circuit contact fabrication process - Google Patents

Integrated circuit contact fabrication process Download PDF

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Publication number
WO1989003589A1
WO1989003589A1 PCT/US1988/003271 US8803271W WO8903589A1 WO 1989003589 A1 WO1989003589 A1 WO 1989003589A1 US 8803271 W US8803271 W US 8803271W WO 8903589 A1 WO8903589 A1 WO 8903589A1
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WO
WIPO (PCT)
Prior art keywords
layer
electrode layer
refractory metal
dielectric
metal based
Prior art date
Application number
PCT/US1988/003271
Other languages
French (fr)
Inventor
Gayle Wilburn Miller
Harold Springer Crafts
George Maheras
Werner Adam Metz, Jr.
Hubert Oscar Hayworth
Original Assignee
Ncr Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ncr Corporation filed Critical Ncr Corporation
Priority to DE8888909410T priority Critical patent/DE3874522T2/en
Publication of WO1989003589A1 publication Critical patent/WO1989003589A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66946—Charge transfer devices
    • H01L29/66954—Charge transfer devices with an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals

Definitions

  • This invention relates to integrated circuit contact fabrication processes of the kind including the steps of: forming over an active region of a semiconductor substrate a first patterned electrode layer and an overlying first dielectric layer; forming in the active region and on said first dielectric layer a second electrode layer relatively overlying at least an edge of said first electrode layer, to create a nonplanar step in the region of relative overlap with said first electrode layer; and forming a refractory metal based layer on said second electrode layer, said second electrode layer being patterned to retain the nonplanar step.
  • FIG. 1 A process for integrated circuit contact fabrication is known from U.S. Patent No. 4,403,394 and is illustrated in Fig. 1 of the present drawings.
  • the prior art represents a portion of a DRAM cell formed in a lightly doped p- type monocrystalline substrate 1, having an n+ conductively doped region 2 on one side of the active region and a doped polycrystalline silicon layer 3 (poly I) situated at the other side.
  • the active region is bordered on the sides by field oxides 4.
  • Poly I layer 3 is one electrode of a capacitor, which is selectively coupled to conductive region 2 upon the enable ent of the field effect transistor formed by secondly deposited polysilicon gate electrode 6 (poly II) through a channel between region 2 and the substrate proximate electrode 3.
  • An oxide dielectric 7 covers electrode 6. Connections between the poly II electrode layer 6 and subsequent metalization layers are made by contacts using metal 8, formed in known manner by masking and then etching openings through dielectric 7, depositing of a metal layer, and patterning the metalization.
  • the known process has the disadvantage that the concluding contour is far from planar, and that the extent of overlapping between poly I capacitor electrode 3 and poly II gate electrode 6 must be significant to ensure that alignment tolerances do not result in a contact cut down to the level of the poly I layer by a misalignment of the contact cut mask over the edge of poly II layer.
  • a relatively large contact area between metal 8 and poly II electrode 6 is also required to minimize the effects of contact resistance on the conduction of charge to poly II electrode 6.
  • the known process also has the disadvantage that the ' contact masking and etching steps are costly, and furthermore the area of the underlying polysilicon layer must be relatively large to compensate for alignment errors which are introduced by the successive masking operations.
  • an integrated circuit contact fabrication process of the kind specified, characterized by the steps of: planarizing the structure with second dielectric to selectively expose the surface of the refractory metal based layer; and forming a patterned metalization layer over the second dielectric to make contact with the exposed surface of the refractory metal based layer.
  • an integrated circuit contact fabrication process has the advantage of providing a self-aligned contact structure and the further advantages of not requiring masking or etching to form contact openings in a dielectric layer, reducing the polysilicon area allocation for mask alignment tolerances, minimizing metal step coverage problems, providing low ohmic resistance contact connections, and providing a degree of planarization for subsequent metalization layers.
  • the use of a contact fabrication process according to the invention reduces the "footprint" or area of the contact from the metalization layer to the second polysilicon gate electrode, and thereby measurably reduces undesired capacitive coupling between the gate electrode of the access transistor and the storage capacitor electrode.
  • Fig. 1 is a cross-sectional schematic of a DRAM fabricated according to the prior art.
  • Figs. 2 and 3 illustrate by way of schematic cross sections two embodiments of DRAM cells fabricated according to the present invention.
  • Figs. 4-9 schematically illustrate in the cross section representative stages in the fabrication sequence which concludes as the embodiment depicted in Fig. 2. Best Mode for Carrying Out the Invention
  • Figs. 2 and 3 of the drawings Structures fabricated according to the present invention are depicted in Figs. 2 and 3 of the drawings. The substantial planarity of the structures is immediately evident. Similarly visible is the minimal overlap between the poly I capacitor electrode 23 and the poly II gate electrode structures 11/12 and 17/18, namely in region 13.
  • the compositely formed gate electrodes, comprising poly II layer 11 or 18 and a selectively deposited refractory metal layers 12 or 17, provide comparatively low resistance electrode structures. Note also that the contacts between the poly II electrode and metalization 9, through intermediate dielectrics, are self-aligned with relation to the edge of poly I electrode 23 by the nonplanar step at location 14.
  • FIG. 3 A variation to the present process results in the alternate embodiment schematically depicted in Fig. 3.
  • the concluding structure has a shunting refractory metal layer 17 over the upper surface alone of poly II layer 18. Fabrication of the structure in Fig. 3 is believed to be somewhat easier, in that selective deposition of tungsten is not required. However, this variant requires the etching of successive tungsten and polysilicon layers during the formation of the electrode 17/18 pattern.
  • Fig. 4 where lightly doped p-type monocrystalline silicon substrate 1 is processed to create field oxide regions 4, and thereby define an active region 19 situated medially.
  • the active region is thereafter covered by a thin oxide layer 21, preferably formed to a thickness of approximately 20 nanometers by thermal oxidation of the substrate 1, and a conductively doped polycrystalline silicon layer 22, poly I, deposited by known techniques to a thickness of approximately 500 nanometers.
  • Poly I layer 22 and oxide 21 are then patterned by standard photoresist masking and etching techniques to create the structure depicted in Fig. 5, a capacitor electrode 23 electrically isolated from substrate 1 by an oxide dielectric 24.
  • the patterned poly I layer 23 is then subjected to an oxidation operation suitable to form directly or in a sequence of multiple steps a dielectric suitable to isolate electrode 23 from any succeeding layers of conductive polysilicon.
  • the thickness of the oxide ' dielectric immediately over substrate 1, designated as 26 in Fig. 6, is nominally 20 nanometers, while the dielectric layer 27 surrounding capacitor electrode 23 is nominally at least 70 nanometers.
  • the difference in thickness is primarily attributable to the accentuated oxidation rate of doped polysilicon 23 over lightly doped monocrystalline silicon 1. The result is consistent with a preference for having a relatively thin gate oxide dielectric 26 while providing a relatively thicker interelectrode oxide dielectric 27.
  • oxide regions 26 and 27 are covered in the next step of fabrication by a layer of doped polycrystalline silicon 28, poly II, which is in normal manner conformally deposited to the same nominal depth of approximately 500 nanometers as the Poly I layer 22.
  • a feature of this deposition is the creation of step 29 in the contour of poly II layer 28, above the edge of poly I electrode layer 23. Step 29 is attributable to the difference in height between oxide layer 26 on one side and the combination of poly I layer 23 and somewhat thicker oxide layer 27 on the other side.
  • the preferred embodiment includes masking and etching to retain a segment, electrode 11, of the poly
  • the preferred practice of the invention next involves a selective deposition of a refractory metal layer 12, such as tungsten to a nominal thickness of 100 nanometers, onto any exposed silicon surface. Tungsten is preferred for its low resistance and high temperature capabilities. Nevertheless, other refractory metals or suicides thereof are also suitable shunting layers. The objective is to create low resistance shunting layers over the doped but relatively higher resistance polysilicon electrode 11.
  • Fig. 7 is next subjected to an ion implantation using phosphorus or the like to form n + doped region 2.
  • Polysilicon layers 11 and 23 serve as implant masks to create the alignment between the edge of the poly II and tungsten gate electrode 11/12 and the doped region 2.
  • Relatively thin gate oxide 26 does not materially impede the implant.
  • a slight variation of the preferred embodiment involves the performance of the implant which produces doped region 2 prior to the selective deposition of refractory metal layer 12.
  • the poly I and poly II layers 11 and 23 would serve as self-align masks, and if so desired, could receive their impurity dose during such implant in lieu of being in situ doped during deposition.
  • the desirability of doing so for poly I electrode 23 is materially less, in that this would reduce the differential oxidation rate used to create a thicker oxide layer 27 over that of 26, and could create an undoped region of poly I electrode 23 immediately under the edge of the poly II layer at 33.
  • Fig. 7 is preferably covered by approximately 1,000 nanometers of chemical vapor deposited (CVD) or plasma CVD oxide 36.
  • CVD chemical vapor deposited
  • plasma CVD oxide 36 the structure of Fig. 7 is preferably covered by approximately 1,000 nanometers of chemical vapor deposited (CVD) or plasma CVD oxide 36.
  • CVD chemical vapor deposited
  • plasma CVD oxide 36 the structure of Fig. 7 is preferably covered by approximately 1,000 nanometers of chemical vapor deposited (CVD) or plasma CVD oxide 36.
  • CVD chemical vapor deposited
  • plasma CVD oxide 36 the structure of Fig. 7 is preferably covered by approximately 1,000 nanometers of chemical vapor deposited (CVD) or plasma CVD oxide 36.
  • the importance of having a high temperature refractory metal layer 12 becomes acutely evident with the use of plasma deposition.
  • substrate 1 is covered with a relatively viscous planarization layer 37.
  • Layer 37 is preferably a dielectric such as doped spin-on-glass (SOG) or
  • planar character of surface 38 is then transferred down and into dielectric layer 36 by an isotropic etch of the composite structure using etchants which remove polyimide/SOG and dielectric 36 at substantially equal rates.
  • a representative technique for such etching is described in U.S. Patent No. 4,604,162.
  • the 1:1 etch is continued until the surface of metal 12 is exposed. See Fig. 9. End point detection for the etch can be related to the presence of metal 12 in the etch residuals.
  • the poly I electrode 23 remains dielectrically isolated and substantially decoupled from overlying poly Il/refractory metal electrode 11/12 by the presence of relatively thick oxide layer 27.
  • Upper surface 39 of the substrate is substantially planar, and would likely have even greater planarity if the field oxide regions 4 were replaced with trench structures.
  • the exposed surface of metal 12 is aligned with the poly II electrode 11 and the edge of the poly I electrode 23, obviating the need for contact masking, etching and dimensional compensation.
  • the low resistance of the metal-to- metal contact provides greater latitude in misalignment, yet provides a highly conductive shunt over the full extent of the poly II gate electrode.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

An integrated circuit contact fabrication process forms self-aligned contacts between a second silicon interconnect layer (11) and a metalization layer (9) without photolithographic masking and etching. A step (29) is created at the overlap of the second polysilicon layer (11) with an edge of the underlying first polysilicon layer (23). A refractory metal based layer (12) formed over the second polysilicon is thereafter selectively exposed at the location of the step by successive dielectric formation and planarization operations. The effect of the refractory metal based layer (12) ensures that contacts to the metalization layer (9) are of low resistance and relatively insensitive to misalignments in fabrication.

Description

INTEGRATED CIRCUIT CONTACT FABRICATION PROCESS
Technical Field
This invention relates to integrated circuit contact fabrication processes of the kind including the steps of: forming over an active region of a semiconductor substrate a first patterned electrode layer and an overlying first dielectric layer; forming in the active region and on said first dielectric layer a second electrode layer relatively overlying at least an edge of said first electrode layer, to create a nonplanar step in the region of relative overlap with said first electrode layer; and forming a refractory metal based layer on said second electrode layer, said second electrode layer being patterned to retain the nonplanar step.
Background Art
A process for integrated circuit contact fabrication is known from U.S. Patent No. 4,403,394 and is illustrated in Fig. 1 of the present drawings. As depicted in Fig. 1, the prior art represents a portion of a DRAM cell formed in a lightly doped p- type monocrystalline substrate 1, having an n+ conductively doped region 2 on one side of the active region and a doped polycrystalline silicon layer 3 (poly I) situated at the other side. The active region is bordered on the sides by field oxides 4. Poly I layer 3 is one electrode of a capacitor, which is selectively coupled to conductive region 2 upon the enable ent of the field effect transistor formed by secondly deposited polysilicon gate electrode 6 (poly II) through a channel between region 2 and the substrate proximate electrode 3. An oxide dielectric 7 covers electrode 6. Connections between the poly II electrode layer 6 and subsequent metalization layers are made by contacts using metal 8, formed in known manner by masking and then etching openings through dielectric 7, depositing of a metal layer, and patterning the metalization. The known process has the disadvantage that the concluding contour is far from planar, and that the extent of overlapping between poly I capacitor electrode 3 and poly II gate electrode 6 must be significant to ensure that alignment tolerances do not result in a contact cut down to the level of the poly I layer by a misalignment of the contact cut mask over the edge of poly II layer. A relatively large contact area between metal 8 and poly II electrode 6 is also required to minimize the effects of contact resistance on the conduction of charge to poly II electrode 6.
The known process also has the disadvantage that the' contact masking and etching steps are costly, and furthermore the area of the underlying polysilicon layer must be relatively large to compensate for alignment errors which are introduced by the successive masking operations.
From U.S. Patent No. 4,566,175, there is known a process for forming an access transistor for a one-transistor dynamic RAM cell wherein the gate of the transistor includes a layer of polysilicon and an overlying layer of molybdenum suicide.
Disclosure of the Invention
It is an object of the present invention to provide an integrated circuit contact fabrication process of the kind specified, wherein the aforementioned disadvantages are alleviated.
Therefore, according to the present invention, there is provided an" integrated circuit contact fabrication process of the kind specified, characterized by the steps of: planarizing the structure with second dielectric to selectively expose the surface of the refractory metal based layer; and forming a patterned metalization layer over the second dielectric to make contact with the exposed surface of the refractory metal based layer.
Thus, it will be appreciated that an integrated circuit contact fabrication process according to the present invention has the advantage of providing a self-aligned contact structure and the further advantages of not requiring masking or etching to form contact openings in a dielectric layer, reducing the polysilicon area allocation for mask alignment tolerances, minimizing metal step coverage problems, providing low ohmic resistance contact connections, and providing a degree of planarization for subsequent metalization layers.
In the context of connecting to a DRAM cell field effect access transistor gate electrode, the use of a contact fabrication process according to the invention reduces the "footprint" or area of the contact from the metalization layer to the second polysilicon gate electrode, and thereby measurably reduces undesired capacitive coupling between the gate electrode of the access transistor and the storage capacitor electrode.
Brief Description of the Drawings
Embodiments of the present invention will now be described by way of example, with reference to the accompanying drawings, in which:-
Fig. 1 is a cross-sectional schematic of a DRAM fabricated according to the prior art.
Figs. 2 and 3 illustrate by way of schematic cross sections two embodiments of DRAM cells fabricated according to the present invention.
Figs. 4-9 schematically illustrate in the cross section representative stages in the fabrication sequence which concludes as the embodiment depicted in Fig. 2. Best Mode for Carrying Out the Invention
Structures fabricated according to the present invention are depicted in Figs. 2 and 3 of the drawings. The substantial planarity of the structures is immediately evident. Similarly visible is the minimal overlap between the poly I capacitor electrode 23 and the poly II gate electrode structures 11/12 and 17/18, namely in region 13. The compositely formed gate electrodes, comprising poly II layer 11 or 18 and a selectively deposited refractory metal layers 12 or 17, provide comparatively low resistance electrode structures. Note also that the contacts between the poly II electrode and metalization 9, through intermediate dielectrics, are self-aligned with relation to the edge of poly I electrode 23 by the nonplanar step at location 14. The presence of shunting refractory metal layers- 12/17 minimized contact resistance effects which might otherwise arise with a misalignment of the first metalization layer, such as that at 16, where direct metal-to-metal ensures acceptably low ohmic connection.
A variation to the present process results in the alternate embodiment schematically depicted in Fig. 3. The concluding structure has a shunting refractory metal layer 17 over the upper surface alone of poly II layer 18. Fabrication of the structure in Fig. 3 is believed to be somewhat easier, in that selective deposition of tungsten is not required. However, this variant requires the etching of successive tungsten and polysilicon layers during the formation of the electrode 17/18 pattern.
Practice of the invention according to the preferred embodiment begins with the structure schematically depicted in Fig. 4, where lightly doped p-type monocrystalline silicon substrate 1 is processed to create field oxide regions 4, and thereby define an active region 19 situated medially. The active region is thereafter covered by a thin oxide layer 21, preferably formed to a thickness of approximately 20 nanometers by thermal oxidation of the substrate 1, and a conductively doped polycrystalline silicon layer 22, poly I, deposited by known techniques to a thickness of approximately 500 nanometers. Poly I layer 22 and oxide 21 are then patterned by standard photoresist masking and etching techniques to create the structure depicted in Fig. 5, a capacitor electrode 23 electrically isolated from substrate 1 by an oxide dielectric 24. The patterned poly I layer 23 is then subjected to an oxidation operation suitable to form directly or in a sequence of multiple steps a dielectric suitable to isolate electrode 23 from any succeeding layers of conductive polysilicon. The thickness of the oxide'dielectric immediately over substrate 1, designated as 26 in Fig. 6, is nominally 20 nanometers, while the dielectric layer 27 surrounding capacitor electrode 23 is nominally at least 70 nanometers. The difference in thickness is primarily attributable to the accentuated oxidation rate of doped polysilicon 23 over lightly doped monocrystalline silicon 1. The result is consistent with a preference for having a relatively thin gate oxide dielectric 26 while providing a relatively thicker interelectrode oxide dielectric 27.
As shown in Fig. 6, oxide regions 26 and 27 are covered in the next step of fabrication by a layer of doped polycrystalline silicon 28, poly II, which is in normal manner conformally deposited to the same nominal depth of approximately 500 nanometers as the Poly I layer 22. A feature of this deposition is the creation of step 29 in the contour of poly II layer 28, above the edge of poly I electrode layer 23. Step 29 is attributable to the difference in height between oxide layer 26 on one side and the combination of poly I layer 23 and somewhat thicker oxide layer 27 on the other side.
In progressing to the structure depicted in Fig. 7, the preferred embodiment includes masking and etching to retain a segment, electrode 11, of the poly
II layer 28 over channel region 32, with a small elevated segment overlying poly I electrode 23 at location 33. The preferred practice of the invention next involves a selective deposition of a refractory metal layer 12, such as tungsten to a nominal thickness of 100 nanometers, onto any exposed silicon surface. Tungsten is preferred for its low resistance and high temperature capabilities. Nevertheless, other refractory metals or suicides thereof are also suitable shunting layers. The objective is to create low resistance shunting layers over the doped but relatively higher resistance polysilicon electrode 11.
In keeping with a preferred practice of the invention and progressing towards the structure depicted in Fig. 8, the structure in Fig. 7 is next subjected to an ion implantation using phosphorus or the like to form n+ doped region 2. Polysilicon layers 11 and 23 serve as implant masks to create the alignment between the edge of the poly II and tungsten gate electrode 11/12 and the doped region 2. Relatively thin gate oxide 26 does not materially impede the implant.
A slight variation of the preferred embodiment involves the performance of the implant which produces doped region 2 prior to the selective deposition of refractory metal layer 12. Again the poly I and poly II layers 11 and 23 would serve as self-align masks, and if so desired, could receive their impurity dose during such implant in lieu of being in situ doped during deposition. However, the desirability of doing so for poly I electrode 23 is materially less, in that this would reduce the differential oxidation rate used to create a thicker oxide layer 27 over that of 26, and could create an undoped region of poly I electrode 23 immediately under the edge of the poly II layer at 33.
Following the implant to form doped region 2 and any desired implant annealing operations, the structure of Fig. 7 is preferably covered by approximately 1,000 nanometers of chemical vapor deposited (CVD) or plasma CVD oxide 36. The importance of having a high temperature refractory metal layer 12 becomes acutely evident with the use of plasma deposition. As is illustrated in Fig. 8, following the relatively conformal deposition of oxide layer 36, substrate 1 is covered with a relatively viscous planarization layer 37. Layer 37 is preferably a dielectric such as doped spin-on-glass (SOG) or polyimide, deposited in an amount and manner to form a relatively planar surface 38 over substrate 1. The planar character of surface 38 is then transferred down and into dielectric layer 36 by an isotropic etch of the composite structure using etchants which remove polyimide/SOG and dielectric 36 at substantially equal rates. A representative technique for such etching is described in U.S. Patent No. 4,604,162. The 1:1 etch is continued until the surface of metal 12 is exposed. See Fig. 9. End point detection for the etch can be related to the presence of metal 12 in the etch residuals.
The attributes of the structure illustrated in Fig. 9 should be recognized. First, the poly I electrode 23 remains dielectrically isolated and substantially decoupled from overlying poly Il/refractory metal electrode 11/12 by the presence of relatively thick oxide layer 27. Upper surface 39 of the substrate is substantially planar, and would likely have even greater planarity if the field oxide regions 4 were replaced with trench structures. Note that the exposed surface of metal 12 is aligned with the poly II electrode 11 and the edge of the poly I electrode 23, obviating the need for contact masking, etching and dimensional compensation.
The concluding structure in Fig. 2, as well as the alternate embodiment in Fig. 3, also aptly illustrate the inherent direct metal-to-metal contact between interconnect metalization 9 and shunting metal layers 12/17. The low resistance of the metal-to- metal contact provides greater latitude in misalignment, yet provides a highly conductive shunt over the full extent of the poly II gate electrode.

Claims

CLAIMS : -
1. An integrated circuit contact fabrication process, including the steps of: forming over an active region of a semiconductor substrate (1) a first patterned electrode layer (23) and an overlying first dielectric layer (27); forming in the active region and on said first dielectric layer (27) a second electrode layer (11,18) relatively overlying at least an edge of said first electrode layer (23), to create a nonplanar step (29) in the region of relative overlap with said first electrode layer (23); and forming a refractory metal based layer (12,17) on said second electrode layer (11,18), said second electrode layer (11,18) being patterned to retain the nonplanar step, characterized by the steps of: pianarizing the structure with second dielectric (36,37) to selectively expose the surface of the refractory metal based layer (12,17); and forming a patterned metalization layer (9) over the second dielectric (36,37) to make contact with the exposed surface of the refractory metal based layer (12,17).
2. A process according to claim 1; characterized in that said second electrode layer (11) is patterned prior to the formation of said refractory metal based layer (12); and in that said refractory metal based layer (12) is selectively deposited on said second electrode layer (11).
3. A process according to claim 1, characterized in that said refractory metal based layer (17) is formed prior to the patterning of said second electrode layer (18); and in that patterning of said second electrode layer (18) includes a successive and substantially coextensive etch of said refractory metal based layer (17) and said second electrode layer (18).
4. A process according to claim 1, characterized in that said second electrode layer (11,18) is formed substantially coplanar with said first electrode layer (23) in a first region and substantially over said first electrode layer (23) in a second region, defining said step (29) therebetween.
5. A process according to claim 4, characterized in that said planarizing step includes: forming successive layers of a conformal dielectric (36) and a viscous planarizing dielectric (37) to create a substantially planar surface; etching the surface to remove at substantially equal rates exposed conformal and viscous dielectric (36,37); and terminating the etch upon exposing the refractory metal based layer (12,17).
6. A process according to claim 5, characterized in that said second electrode layer (11,18) is conductively doped polycrystalline or amorphous silicon.
7. A process according to claim 1, characterized in that said refractory metal is tungsten. *
8. A process according to claim 1, characterized in that said refractory metal is a tungsten rich suicide.
9. A process according to claim 1, characterized in that said first and second electrode layers (23;11,8) are formed to approximately the same thickness.
PCT/US1988/003271 1987-10-08 1988-09-23 Integrated circuit contact fabrication process WO1989003589A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE8888909410T DE3874522T2 (en) 1987-10-08 1988-09-23 METHOD FOR PRODUCING CONTACTS IN INTEGRATED CIRCUITS.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10708687A 1987-10-08 1987-10-08
US107,086 1987-10-08

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0226549A1 (en) * 1985-12-20 1987-06-24 STMicroelectronics S.r.l. A monolithic integrated circuit, particularly of either the MOS or CMOS type, and method of manufacturing same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0226549A1 (en) * 1985-12-20 1987-06-24 STMicroelectronics S.r.l. A monolithic integrated circuit, particularly of either the MOS or CMOS type, and method of manufacturing same

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Extended Abstracts, volume 86-2, 19-24 October 1986, (Princeton, NJ, US), C.H. Ting et al.: "Spin-on-glass as a planarizing dielectric layer for multilevel metallization", page 529 *
Journal of the Electrochemical Society, volume 130, no. 9, September 1983, (Manchester, New Hampshire, US), R.M. Levin et al.: "Oxide isolation for double-polysilicon VLSI devices", pages 1894-1987 *

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JPH02501519A (en) 1990-05-24
EP0336951A1 (en) 1989-10-18
DE3874522D1 (en) 1992-10-15
EP0336951B1 (en) 1992-09-09
DE3874522T2 (en) 1993-04-22

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