WO1988009014A3 - Memory addressing system - Google Patents

Memory addressing system Download PDF

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Publication number
WO1988009014A3
WO1988009014A3 PCT/US1988/001388 US8801388W WO8809014A3 WO 1988009014 A3 WO1988009014 A3 WO 1988009014A3 US 8801388 W US8801388 W US 8801388W WO 8809014 A3 WO8809014 A3 WO 8809014A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
cache memory
bits
utilized
output
Prior art date
Application number
PCT/US1988/001388
Other languages
French (fr)
Other versions
WO1988009014A2 (en
Inventor
Joseph Michael Sekel
Donald James Girard
Original Assignee
Ncr Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ncr Co filed Critical Ncr Co
Publication of WO1988009014A2 publication Critical patent/WO1988009014A2/en
Publication of WO1988009014A3 publication Critical patent/WO1988009014A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1054—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently physically addressed

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

A memory addressing system utilizing translated memory address information includes a microprocessor (20), a memory management unit (52) adapted to translate addresses, a cache memory (26) which stores data information and tag information, and a main memory (19). The cache memory (26) is addressed by a 23-bit word which includes a 12-bit index address portion and an 11-bit tag portion. The two most significant bits of the index address portion are stored in a flip-flop device (76). During the next memory cycle the cache memory (26) is addressed using the untranslated least significant 10 bits of the index address together with the two stored bits to provide rapid addressing. The two stored bits are compared in a comparator (80) with the corresponding two new bits after translation, and the cache memory (26) output is utilized for a further comparison if the comparison result is equal. Otherwise, the main memory (19) output is utilized as the system output. The further comparison in a comparator (98) between the new tag information and the tag information read out from the cache memory (26) further determines whether the cache memory (26) or the main memory (19) is utilized for the system output.
PCT/US1988/001388 1987-05-14 1988-04-27 Memory addressing system WO1988009014A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US5079587A 1987-05-14 1987-05-14
US050,795 1987-05-14

Publications (2)

Publication Number Publication Date
WO1988009014A2 WO1988009014A2 (en) 1988-11-17
WO1988009014A3 true WO1988009014A3 (en) 1988-12-15

Family

ID=21967470

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1988/001388 WO1988009014A2 (en) 1987-05-14 1988-04-27 Memory addressing system

Country Status (2)

Country Link
EP (1) EP0314740A1 (en)
WO (1) WO1988009014A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2008313A1 (en) * 1989-05-03 1990-11-03 Howard G. Sachs Cache accessing method and apparatus
JPH09512117A (en) * 1994-04-15 1997-12-02 ゲーエムデー−フォルシュングスツェントルム インフォルマチオンシュテクニク ゲーエムベーハー Data storage cache memory device
WO1995029445A1 (en) * 1994-04-22 1995-11-02 Gmd - Forschungszentrum Informationstechnik Gmbh Cache storage device for data storage
US6807615B1 (en) * 1999-04-08 2004-10-19 Sun Microsystems, Inc. Apparatus and method for providing a cyclic buffer using logical blocks

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4400774A (en) * 1981-02-02 1983-08-23 Bell Telephone Laboratories, Incorporated Cache addressing arrangement in a computer system
EP0206050A2 (en) * 1985-06-28 1986-12-30 Hewlett-Packard Company Virtually addressed cache memory with physical tags

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4400774A (en) * 1981-02-02 1983-08-23 Bell Telephone Laboratories, Incorporated Cache addressing arrangement in a computer system
EP0206050A2 (en) * 1985-06-28 1986-12-30 Hewlett-Packard Company Virtually addressed cache memory with physical tags

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Patent Abstracts of Japan, volume 8, no. 188 (P-297)(1625), 29 August 1984; & JP-A-5975482 (FUJITSU K.K.) 28 April 1984 *

Also Published As

Publication number Publication date
EP0314740A1 (en) 1989-05-10
WO1988009014A2 (en) 1988-11-17

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