WO1988007119A1 - Security and control systems - Google Patents

Abstract

In large installations, for example factories, offices or hotels, security systems are needed. Disclosed herein is a security system which can be easily monitored and controlled. The system includes a central controller connected to a plurality of send/receive unit (1/1), each unit being associated with a lock. Each lock is opened by receipt of a suitable signal from its associated send/receive unit (1/1) which is, in turn, controlled by the central controller.

Description

SECURITY AND COMTROL SYSTEMS

This invention relates to security and control systems .

There are many areas where security, monitoring and control is needed. In particular, such activity is required in the running of large installations, whether they be factories, office buildings or hotels. One particular aspect of such operations concerns access of personnel, either access of the persons themselves to restricted areas or access e.g. to the use of certain equipment or apparatus.

Numerous individual systems have been proposed for highly specific and directed purposes, but up until now little thought has been given to the development and implementation of overall systems. The present invention seeks to overcome this lack, and to provide systems which are usable in a wide variety of configurations over a wide range of security and control applications. Although for the purpose of simplicity and of illustration the invention will be described in what follows with specific reference to an hotel, it is quite clear that analogous systems may be employed in factories or other industrial plant, office buildings, commercial buildings such as airport terminals and other installations. An essential component of systems according to the present invention is a physical lock. This may take many and varied forms, but for simplicity of explanation below will be simply referred to as a lock. In an hotel environment, a variety of different types of lock may be used, for example a lock on a bedroom door, the lock on the door of a refrigerator or mini-bar installed in the bedroom, or a lock on a small safe installed in the bedroom and used for storage of a guest's valuables. Other locks, for example a lock which prevents operation of elevator doors may also be included.

According to the broadest aspect of the present invention there is provided a security and control system including a central controller, a plurality of send and/or receive units connected thereto, and a plurality of locks, each lock being associated with a send/receive unit and with mechanism for opening the lock on receipt of a suitable signal from that unit, the send and/or receive units being connected to the central controller for operation thereby. Preferably the send/receive units take the form of self-contained electronic units, most preferably with their own power supply or back-up power supply, and which if associated with a lock give informatioa about the operating condition of that lock, or which otherwise constitute sensors.

One particular type of send/receive unit of considerable value is a card reader type of unit, which may read a "card" and send information read from the card to the central controller. The card need not be of any particular shape form or construction, and may for example consist of a card with apertures in suitably coded form, a card bearing a bar code , or a card bearing a magnetic stripe on which an appropriate signal has been recorded. In a particularly preferred way of putting the invention into effect, the controller and the various send and/or receive units are connected via a suitable ring cabling and are configured to operate using a token ring system. In a token ring system, all units effectively "watch" the ring to see if any signal is sent round the ring which is addressed to the unit in question. If it is, the signal is captured and appropriate action taken. If not, no action is taken by the particular unit in question. A variety of different approaches may be taken within this general approach, and more details of this are given below.

By operating in accordance with the present invention, and providing an integrated system, very considerable operational facility and efficiency in managing large installations such as factories and hotels can be achieved. In particular, it is often very useful to associate with the central controller apparatus which will issue pass cards which may bear appropriate printed information on them for the user, and appropriate coded information on them for use by the system. Thus for example staff on clocking on may receive cards with magnetic stripes which give them access to appropriate areas but only for the duration of their shift. Various levels of access may clearly easily be provided by appropriate encoding. When guests check in, they may similarly be provided with a card which may remain valid for the period of the intended stay, but which will become invalid thereafter. Clearly, using appropriate digital programming techniques, very large numbers of combinations may be generated and appropriate flexibility of operation achieved. For example for a conference at a hotel, each participant could receive a card which not only enabled him to gain entry to his own room, but also to a hospitality suite.

If desired, the send and/or receive devices which are e.g. used in conjunction with room access may require not only the presence of an appropriately coded card, but in addition the entry, e.g. via a simple numeric key pad, of a personal identification number, which could either be assigned to each guest or which could be chosen by the guest.

In one particular area, the present invention provides an electronic combination lock system adjusted to control a safe deposit box or the like located in a guest room. Quite clearly, security could be substantially compromised if it were possible for the management to open the safe, so in accordance with a further feature of the present invention there is provided an electronic safe installation comprising a container having a lock associated therewith to enable or prevent access to the container, the lock being electronically controlled and adapted to operate only in response to a code entered by a user, and which corresponds to a code previously taught the system by the user, and wherein the system will respond only to such code for a given period of time, and thereafter may be opened using a different code. Thus, the safe is secure for the duration of the guest's stay, but thereafter can be opened without damage by the management.

The implementation of systems in accordance with the present invention may vary very widely. Described below for the purposes of illustration and not limitation are, however, two specific sub-systems of value in connection with the invention, the first being an electronic safe locking system and the second a bus system useful for communicating between a central control computer and the individual send and/or receive units. Turning first to the electronic lock suitable for a room safe, this, as a fixed installation, can conveniently include a small single board micro-processor control unit and key pad.

In broad terms, the key pad may have ten digital keys to enable the entry of numbers, and a small number of function keys for overall control. Thus, for example, to set the safe, which will normally be in an unlocked condition when the guest comes to his room for the first time, a button may be designated for the entry of the security code. Pressing it once puts the system into a learn mode, whereafter the sequence of digits may be entered. It is particularly valuable so to arrange the electronics and micro-processor control that the user may enter the code of his choice of variable length. Thus, for those who did not want very high security or who coul not remember a very long number, a one or two digit code could simply be inserted, and the learn button then pressed again to put the code into the machine's memory. At this stage, the electro-mechan.ical parts of the safe could simply be arranged to lock the safe when the door was next closed. A different actuation button could be provided for use when it was desired to open the safe, and which would be pressed followed by the code put in by the - user. If the code put in matched the code in its memory, the safe could then be opened.

The micro-processor based system may be configured with an appropriate clock to enable it to detect e.g. successive attempts to open the safe but using the wrong code. That could cause an appropriate signal to be admitted to a central controller in order to alert management, and it could also serve to disable the safe from further electronic input, e.g. for the next sixty minutes.

By way of illustration, the accompanying drawing shows, in block diagram form, a micro-processor system which could be used in such circumstances. Referring to that system it will be seen that input is from a suitable key pad or card reader device Bl and the eventual output to a locking mechanism is provided by an output driver B20. This may, for example be an appropriate solenoid which when activated enables a door unlocking action to be effected. A convenient key pad configuration consists of a button called # a button called *, and ten buttons corresponding to the digits from zero to nine.

As can be seen from the drawing, the input device is connected to an interface decoder and multiplexer B2 which is connected in turn to a micro-processor arranged to control, according to an appropriate programme the sequence of logical operations. That central micro-processor is denoted B3. Various associated components are indicated on the drawing, including in particular two memory chips denoted user code memory B4 and master code memory B8. The remaining circuitry is straightforward and its functions explained in what follows. The twelve buttons or pads indicated above may be arranged as a three by four matrix which is scanned by the interface decoder and multiplexer B2. If the $ key is pressed, then this may be interpreted as a start signal which is sent to micro-processor B3 which then in accordance with a predetermined programme decides what to do next. For example it may be programmed that if the next key pressed is the * key then a master code to be memorised is going to be input. If on the other hand the door is locked, pressing the # key followed by the * key could place the apparatus waiting for a further -set of numbers to be input, those numbers corresponding to the already stored code .

If a user code to unlock the locked safe is to be received, the control sequence logic B3 selects the data in the user code memories B4 and B5 via selectors B6 and B7.

Memory B4 holds up to 16 four bit hexadecimal codes which will be necessary to enable a correct entry sequence while B5 contains the code for the number of codes contained in B4.

However, if a master code is to be received then selectors B6 and B7 select the data in the master code memory B8 and B9.

The operation of the logic to compare the input number sequence to the stored number sequence is the same for both master and user codes, the only difference being the memory which supplies the comparison data.

Each number sent from Bl is converted into a time period by B2 synchronised to and following a control signal generated by B2 designated "scan sync". Counter-Latch 310 counts the system clock for the period between the "scan sync" and signal "inputting data" and generates a 4 bit hexadecimal number corresponding to the value of the number sent from Bl.

For each number input, a word counter Bll is incremented having been set to zero by the #, (start) input.

The value of Bll causes the number stored in the equivalent address of memories B4 and B8 to be passed via B6 to B12 while the value of the number being input is passed from BIO to B13.

Logic Blocks B12, B13 and B14 make up a dynamic comparator which compares two static four bit numbers on a bit by bit basis, producing a serial output of one pulse per bit comparison achieved. Input code comparison is achieved' by logic blocks B15 and B16 by a method of bit comparison counting.

Divider B15 is used to decide if the individual numbers in the sequence are correct. For a number to be correct the comparator B14 must have output four correct bit comparisons which are signalled as a pulse per comparison achieved. The pulses are counted by B15 which outputs a single pulse if four are input. The counter is set to zero at the end of each number input sequence thus preventing accumulation of comparator outputs between input numbers. The output of B15 may therefore be considered as a single pulse per correct number entered in sequence.

The main code comparison takes place in B16 which is a counter comparator which carries out several functions. It counts the number of sequentially correct entries, the output of B15. It compares the number of expected entries, output of B7, with the number of actual entries, output of Bll, and it compares the number of current entries, output of B15, with the actual number of entries. If and only if all comparisons equate, B16 generates an equality output which is sent to B17 to initiate an unlock sequence.

If equality is not found then an output is sent to an error counter B18 which is set to zero on entry of a correct sequence and outputs an error after three incorrect successive sequences.

Two timers are employed for output timing. B17 generates a 20 second period during which unlock signal is enabled while B19 generates a 20 minute period which locks out the system after three consecutive errors. Block B20 is an output driver with the capability of driving the power required for electro-mechanical devices.

The user memory is programmed in a similar manner to the entry of an unlock code. At any time when the door which is being controlled, is open or during the twenty second open sequence a memory reprogramme sequence may be initiated. This is achieved by inputting from Bl a # code followed by a "memory" code. This instructs the contr'ol sequence logic B3 to upgrade the user code memory B4 with the entries which follow. Each successive code entered is placed in the memory location indicated by the word counter Bll which is incremented by one count per code. Programming is terminated by the * code which causes the number of codes entered to be stored in latch B5. This procedure allows the user to define the length of code which suits the individual's preference.

Provision is made for the master code memory to be re-programmed in a similar manner to the user code. However, to enable master code programming a control sequence requires the lock to have been operated by the master code prior to re-programming.

For application where self-latching locks are used, an option exists to enable a lock door sequence.

When enabled this sequence requires that prior to closing a self-latching mechanism the # code must be received by the control sequence logic. If a self-latching mechanism is operated without the # signal then the user code would be replaced by a default user code (e.g. '0' or 1234) and at the same time a warning would be sounded to indicated that the user code had been cleared. The electronic circuit shown in the drawing may be fabricated by modern integrated circuit processes which allow the combination of low power memory cells as well as custom logic on the same piece of silicon. This approach requires power to be maintained to the circuit to support the two memories B4 and B8. Modern processes allow very low power consumption when a circuit is placed in a low voltage stand-by mode and such applications will allow a 5 year retention of the memory from a small chemical battery integral with the integrated circuit package. Where longer life is required for the master code and where re-programming of the master code is not required, a non-volatile memory element would be used to replace the chemical cell in the package. In such a case block B8 would be a separate integrated circuit which did not require voltage to support memory retention, e.g. E-Prom, EE-Prom, Rom or diode matrix.

Turning now to the way of connecting a large number of send and/or receive units and a central controller together in a system, we have found that this may be achieved by using a system in which all units are connected together as terminals on a signal transmitting ring. There will now be described a way of operating such a ring as a so-called token ring system with no so-called bus controller operating it, but with each unit simply listening for signals on the ring and transmitting signals to the ring when appropriate.

In order for such systems to work adequately and efficiently, each unit on the ring, denoted a terminal, is designed to receive and re-transmit pieces of data on the ring. Power for doing this should be drawn from the ring wiring itself.

It is particularly preferred to operate with data being handled in two different ways. For example both DC and AC signals may be employed.

It is convenient to characterise the signals placed on the ring into the categories tokens, command words, addresses and data.

There are a number of options for the physical connection which constitutes the data bus. If it does not need to carry power but only signals, fibre-optics may be used. However, it is quite often convenient to use wire systems and these may be two, three or four wire configurations. For example a two wire system may be used with data superimposed on power and with each terminal having a local clock. Four wire systems enable data, power and clock signals to be distributed separately, and three wire systems may be used with two of the three on one wire and the third on another.

Signals may be sent in any convenient format, and in particular in any convenient baud rate. Line characteristics may prevent the use of very high baud rates. Impedance of the bus may vary as desired, e.g. from 50 to 1000 ohms.

The following notes constitute a protocol for data transmission on such a bus. Data Transmission terms.

1. data the bus period for one bit of data - il ¬

period data one half data period logic high followed by half period logic low. data zero half data period logic low followed by half data period logic high, bus clock quarter of data period. period

5. data word 16 periods of 1 of mixed 2. and 3.

Bus Tokens. 1 TOKEN Two data periods logic high followed by two data periods logic low.

ACTIVE Continuous transmission of TOKEN logic .

FREE TOKEN followed by a 8 data periods logic low or continuous logic low not exceeding Y data periods.

QUALIFIED A token following by a data string in multiples of data words. The first data word defines the token type.

,1 Emergency Broadcast (000) 2 Select (001) 3 Request (100) 4 Command (101) 5 Demand (XIX) 5 QUIET Bus has been at a logic low state for a period exceeding 8 data periods.

TIME OUT Y data periods are equivalent to 1.25 milli-sec. Addressed Transmissions. Emergency Broadcast, Select, Request and Demand.

1. Emergency Broadcast.

As in 4.1 above with remaining 13 bits containing the terminal's address.

2. Select. As in 4.2 above with the remaining 13 bits containing the address of the terminal being selected.

3. Request.

As in 4.3 above with the remaining 13 bits containing the address of the terminal requesting the bus.

4. Demand.

As in 4.5 above with the remaining 13 bits containing the address of the terminal demanding the bus. Command transmission. 1. Command.

As in 4.4 above with the remaining 13 bits containing a command word. NOTE: A command word may precede a series of data words depending on the content of the command. Bus Interface. (TERMINAL)

1. An active unit inserted into the Ring Bus.

2. When not intercepting data on the bus, it must pass it through the terminal with a maximum delay of 1 micro second.

3. It must intercept data and not pass it on, under sub-system command.

4. It should be powered from the bus

5. It should always listen to the bus and make available all information to sub-system, even when transmitting.

6. If a sub-system power fails 2. and 4. must apply. Subject to this, it may be part of a monolitich structure. Information from input to output must be the non-inverting DC coupled.

NOTE: The simplest form will be a non-inverting buffer. Bus Transmissons.

1. Negative logic All tokens and data definitions are negative logic.

2. Logic High Min. - 0.4 volts. Max . + 5. 4 vol ts .

3. Logic Low Min. + 1.8 volts

Max. + 5.4 volts

4. Line Voltage Min. - 0.4 volts Max. + 10 volts

Word Length.

1. Command Word 13 Bit

2. Data 16 bit 3 types of data are permissible 3. Address 13 bit

Authority to transmit.

1. The terminal holds the control of the bus by virtue of the token.

2. The last token on the bus was FREE 3. The bus has been QUIET for a period of less than Y data periods.

4. Emergency: When set

5. DEMAND. (See 4.5 above) when authorised may be output by a special terminal to immediately take control of the bus

6. When commanded to (4.4 above to a command word) by a terminal holding the token.

7. Error as in 3. above except only when QUIET is present on the bus for greater than Y DATA PERIODS. 8. A token has not been received within the last Y data periods. NOTE: Emergency is a request for control of bus. See

Power on condition described below. To Generate FREE Free can be output subject to the terminal holding control of the bus. When outputting a free the QUIET is thrown away as received if the bus has been QUIET for less than Y data periods. o Generate ACTIVE This may be done subject to the terminal holding the control of the bus by virtue of the token. To Generate DEMAND (4.5 above)

Only one terminal per bus may be authorised to generate a demand. To Generate COMMAND (4.4 above) 1. Control of the bus must be held

2. All commands must be followed by a COMMAND WORD. To Generate QUIET

A quiet may only be generated by a terminal holding control of the bus and cannot exceed Y DATA PERIODS. Power-On Conditions.

At Power-On a terminal shall force a hardware reset causing all flags to be cleared except the power-on sequence flag (POS) , which shall be set. Terminal output shall be forced to a logical low. All timers in the terminal shall be reset to zero. At the end of the reset a Y Data period counter shall be started.

1. Bus request at power-on is optional.

1.1 If a bus request at power-on is not enabled, terminal shall switch to a Listen only mode at the end of the reset.

2. If bus request at power-on is enabled, at the end of Y Data Period, terminal shall output a bus request

(4.3 above) followed by its own address and the QUIET.

3. Also at the end of the Y data periods. Error computation is enabled. 4. From the end of the reset, the input^' is monitored for bus request plus address (4.3 above). The address is compared with the terminal's own address and acted on as follows:-

4.1 If the received address has higher priority, the terminal shall switch into listen only mode with its bus request flag (BRF) set.

4.2 If the received address has lower priority the terminal shall repeat its transmission of bus request plus address (4.3) followed by QUIET and compare inputs as above.

4.3 If the received address is the terminal's own address then output a bus free.

5. On reception of a bus free, all terminals shall clear their Power-on sequence (POS) flags. Those that were then in a listen only mode are now in STAND-BY. (See below).

6. The terminal which transmitted the bus free may now pick-up control of the bus by outputting a bus request (4.3) after receiving back the bus free (See below) . Error Handling.

Any error identified by a terminal shall be reported onto the bus, giving the address of the reporting terminal.

1. An error is transmitted (reported) by outputting EMERGENCY BROADCAST.

2. When originating or passing an error, every terminal must acknowledge the error with the ERROR bit in its status register.

3. On receipt of an error input, a terminal that generated the error will clear its error condition.

4. Error bits in the status registers are cleared by a bus free token.

5. Valid error states.

5.1 Terminal has had its error flag set by the sub-systems to signify a failure in the sub-system.

5.2 Bus failure type with QUIET ■present for more than Y data periods or no token received within the last Y such periods, has occurred.

5.3 Error detection is inhibited during the Y data Periods following a power-on reset. 6. The error statement applied to the bus as per 1. above can only be output if the terminal itself identified the state. The setting of the error flag by virtue of passing an error transmission is not authority to originate an error transmission. Terminal Stand-by.

When a terminal is inactive and not waiting to send or receive data on the bus, it is said to be in "stand-by" mode.

1. The terminal will be listen only when in stand-by. 2. The terminal cannot be in stand-by if:

2.1 It is selected.

2.2 It is in its power-on sequence.

2.3 It issued a send data and is awaiting the response. 2.4 It is control of the bus

2.5 It is in error sequence.

3. When in stand-by a terminal will respond to:-

3.1 A select command directed to itself.

3.2 An unaddressed command. 3.3 An emergency broadcast.

Status Register.

A status register is not mandatory to a terminal. However, where a status register is employed and the terminal responds to a send status register (SSS) command, then the format will be in the prescribed form: 1. Response to SSS. All addressable terminals must respond to the SSS command and if a status register is not present then the terminal must output a 16 bit status word of zero. 2. Status word definition. The status word contains defined flags plus use defined sub-system status signalling. 4 bits SB12 to SB15 are user definable for sub-system information.

3. Terminal Status SBO to SB6. SBO POS Power-on sequence active

SB1 TEF Terminal emergency flag

SB2 TAF Terminal addressed flag

SB3 TBF Terminal busy flag

SB4 BCF Bus control flag. SB5 BRF Bus request flag

SB6 ERF Error flag

4. Bus status as seen from Terminal

SB7 BQF Bus quiet flag

SB8 BFF Bus free flag SB9 BAF Bus active flag

SB10 BDF Bus demand flag

SB11 TCF Terminal command flag

5. SB12 UF1 User flag one SB13 UF2 User flag two SB14 UF3 User flag three

SB15 UF4 User flag four

Bus Request.

To request control of the bus a terminal will have its BRF status flag set. The TBF must also be set and the BCF unset.

1. If the BAF is set, then listen to bus until FREE is detected then switch to transmit mode and output a bus request, followed by repeated ACTIVE.

2. If the BQF is set then enter the power-on sequence. 3. If the BFF is set then wait for a BQF then enter the power-on sequence. To receive Control of Bus.

1. Control of the bus is received by a terminal when it receives a Request Token (4.3) with its own address, followed by an ACTIVE. 2. If a terminal is authorised to generate DEMAND, control is received when DEMAND is detected at the input.

3. If a terminal is selected and receives a Send System Data (SSD) or Send System Status (SSS) command, it shall set the Bus controller flag and reset its selected terminal flag at the termination of that command sequence, and output a RSD command plus the requested data. NOTE: Control is given up at the end of the data transmission by resetting the Bus Control flag and setting the selected terminal flag. To Release Control of Bus.

1. Unless holding the Bus Control function by virtue of a SSD or SSS command, terminal wishing to release control shall output a free token followed by a Bus Quiet.

2. Control is released and Bus control flag reset on reception of a Bus Request followed by an Active Token. 3. When holding control by virtue of an SSD or SSS command, control is released at the end of the commanded data transmission by resetting the Bus Control flag and setting the terminal flag.

4. On release of Bus Control^'.a terminal will switch into Stand-by»

Transmission Passing.

1. LISTEN ONLY transmissions received and dynamically re-transmitted subject to data not being intercepted. During such transparent operation all Bus messages are listened to an the terminal is said to be LISTEN ONLY. 2. TRANSMIT. Terminal is in transmit mode and monitors return transmisions. This mode is only valid subject to authority to transmission being given.

3. ECHO. Terminal receives data then re-transmits the same data after delay for recognition purposes.

Valid subject to error handling. Command Word Structure.

1. The command word is a 13 bit word.

2. The Command word is split into three groups. 2.1 Terminal Command 6 bits

2.2 Sub-System comand 4 bits

2.3 No. of data words 3 bits following.

3. Bit Designation. 3.1 Most significant bit CB12

3.2 Lease significant bit CBO

4. Defined Commands.

There are six basic commands, each of which is associated to an individual bit of the command word. 5. Command Table.

CB12 ATC Addressed Command

CB11 RSS RESET Sub-systems

CB10 RSD Receive System Data

CB 9 EMS Execute Micro-code CB 8 SSS ^' Send System Status

CB 7 SSD Send System Data

5.1 RSD and SSD are mutually exclusive.

The remaining command bits may be sent as a combinational command in which case the commands are acted upon in sequence of priority of the individual command bits. Priority of sequence is:- ATC,RSS,RSD,EMS,SSS,SSD. 6. Sub-system Commands.

CB6 - CB3 User definable decoded commands. 7. Number of Data Words.

CB2 - CBO Binary decoded word counts for data words following the command word of the current transmission. Terminal Commands. 1. ATC When set to logic ONE only the selected terminal responds to the command otherwise the command is global to all terminals.

RSS When set causes a hardware type reset to any sub-system connected to the terminal. If not set, no action is implied.

RSD Instructs sub-system to receive data. EMS A command to the terminal sub-system to execute hardware/micro-code sequence associated to RSD and sub-system commands.

SSS Instructs terminal to output the contents of the data register in the form of a data word.

6. SSD Instruction to terminal to output the contents of the data register in the form of a data word. 7. POR A command word which has no bits set.

This is an output command which is instructing all terminals to start their power-on sequence.

Command Addressing.

Commands which do not have CB12 (ATC) set. These commands come in two categories:-

1. Non-addressed commands

When CB12 (ATC) is not set, all terminals respond, i.e. Global command. 2. Addressed command.

When CB12 (ATC) is set, only currently selected terminal responds to the command.

Claims

1. A security and control system including a central controller, a plurality of send and/or receive units connected thereto, and a plurality of locks, each lock being associated with a send/receive unit and with mechanism for opening the lock on receipt of a suitable signal from that unit, the send and/or receive units being connected to the central controller for operation thereby.

2. A system according to claim 1, wherein the send/receive units are self-contained electronic units.

3. A system according to claim 2, wherein each self-contained electronic unit has its own power supply.

4. A system according to claim 2 or 3, wherein each self-contained electronic unit has a back-up power supply.

5. A system according to any one of claims 1 to , wherein each send/receive unit includes a card reader which reads information from a card and passes that information to the central controller.

6. A system according to any one of claims 1 to 5, wherein the central controller and send/receive units are connected via a ring system.

7. A system according to any one of the preceding claims, wherein each send/receive unit includes a numeric keypad.

8. A system according to any one of the preceding claims, including an electronic combination lock system.

9. An electronic safe installation comprising a container having a lock associated therewith to enable or prevent access to the container, the lock being electronically controlled and adapted to operate only in response to a code entered by a user, and which corresponds to a code previously taught the system by the user, and wherein the system will respond only to such code for a given period of time, and thereafter may be opened using a different code.

10. An installation according to claim 9, including a single board microprocessor control unit.

11. An installation according to claim 9 or 10, including a keypad which is used both to enter the code into the system and to operate the lock.