WO1988002512A1

WO1988002512A1 - Improvements in pattern recognition apparatus

Info

Publication number: WO1988002512A1
Application number: PCT/AU1987/000325
Authority: WO
Inventors: John Emil Sander
Original assignee: John Emil Sander
Priority date: 1986-10-03
Filing date: 1987-09-23
Publication date: 1988-04-07

Abstract

A pattern recognition system including data processing apparatus interconnected with random-access memory units (R1, R2 and Rn) adapted to be loaded with data representing patterns to be recognised, the memory units being addressable by electrical signals derived from groups of multi-state elements (G1, G2 and Gn) forming a matrix (M), each of the random-access memory units (R1, R2 and Rn) producing digital signal data outputs applicable to an electronic analogue-computer and level-discriminator (C) to perform the summing and comparing operations necessary to select the most probable pattern represented on the matrix as compared to the data already in the memory units, said electronic analogue-computer and level-discriminator including summing means (S1, S2 - Sx) connected to a comparator (C), the whole being arranged firstly to identify very rapidly the particular bit-column of the digital signal data outputs which has the greatest number of bit elements set to a pre-determined state and to identify thereby the unknown pattern to be identified, and secondly to compare the greatest number of bit-column elements set to a predetermined state against a preset threshold number to confirm whether or not the pattern being recognised has at least a particular probability of being correctly recognised.

Description

IMPROVEMENTS IN PATTERN RECOGNITION APPARATUS

This invention relates to certain improvements in pattern recognition apparatus.

It has been found in practice, in pattern recognition machines embodying the concepts described in the paper "Guide to Pattern Recognition Using Random- Access Memories" by I. Aleksander and T. J. Stonham, in Computers and Digital Techniques. February 1979, Vol 2, No 1, that conventional digital processors are relatively slow when very high speed pattern recognition response times are required.

The data processing procedures of summing and comparing, which are required by random-access-memory pattern-recognition machines, are necessarily relatively slow processes if carried out by means of conventional digital processors. Typically time periods of the order of one millisecond are required to process the data read out from the random-access memories in order to decide which pattern, from amongst those previously ' taught ' to the machine, most closely resembles the pattern being identified.

According to the invention much faster data processing of the summing and comparing procedures may be achieved by using certain arrangements of electronic analogue computing elements and multi-input electronic signal-level discriminator units. Pigure 1 is a sketch, of a random-access-memory pattern recognition apparatus in which M is a matrix of various multi-state electronic storage elements PI, P2, ... up to Py, onto which the pattern to be recognised is represented by setting appropriately the electronic state of each of the elements.

Rl, R2, ... up to Rn, are random-access-memory units which each have address-line groups, indicated by Gl,G2,...up to Gn, which , are able.to address all Of the memory locations in th respective random-access- memory units. At each memory location is a group of bi-state (or binary) memory elements called a word. In any given embodiment of the invention there will be at least as many binary-digit (bit) elements comprising each memory word as there are patterns to be recognised. Assume ∑ is the number of patterns to be recognise d.

The random-access-memory address-line groups Gl, G2, ... up to Gn are suitably interconnected with the storage elements in matrix M such that when a pattern is represented by a set of states of the storage elementsPl, P2_* ~. up. to Py, then various appropriate memory locations are addressed in each of the random-access- memory units Rl, R2, ... up to Rn. When the appropriate addresses are impressed on the address-lines of the random-access-memory units Rl, R2, ... up to Rn and the memory units are suitably enabled, by means not shown, then the binary digit (bit) information contents of each addressed word will appear as digital data signals at the data output terminals of each random-access-memory unit.

According to the invention analogue-summing elements SI, S2, ... up to Sx are provided as shown in Fig. 1. The analogue summing elements are designed to produce electrical outputs on each line L1. L2 up o Lx , such that each electrical output has a magnitude which varies as a function of the sum of the binary digits (bits) in the associated bit-column which are set to a binary high-voltage state. (A bit-column is defined in this specification as the column of bits in any designated position in each data output of each random-access-memory unit).

Each of the lines LI, L2, ... up to Lx are connected to appropriate inputs of an analogue level- discrimination apparatus C, which has two principal functions.

The first of the principal functions of C is to identify which of the lines LI, L2, ... up to Lx, has the electrical output of greatest relative magnitude impressed upon it, and then to apply an electrical signal to the corresponding output line 01, 02, ... up to Ox. The second principal function of the discriminating apparatus C is to compare the magnitude of the highest electrical signal it has selected from amongst the lines LI, L2, ... up to Lx, against a reference electrical signal level which has been preset beforehand to correspond with the magnitude of the electrical signal desired as a threshold before the output signal on one of the lines 01, 02, ... up to Ox, is taken as a valid signal by the device, not shown, which is receiving the outputs from the pattern recognition system. If the magnitude of the highest electrical signal is greater than the magnitude of the preset reference level, then a signal i caused to be present ΏΏ. the output fine V so that the receiving device (usually a digital processor) may be informed that the signal it is receiving on one of the output lines 01, 02, ... up to Ox, is a signal which has a high probability of being correct. Alternatively if the magnitude of the greatest electrical signal on lines 01, 02, ... up to Ox, is less than that of the preset reference signal, then no signal is sent on the output line V.and the receiving device may take whatever action it has been programmed for in these circumstances.

By using appropriate analogue-computing elements for units Si, S2, ... up to Sx, in combination with appropriate analogue level-discriminating elements InunitQ the time period required to carry out the necessary summing and comparing data processing procedures may be easily reduced to less than one microsecond. I.e. at least one thousand times faster than the approximately 1 millisecond required if jconventionat digital processor technology wer tobe used instead. As an illustration of embodiments of the invention Fig 2 and Fig 3 show two possible alternative analogue summing elements which may be used to construct the summing units S 1 , S2, ... up to Sx.

In Fig 2 the resistors Bl, B2, ... up to Bn are connected to the appropriate bit-column outputs of the memory units Rl, R2, ... up to Rn. Resistor BF is a suitable feedback resistor connected between the output and the input of the operational amplifier B. The whole assembly forms a simplified example of the well known analogue-computing element, a summing amplifier, used to compute the sum of the electrical input signals. The magnitude of the output signal sent to an input of C is thereby a function of the number of bits in the bit-column which are in a high voltage state.

In Fig 3 a transistor T is connected in the well known grounded-base configuration. In this mode of operation the collector current varies in approximate proportion to the sum of the emitter currents produced by the output terminals in the bit-column which are in a high voltage state.and the magnitude of the output signal sent to an input of C again is a function of the number of bits in the bit-column which are in a high voltage state. Either Fig 2 or Fig 3 can therefore be used as the summing units SI, S2, ... up to Sx, in Fig 1. Note however that the output signal-voltages move in opposite phase in each case, and appropriate level-discriminator units need to be used in C. In Fig 4 is shown one very simple embodiment of an analogue level-discriminator unit which automatically indicates which of its input lines LI, L2, ... up to Lx, has the highest voltage upon it. The indication is given by a signal on one of the output lines 01, 02, ... up to Ox, whichever has the highest magnitude signal impressed on its corresponding input line LI, L2, ... up to Lx.

Fig 4 also shows one simple way in which the verification output signal V can be produced. In this case the reference voltage 3 can be preset so that an output level change on wire Υ occurs whenever the highest magnitude input voltage on one of the L-lines exceeds the level which corresponds to the desired value of a function of the state of the bits in its corresponding bit-column.

Note that many other alternative designs of analogue level-discriminating units_^can he-developed to perform-better than the very simple design illustrated in Fig 4.

Note also that the transistors and the operational amplifiers illustrated in the Figures may be designed or configured to be of the P' or the Ε' type.Or.be bipolar orϊield-effect types, as desired to suit particular requirements of various embodiments of this invention.

Claims

THE CLAIMS DEFINING THE INVENTION ARE AS FOLLOWS:

1. A pattern recognition system including data processing means interconnected with random-access memory units adapted to be loaded with data representing patterns to be recognised, the memory units being addressable by electrical signals derived from groups of multi-state elements forming a matrix, wherein each of the random-access memory units is adapted to produce digital signal data outputs applicable to electronic analogue-computer and level-discriminator means to perform the summing and comparing operations necessary to select the most probable pattern represented on the matrix as compared to the data already in the memory units.

2. A system as claimed in claim 1 wherein said electronic analogue-computer means and level-discriminator means comprises summing means connected to comparator means, the whole being arranged firstly to identify very rapidly the particular bit-column of the digital signal data outputs which has the greatest number of bit elements set to a pre-deter mined state and to identify thereby the unknown pattern to be identified, and secondly to compare the greatest number of bit-column elements set to a pre-deter mined state against a preset threshold number to confirm whether or not the pattern being recognised has at least a particular probability of being correctly recognised.

3. A system as claimed in claim 1 wherein said electronic analogue-computer means and level-discriminator means comprises summing meansxonnecte ioxomparator means, the whole being arranged firstly to identify very rapidly the particular bit-column of the digital signal data outputs which has the greatest number of bit elements set to a particular voltage state and to identify thereby the unknown pattern to be identified, and secondly to compare the greatest number of bit-column elements set to a particular voltage state against a preset threshold number to confirm whether or not the pattern being recognised has at least a particular probability of being correctly recognised.

4. A system as claimed in any of the above claims which embodies electronic circuits similar to those described in the text or in the various Figures forming part of this specification.