WO1988001817A1 - Stations pour communiquer avec des messages chiffres via des cles stockees de maniere circulaire et selectionnees au hasard - Google Patents

Stations pour communiquer avec des messages chiffres via des cles stockees de maniere circulaire et selectionnees au hasard Download PDF

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Publication number
WO1988001817A1
WO1988001817A1 PCT/US1987/002149 US8702149W WO8801817A1 WO 1988001817 A1 WO1988001817 A1 WO 1988001817A1 US 8702149 W US8702149 W US 8702149W WO 8801817 A1 WO8801817 A1 WO 8801817A1
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WO
WIPO (PCT)
Prior art keywords
station
bits
sequence
bit
key
Prior art date
Application number
PCT/US1987/002149
Other languages
English (en)
Inventor
George Tomomitsu Shima
Original Assignee
Unisys Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisys Corporation filed Critical Unisys Corporation
Publication of WO1988001817A1 publication Critical patent/WO1988001817A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/12—Transmitting and receiving encryption devices synchronised or initially set up in a particular manner
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/14—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using a plurality of keys or algorithms
    • H04L9/16—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using a plurality of keys or algorithms the keys or algorithms being changed during operation

Definitions

  • This invention relates to methods of communicatin via encrypted messages from one station to another on communication network, and to circuits for implementin such communication methods.
  • a communication network of the typ with which this invention is concerned includes at leas one station which accepts messages from an operator, an which encrypts and transmits those messages; and i includes at least another station which receives th encrypted messages, decrypts them, and provides th decrypted message to an operator.
  • Such networks are usefu wherever proprietary information needs to be transmitted.
  • the proprietary information might include recommendation from a broker to a client to purchase o sell certain stock, an electronic transfer of funds, military-related data, etc.
  • each person at the receiving station who is to receive a message has his own unique key, and the operator at the transmitting station has all such keys. Then, to encrypt a message for a particular person, the transmitting station uses the key which is assigned to that person.
  • FIG. 1 is a detailed logic diagram of a station which receives, encrypts, and transmits messages in accordance with the present invention
  • FIG. 2 is a flow chart of a program in a micro- processor in FIG. 1 which controls its operation;
  • FIG. 3 is a schematic diagram showing how encryption keys are stored in a memory in FIG. 1;
  • FIG. 4 is a detailed logic diagram of a station which receives and decrypts messages in accordance with the present invention.
  • FIG. 5 is a flow chart of a program in a micro ⁇ processor in FIG. 4 which controls its operation.
  • This station includes a random access read/write memory 10, a random access read only memory 11, an exclusive OR gate 12, a modulator 13, a transmitter 14, a pair of counters 15 and 16, a multiplexor 17, a random number generator 18, a microprocessor 19, and a keyboard/CRT 20. All of these components are intercon ⁇ nected as illustrated via conductors 30a thru 30s.
  • Memory 10 holds the messages which are to be encrypted and transmitted. It is 1 bit wide and N bits long, where N is any integer which is large enough to allow the memory to hold each message individually.
  • Memory 10 has a single data input terminal DI, a single data output terminal DO, a single write control terminal W, and binary address terminals A.
  • Memory 11 by comparison, holds all of the keys which are utilized to encrypt the messages from memory 10. It is 1 bit wide and M bits long, where M is any number which is large enough to allow the memory to store all the encryption keys at the same time. How this is achieve without making memory 11 excessively large will b described shortly in conjunction with FIG. 3.
  • Memory 1 has a single data output terminal DO, and binary addres terminals A.
  • Multiplexor 17 has inpu terminals Al and A2. Address signals on terminals Al an A2 respectively pass through the multiplexor when th control signal on conductor 301 is high and low.
  • Counte 16 has a reset terminal R and a clock terminal CK; an counter 15 has a load data terminal LD and a clock termina CK. When terminal R receives a low signal, counter 1 resets; when terminal CK receives a clock pulse, counter 15 and 16 increment by one; and when terminal LD receives pulse, counter 15 loads a random number from generator 18.
  • FIG. 2 a program in microprocesso 19 which controls the sequence by which the above circuitr operates to encrypt and transmit a message will b described.
  • the program waits for a message that is to be encrypte and transmitted. This message is received by microproces sor 19 from keyboard 20, and it must include a contro word.
  • each control word is chosen such tha it has some secondary meaning to the person for whom th message is intended (i.e., a meaning other than an abstrac sequence of one and zero bits).
  • the contro words can be selected from a large set of data that i personal to the individual for whom a message is intended, such as his Social Security number, his license plat number, his home address, etc.
  • Fro microprocessor 19, as indicated by reference numeral 42 the message is loaded into memory 10. To achieve this, microprocessor 19 forces the signal on conductor 301 to a high state, generates a sequence of consecutive addresses on the conductors 30k, and it generates the bits of the message on conductor 30a and write pulses on conductor 30m in synchronization with the addresses.
  • microprocessor 19 randomly selects an encryption key from memory 11. To achieve this, microprocessor 19 sends a pulse on conductor 30n to generator 18; and in response, signals representing a random number are generated on the conductors 30p. Microprocessor 19 then sends a pulse on conductor 30o which causes the random number on the conduc ⁇ tors 30p to be loaded into counter 15. By this means, a beginning address for memory 11 is randomly selected.
  • the keys in memory 11 are not stored separate from one another. Instead, all of the keys are stored as a single circular sequence of bits; and each bit of this sequence is a bit of many different keys. This circular sequence is illustrated schematically in FIG. 3.
  • reference numeral 50-1 indicates the cell in memory 11 which has address 0
  • reference numeral 50-2 indicates the cell in memory 11 which has address 1
  • reference numeral 50-M indicates the cell in memory 11 which has address M-l.
  • one of these cells is addressed initially in a rando fashion as described above. Thereafter, the cells are addressed by counter 15 by adding one to the previous address in sequential fashion until cell 50-M is addressed. Then the next cell that is addressed by counter 15 is cell 50-1. Then the cells are addressed by adding one to the previous address in a sequential fashion until cell 50-M again reached, at which time the whole sequence repea itself.
  • the encryption key would be 111010... indicated by reference numeral 51 in FIG. 3.
  • the initial address in counter 15 selects ce 50-(M-3)
  • the encryption key, as indicated reference numeral 52 would be 11011001..., etc.
  • the key which is utilized to encrypt a message the circular sequence of bits which is stored in memory beginning at a cell which is randomly selected.
  • microprocessor 19 To activate an actual encryption and transmissi process, microprocessor 19 simply forces signal STARTXMT o conductor 30g to a high state. This is indicated by refe rence umeral 44 in FIG. 2.
  • modulator 1 starts sending CLOCK pulses on conductor 30i. Each CLOC pulse on conductor 30i causes one bit of the message i memory 10 and one bit of the selected key in memory 11 t be exclusively ORed, and the result is modulated b modulator 13 and transmitted by transmitter 14.
  • microprocesso 19 After sending the STARTXMT signal, microprocesso 19 waits for signal ENDXMT on conductor 30h to go high This is indicated by reference numeral 45 in FIG. 2 Signal ENDXMT is forced high by counter 16 after it ha reached a certain count which indicates that the entir message in memory 10 has been encrypted and transmitted When that occurs, microprocessor 20 returns to its quies cent state by forcing signal STARTXMT low.
  • This station includes a random access read/writ memory 60, a random access read only memory 61, a receiver 62, a demodulator 63, a counter 64, a multiplexor 65, an exclusive OR gate 66, a comparator 67, a random access read/write memory 68, a pair of counters 69 and 70, a micro- processor 71, and a keyboard/CRT 72. All of these compo ⁇ nents are interconnected via conductors 80a through 80w as illustrated.
  • Memory 60 stores the encrypted messages which are received for decryption, and it has the same structure as memory 10 of the FIG. 1 station.
  • Memory 61 stores the keys that are utilized to decrypt the messages in memory 60, and it has the same structure and stored bit pattern as memory 11 of the FIG. 1 station.
  • FIG. 4 shows a high level flow chart of a program in microprocessor 71. This program controls the sequence by which the FIG. 4 circuitry operates to receive and decrypt a message.
  • microprocessor 71 forces a STARTRCV signal on conductor 80h to a high level.
  • demodulator 63 receives the next message which passes through receiver 62. As that message is received, demodulator 63 sequentially generates the bits of the message on conductor 80x; and in synchronization with those bits it generates write pulses on conductor 80d and clo pulses on conductor 80c
  • counter 64 In response to each of the clock pulses conductor 80c, counter 64 counts up by one; and the signa from the output of counter 64 are passed through mult plexor 65 to address memory 60. Thus the bits of encrypted message are sequentially loaded into memory 60 consecutively addressed cells beginning at address 0. Whe the message is completely loaded, counter 64 forces ENDRCV signal on conductor 80i to a high state which cause demodulator 63 to stop sending the pulses on conductors 80 and 80d.
  • a high state of signal ENDRCV on conductor 80i i also detected by microprocessor 71 as an indication that message has been received. This is indicated by referenc numeral 92 in FIG. 5.
  • microprocessor 71 forces signal STARTRC on conductor 80h to a low state; and this returns demodu lator 63 to its quiescent state and resets counter 64.
  • microprocessor 72 waits for an operator t enter a control word from keyboard 72.
  • This control word as indicated by reference numeral 94, is then loaded b microprocessor 71 into memory 68. Such loading is achieve by sequentially sending the bits of the control word o conductor 80q in synchronization with addresses on conduc tors 80o and write pulses on conductor 80p.
  • microprocessor 71 selects by chance a decryption key fro memory 61. To do this, microprocessor 71 sends a -pulse o conductor 80s which causes whatever count is in counter 7 to increment by one; and then, it sends a pulse o conductor 80t which causes the contents of counter 70 to b loaded into counter 69.
  • micro ⁇ processor 71 uses the selected key to perform a decryption operation on the control word portion of the message.
  • microprocessor 71 sequentially addresses the bits of encrypted control word in memory 60 via the conductors 80f; and in synchronization therewith it sequentially addresses the bits of the selected key by sending clock pulses on conductor 80r.
  • Each address on the conductors 80f and corresponding clock pulse on conductor 80r results in one bit of the encrypted control word being exclusively ORed via gate 66 with one bit of the selected key.
  • microprocessor 71 addresses via the conductors 80o the corresponding bit of the control word in memory 68; and these signals from gate 66 and memory 68 are compared via comparator 67. Microprocessor 71 monitors the result of each compare operation on conductor 80m. This is indicated in FIG. 5 by reference numeral 97.
  • Counters 69 and 70 are constructed such that they increment by one for each pulse that is received on their CK terminal until they address the last cell 50-M, and then the next pulse on their CK terminal causes their count to recycle back to zero.
  • a primary feature of the above described invention is that it enables messages to be transmitted with an added security over the prior art. This is because with the present invention, the keys are selected at random with human intervention; and no one knows what key is bei utilized to encrypt a particular message. Also, no ke have to be secretly carried from a transmitting station t a receiving station; and different keys are utilized t encrypt different messages for the same individual.
  • Yet another feature of the present invention i that it enables the large number of encryption an decryption keys to be stored in a small number of memor cells.
  • memory 11 of FIG. 1 and memory 6 of FIG. 4 are each one bit wide and one million bits long then, with present technology, they can each be implemente via a single semiconductor chip.
  • Memories 11 and 60 each then store one million keys which are each one millio bits long. By comparison, to store those same key separate from one another would require one million chips which is totally impracticable.
  • counters 15 of FIG. 1 and 69 of FIG 4 have been described as counting up by one in order t address consecutive bits of the keys.
  • thos counters 15 and 69 could alternatively count down by one t address consecutive bits of the keys. In that case, whe they reach a count of zero, they would recycle on the nex CK pulse to address cell M as previously defined.
  • control word portion of each message is fixed a the beginning of the message.
  • control word can be located at the end of the messag or at any other location within the message.

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  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Storage Device Security (AREA)

Abstract

Un réseau de communication du type dans lequel une première station envoie des messages chiffrés à une seconde station est construit de sorte que la première station comprend: un module permettant de choisir une clé de chiffrement d'une manière aléatoire à partir d'une pluralité de clés de chiffrement, et un module pour chiffrer un message par l'intermédiaire de la clé de chiffrement choisie au hasard et transmettre le message chiffré au réseau; et de sorte que la seconde station comprend un module pour recevoir et stocker le message chiffré provenant du réseau, un module pour sélectionner au hasard une clé de déchiffrement parmi une pluralité de clés de déchiffrement, un module pour effectuer une opération de déchiffrement sur une certaine partie du message stocké chiffré à l'aide de la clé de déchiffrement sélectionnée, un module pour comparer le résultat de l'opération de déchiffrement avec un mot de contrôle, un module pour activer de manière répétée les modules de sélection, de déchiffrement et de comparaison cités ci-dessus jusqu'à ce que le résultat de l'opération de déchiffrement concorde avec le mot de contrôle, et un module pour effectuer l'opéation de déchiffrement sur la partie restante du message stocké chiffré, à l'aide de la clé de déchiffrement qui provoque la concordance. Des modules qui choisissent la clé de chiffrement et sélectionnent la clé de déchiffrement comprennent chacun une mémoire qui mémorise une séquence circulaire de bits, un sous-module qui prend un bit particulier parmi tous les bits dans la séquence, et un sous-module qui lit la clé dans la mémoire comme étant le début de la séquence binaire circulaire au niveau du bit particulier.
PCT/US1987/002149 1986-09-02 1987-08-31 Stations pour communiquer avec des messages chiffres via des cles stockees de maniere circulaire et selectionnees au hasard WO1988001817A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US90274286A 1986-09-02 1986-09-02
US90274386A 1986-09-02 1986-09-02
US902,743 1986-09-02
US902,742 1986-09-02

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WO1988001817A1 true WO1988001817A1 (fr) 1988-03-10

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2288519A (en) * 1994-04-05 1995-10-18 Ibm Data encryption
DE19533544A1 (de) * 1995-09-11 1997-03-13 Taschner Hans Joachim Vorrichtungen zum Übertragen einer geheimhaltungsbedürftigen Nachricht und Verfahren zum Betreiben derselben
WO1998029983A1 (fr) * 1996-12-30 1998-07-09 Commonwealth Bank Of Australia Systeme de generation de cles de transaction
FR2800537A1 (fr) * 2000-09-27 2001-05-04 Geneticware Co Ltd Procede et systeme d'emulation d'un code secret entre deux modules materiels
GB2358333A (en) * 1999-10-01 2001-07-18 Geneticware Co Ltd Emulating a secret code between two hardware modules

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2288428A1 (fr) * 1974-10-17 1976-05-14 Ericsson Telefon Ab L M Dispositif de chiffrement et de dechiffrement d'informations
GB2068691A (en) * 1980-02-04 1981-08-12 Philips Nv Method of coding and decoding messages

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2288428A1 (fr) * 1974-10-17 1976-05-14 Ericsson Telefon Ab L M Dispositif de chiffrement et de dechiffrement d'informations
GB2068691A (en) * 1980-02-04 1981-08-12 Philips Nv Method of coding and decoding messages

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IBM Technical Disclosure Bulletin, Volume 24, No. 1B, June 1981, (New York, US) R.E. LENNON et al.: "Isolation of Cryptographic Functions Via Operation Sub-Sets, pages 559-560 see page 560, last paragraph *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2288519A (en) * 1994-04-05 1995-10-18 Ibm Data encryption
DE19533544A1 (de) * 1995-09-11 1997-03-13 Taschner Hans Joachim Vorrichtungen zum Übertragen einer geheimhaltungsbedürftigen Nachricht und Verfahren zum Betreiben derselben
WO1998029983A1 (fr) * 1996-12-30 1998-07-09 Commonwealth Bank Of Australia Systeme de generation de cles de transaction
GB2358333A (en) * 1999-10-01 2001-07-18 Geneticware Co Ltd Emulating a secret code between two hardware modules
GB2358333B (en) * 1999-10-01 2003-06-25 Geneticware Co Ltd Method and system for emulating a secret code between two hardware modules
FR2800537A1 (fr) * 2000-09-27 2001-05-04 Geneticware Co Ltd Procede et systeme d'emulation d'un code secret entre deux modules materiels

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