WO1988000391A1

WO1988000391A1 - Method for providing a metal-semiconductor contact

Info

Publication number: WO1988000391A1
Application number: PCT/US1987/001534
Authority: WO
Inventors: Adam Shepela
Original assignee: Digital Equipment Corporation
Priority date: 1986-06-27
Filing date: 1987-06-26
Publication date: 1988-01-14
Also published as: CA1311565C; AU7694487A; KR880701455A

Abstract

In a process for preparing a silicon-based semiconductor device, prior to the deposition of dielectric and metal for forming the metal interconnect contact, a lift-off mask and metal deposition provide a metal plate contact in the region of the substrate to which the metal interconnect contact is to be connected. The metal plate contact provides protection for the substrate region when the dielectric is being etched to provide a path to the substrate region. The metal interconnect contact is in contact with the metal plate contact rather than directly to the substrate region. This metal plate contact can be a barrier material or, if a second metal layer is connected to the metal plate contact, the second metal layer can be a second barrier layer.

Description

METHOD FOR PROVIDING A METAL-SEMICONDUCTOR CONTACT
BACKGROUND OF THE INVENTION 1. Field of the Invention
This invention relaxes generally to the manufacture of integrated circuits using si-licon
technology and more particularly y to a procedure for the placement of a metal contact onto the surface of a silicon con junction or on to the gate interconnect surface.

2. Description of the Related Art
In the article by D. C. Chen et al, cited above as a related publication, a process is described that can achieve the same purpose, i.e. to provide a layer of material to protect a portion of the substrate against subsequent processing steps.

o I #i y or layer #cr 1 bed in the reference was produced by the deposition of a layer of refractory metal and a layer of amorphous silicon. These two layers were processed using a plurality of steps. Furthermore, the deposition of the material layers was subject to
strict controls to be successful. Finally, the described protective layer was useful only for a self-aligned silicide (salicide) process. These features minimize the usefulness of the protective layer described by hen et al.

A need has therefore been felt for a process that. can provide a protective layer over a junction in a silicon substrate that does not involve critical process control and which has a wider applicability than a single semiconductor junction-contact structure.

FEATURES OF THE INVENTION
It is an object of the present invention to pr;avid-:# aSn. improved process for the manufacture of s4 I#ico#t nLe6zrated circuits.

It is a feature of the present invention to provide an improved process involving the placement of the a metal contact on a region of the substrate that protects the substrate region during further processing.

SUMMARY OF TIlE INVENTION
The aforementioned and other features are obtained, according to the present in.vention, by placing a metal plate in the active area over a silicon junction surface and over the field oxide
encroachment in the active area. After the metal plate is in place and a dielectric deposited, the metal interconnect contact mask is provided as in the related art semiconductor structures. The deposited metal interconnect contact is now coupled to the metal plate instead of the active area of the silicon junction surface. The metal plate acts as an etch stop during the interconnect metal contact etch process and the gaseous species in the plasma etch will not contact the the silicon surface. The metal plate is oversized with respect to the metal interconnect contact so that the metal interconnect contact alignment is less critical.

The metal plate process sequence permits coupling of the metal plate to silicided junctions or to bare surfaces. The metal plate can be a barrier material when it is coupled to a silicided junction or can act as a low contact resistance metal when it contacts a silicon surface.

These and other features of the present invention will be understood upon reading of the following description along with the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a process flow diagram for providing a contact metal. plate for a polycide gate and a silicided junction according to the present invention.

Figure 2 is a process flow diagram for providing a contact metal plate for salicide process with silicide/poly-Si gate and silicided junctions.

Figure 3A is a cross-sectional view of a semiconductor device prior to implementation of the novel steps of the present invention. Figure 3B is a cross-sectional view of a semiconductor device illusltrating some of the steps of 0 the present invention.

Figure 3C is a top view of the semiconductor device and the contact metal plate illustrating one of the advantages of this process.

DESCRIPTION OF TilE PREFERRED EMBODIMENT 1. Detailed Description of the Figures
Referring now to Fig. 1, the contact metal plate process is illustrated for a polycide gate and for a silicided junction. In step 100, the polycide
deposition and etch process are performed on the substrate. The spacer process is performed on the substrate in step 101. In step 103, the oxidation of the polycide and the junction surfaces is performed, while in step 104, the source and drain regions are forllle(l in the substrate. After the ion implant anneal (drive) cycle in step 105 in which the impurities are diffused in the substrate through thermal annealing, the oversized gate area mask is deposited on the device in step 106.

In order to clear (i.e. remove the surface oxides by etching) the junction surfaces, an oxide etch process is performed in step 107. A metal layer is deposited in step 108, and the process forming silicide on the junction surfaces is performed in step 109. In step 110, a masking
suitable for lift-off is applied to the surface to position the contact metal plate. The mask profile is provided with an overhang at the surface. In step 111, the metal for the metal plate is deposited from a directional source. In step 112, the mask is removed from the device and a thick dielectric is applied to the device in step 113. In step 114, the process of p 1 a n a r i z a t i o n of the thick dielectric is performed with rapid --thermal annealing reflow or dielectric back-etch planarization.

In step 115, the mask for the metal interconnect contact is applied to the device and, in step 116, the metal interconnect is deposited on the device.

Referring to Fig. 2, the process flow for applying the contact metal plate of the present invention to a salicide process with silicide/poly-Si gate and silicided junction is illustrated. In step
201, poly-Si is deposited on the substrate and an etch performed. The spacer process implemented in step 202 and, in step 203, the oxidation of the poly-Si and junction surfaces is performed. The implantation of the source and drain areas in the substrate is accomplished in step 204 and the drive cycle, i.e. the diffusion of impurities in the substrate by thermal diffusion, is performed in step 205. In step 206, the poly-Si and junction surfaces are cleared by means of an oxide etch and the metal is deposited on the device is step 207.

The metal is reacted with the silicon to form silicide on the junction surfaces nctanandon rfacCSanthe poly-Si in step 208. In ste or)9, a mask designed for lift-off for the contact metal plate is placed on the device. The mask has a profile with overhang at the surface. In the step 210, the metal for the metal contact plate is deposited using a directional source. In step 211, the contact metal mask is removed from the device and, in step 212, a thick dielectric is deposited on the device. In step 213, the planarization of the dielectric is performed either by rapid thermal
annealing ref low or by dielectric etch back.

The interconnect metal contact mask is applied to the device and the appropriate pattern is etched therein.

In step 215, the metal interconnect is deposited on the device.

Referring next to Fig. 3A, a cross-section view of a semiconductor device is illustrated. This
Figure represents the device process after roughly step 107. Areas 31 are field oxide areas, areas 32 are the regions of ion implantation, structure 33 is a gate oxide area, structures 35 are spacer oxides, while areas 36 are oxide layers and 39 is the substrate.

Referring to Fig. 3B, the same device after the deposition of the metal (step Ill of Fig. I) is
illustrated. Structure 41 includes the structures 36, 35 and 34. The areas 42 are the photoresist regions and areas 45 and 45 'are the deposited metal contact plate. The overhang necessary to facilitate the removal of the photoresist regions. The deposited metal regions 45' will be removed with the photoresist regions.

In Fig. 3C, one advantage of the present invention is illustrated by this top view of the contact metal plate on the processed substrate. The metal contact plate 45 can extend well outside the active area 49. In the related art, the interconnect
contact was constrained to be located inside the active area (illustrated as region 46) to avoid damage to the device during the preparatory processil1g of the substrate.

2.' OPERATION OF THE PREFERRED EMBODIMENT
In the process for coupling selected regions of the semiconductor device, a dielectric material is deposited on the device to provide ultimately insulation between the metal interconnect contact and regions of the device to which electrical coupling is not desired. Then, through the use of an appropriate mask, regions of the dielectric are etched away until the portion of the device to which the metal interconnect contact is to be coupled is reached. The etching process can result in damage to
the now exposed region. The metal plate of the present invention provides a protection for the substrate region to be contacted while still permitting the coupling to the metal interconnect contact when this contact is coupled to the metal plate r.-ather than to the substrate directly.

Although the method for providing a
vertical structure for a silicon contact is longer than the processes of the related art, the procedure provides several advantages. The quality of contact in terms of electromigration resistance is improved because two barrier films can be incorporated into the process. The process is versatile in that it is compatible with poly-silicon, polycide and salicide gate interconnects and with the non-silicided metal contacts to the silicon. This compatibility is summarized in Table A.

5
TABLE A
Process/Device Feature
Gate Interconnect Junction Surface
polycide silicide
poly silicon silicide
polycide metal contact
poly silicon metal contact
salicide salicide
Contact quality potentially can be improved because the silicon contact surface is not exposed to the plasma environment during the interconnect metal conacl step. Minimum transisor dimensions and minimum spacing between transistors are obtainable without enhancements to the lithography or etch process control because the placement of the contact metal plate is less critical as shown illustrated in Fig. 3C.

It will be clear to those skilled in the art that the contact metal plate of the present invention can be used to couple independent
semiconductor devices, can be used to provide a strapping path to a (relatively) remote interconnect path and can be used to interconnect p-type devices and n-type devices on a substrate.

The foregoing description is included to illustrate the operation of the preferred embodiment and is not meant to limit the scope of the invention.

The scope of the invention is to be limited only by the following claims. From the foregoing description, many variations will be apparent to those skilled in the art that would yet be encompassed by the spirit and scope of the invention.

Claims

CLAIMS:

1. A process for coupling a metal interconnect contact to a semiconductor region of a silicon substrate comprising the steps of: preparing said semiconductor region with preseLected processes; forming a lift-off mask for which an exposure area to said silicon substrate includes at least said semiconductor region; depositing a metal layer, said metal layer forming a metal plate coupled to said semiconductor region; removing said lift-off mask; preparing said substrate for deposition of a metal interconnect deposition; and applying said metal interconnect to said metal Iate.

2. The metal interconnect contact coupling process of Claim 1 wherein said depositing a metal layer step comprises the step of depositing said metal layer with a directional source.

3. The metal interconnect contact coupling process of Claim 2 wherein said preparing step comprises the step of preparing said region as a one of a poly-Si region, a polycide region, and a salicided gate.

4. The metal interconnect contact coupling process of Claim 2 wherein said preparing step comprises the step of preparing said region with one of a silicided and a non-silicided metal contacts to said silicon substrate.

5. The metal interconnect contact coupling process of Claim 2 wherein said applying step comprises the step of aligning a metal interconnect contact with said metal. plate.

6. The metal interconnect contact coupling process of Claim 2 further comprising the step of selecting material for said contact metal plate to provide a barrier layer.

7. The metal interconnect coupling process of Claim 6 comprising the step of coupling a second metal layer to said contact metal plate, said second metal layer forming a second barrier layer.

8. The metal interconnect contact coupling process of Claim 2 further comprising the step of depositing a second metal layer on said contact metal plate, said second metal layer being a barrier layer for semiconductor substrate.

9. The metal interconnect contact coupling process of Claim 2 further including the step of using said contact metal plate for a one of interconnecting semiconductor devices, providing a strapping path for the interconnect contact and interconnecting a p-type gate device to an n-type gate device.