WO1987007053A1 - Accumulating recursive computation - Google Patents
Accumulating recursive computation Download PDFInfo
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- WO1987007053A1 WO1987007053A1 PCT/GB1987/000297 GB8700297W WO8707053A1 WO 1987007053 A1 WO1987007053 A1 WO 1987007053A1 GB 8700297 W GB8700297 W GB 8700297W WO 8707053 A1 WO8707053 A1 WO 8707053A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
- G06F7/552—Powers or roots, e.g. Pythagorean sums
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/552—Indexing scheme relating to groups G06F7/552 - G06F7/5525
- G06F2207/5523—Calculates a power, e.g. the square, of a number or a function, e.g. polynomials
Definitions
- Frequency analysis of a waveform is a basic technique in signal processing since certain information carried by a signal can be very di fficult or impossible to extract otherwise than in the frequency domain.
- the range of applications of frequency analysis is very wide, and includes, for exampl e, sonar, radar and image processing.
- the Di screte Fourier Transform is used to compute the frequency domain matrix [X k ] from the time domain series [x n ] according to the equation for an N-point DFT:
- x n is the value of the n th (complex) waveform sample and X k is the amplitude of the k th frequency component.
- the expression (1) and hence also the present invention, is not limited to applications in frequency analysis, but the primary use of the expression is to perform a DFT.
- the DFT may be calculated by various methods, but digital techniques are preferable where hi gh precision is requi red.
- the necessary hardware is simplified greatly if the DFT is calculated by a recursive prime radix transform, as described by T.E. Curtis and J.E.Wickenden in I .E.E. Proceedings Vol .130, Part F, No.5, pages 424-425. Equation (1) may be written in the recursi ve form:
- N which is the transform length
- N which is the transform length
- the transform wi ll be calculated for all k between 0 and N-1.
- An object of this invention is to remove the condition that N be relatively prime to k.
- a processor for computing a value X k from a series of input data x o ..x n ..x N-1 for selected values of k in the range 0 ⁇ k ⁇ N
- Q is any non-zero integer containing no prime factors common to N that are not common to all values of k
- the processor being arranged to calculate and store sequential current values, each current value being the sum o a product component and a sum component, the sum component being he sum of a group of selected data, the number in each group, whi may be one, being derived by multiplying together those prime factors of N which are common to k, and the product component being the product of W Q and the preceding current value, the arrangement being such that a value of X k is obtained for any non-zero Integral value of N.
- the processor may include a kernel arranged to calculate the current values, an accumulator arranged to operate concurrently with the kernel to sum Input data, and a selector adapted to select data to be loaded into the kernel from raw input data and summed data from the accumulator.
- a processor is arranged to compute a value X k from a series of input data x o ..x n ..x N _ 1 for selected values of k in the range 0 ⁇ k ⁇ N
- a processor is arranged to compute a value X k from a series of input data x o ..x n ..x N-1 for selected values of k in the range 0 ⁇ k ⁇ N where
- FIG. 3 is a block diagram of the elements of the processor.
- the powers of W have been written modulo N i.e. as the remainder after dividing by N.
- the rate at which the power of W increases down the W column matrix is equal to Q.
- N is not prime and consequently powers of W occur more than once in rows of the W matrix, so it cannot be re-expressed directly in the simple recursive form of Figures 1c-e.
- Figure 3 shows the computing structure. This could be in software or analogue or digital hardware but for convenience of description it will be treated as digital hardware.
- the kernel constitutes the means for computing the terms W Q X and the final expressions for X k .
- the kernel and accumulator operate concurrently.
- the input data x n are time samples of some signal which is to be analysed in the frequency domain, for example Doppler signals from a radar or vibration from an engine.
- the corresponding frequency components X n are normally computed for all of 0 k N although a subset only may be required in certain applications.
- N and k are chosen by the user according to the application in hand.
- Q is also chosen by the user. Its value is always modulo N, and must not be zero or contain any prime factors common to N that are not also common to each and every value taken by k. (Illegal values of Q do not allow a solution to the recursive form equation (2), since the powers of W required in the direct form, equation (1), cannot be generated).
- the accumulator 1 operates to Load, Sum or Hold.
- the Load operation is used when it is necessary to reinitialise the accumulator, i.e. at the start of each X k computation sequence.
- the current input value x n at A is loaded and held.
- 'Sum' adds the next x n to the stored value.
- 'Hold' simply holds the current stored value, with no loading.
- the data x n are input under the control of some control means (not shown) in the order required for the values of N, k and Q in use.
- the selector 2 operates to select Zero, Accumulate or Raw for the input to the kernel 3. If Accumulate is selected the total from the accumulator 1 is fed into the kernel. If Raw is selected, the Raw input value x n is read off path 4, which is a bypass around the accumulator.
- the facility for selecting Raw data enables parallel processing to take place, as will be described below.
- the kernel 3 also requires reinitialising before the start of each X n computation sequence, and this is achieved by a 'Load' operation. Otherwise, the kernel Computes i.e. multiplies the value it holds (which will initially be zero) by W Q and adds the value selected by the Selector. The sum thus formed provides the new stored value.
- the accumulator is reinitialised (to zero) then loads the first input value, x 5 .
- the accumulator adds the next input x 3 to the stored value x 5 and so on as shown.
- Steps 13 to 18 the accumulator continues to load and sum the Input data x n , but now the selector selects Raw, that is the data loaded Into the kernel is the raw data x n from the bypass path 4.
- This accumulation is completed at Step 18, as the computation of X 1 is completed by the kernel.
- the accumulator 'Holds' its value until Step 19 when it is loaded Into the reinitialised kernel and can be output directly at D as X Q .
- This parallel computation of X 0 and X 1 Increases the speed of computation.
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- General Physics & Mathematics (AREA)
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- Theoretical Computer Science (AREA)
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- General Engineering & Computer Science (AREA)
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Abstract
A processor computes Xk? from a series of data xo?..xn?..xN-1? for 0k<N where Xk? = (I) in a case where W?nk = W?nk N so that Xk? = W?Q(..W?Q (W?Q xN-1? + xN-2?) + xN-3?)...)+x1?) +xo? where Q is any non-zero integer relatively prime to N but where N need not be relatively prime to k. Selected data xn? are fed in one by one and summed in an accumulator (1). Each sum required for a given Xn? is fed to a recursive ''kernel'' (3) where it is multiplied by W the required number of times. While the kernel (3) calculates Xn? the accumulator (1) is concurrently operating on the next data.
Description
Accumulating Recursive Computation.
Frequency analysis of a waveform is a basic technique in signal processing since certain information carried by a signal can be very di fficult or impossible to extract otherwise than in the frequency domain. The range of applications of frequency analysis is very wide, and includes, for exampl e, sonar, radar and image processing. In the majority of applications the Di screte Fourier Transform (DFT) is used to compute the frequency domain matrix [Xk] from the time domain series [xn] according to the equation for an N-point DFT:
xn is the value of the nth (complex) waveform sample and Xk is the amplitude of the kth frequency component.
The expression (1), and hence also the present invention, is not limited to applications in frequency analysis, but the primary use of the expression is to perform a DFT.
The DFT may be calculated by various methods, but digital
techniques are preferable where hi gh precision is requi red. The necessary hardware is simplified greatly if the DFT is calculated by a recursive prime radix transform, as described by T.E. Curtis and J.E.Wickenden in I .E.E. Proceedings Vol .130, Part F, No.5, pages 424-425. Equation (1) may be written in the recursi ve form:
Xk = Wk(... (Wk(Wkx(N-1 ) + x(N-2)) + x(N_3) )... )+x1)+x0 (2)
and in the case that N and k are relatively prime and nk can be written modulo N i.e. Wnk = w(nk±N), the terms Wk in equation (2) can be replaced by WQ where Q is any non-zero value containing no prime factors common to N that are not common to all values of k. The advantages of this approach are that the DFT can be performed using only add/rotate operations rather than multiply operations which are ouch more complex to implement digital ly. The value Q can be chosen for ease of implementation and it is fixed for al l k (except k=0), whereas equation (1) requi res a different rotation for each value of k. N, which is the transform length, will typical ly be several hundred or more, and, in general , the transform wi ll be calculated for all k between 0 and N-1. To make N and k relati vely prime therefore means essential ly that N must be prime. This excludes the use of 'easy ' numbers such as N=500 which has factors 2,4,5,10 and so on, in addition to 1 and 500. Convenient binary numbers, such as 512 are also excluded since these will also have many factors.
Another drawback of this prime radix technique is that the D.C. component Xo can only be computed either by re-setting Q to zero, or in a separate accumulating device.
An object of this invention is to remove the condition that N be relatively prime to k.
According to one aspect of the invention a processor for computing a value Xk from a series of input data xo..xn..xN-1 for selected values of k in the range 0≤ k<N where
where Q is any non-zero integer containing no prime factors common to N that are not common to all values of k, the processor being arranged to calculate and store sequential current values, each current value being the sum o a product component and a sum component, the sum component being he sum of a group of selected data, the number in each group, whi may be one, being derived by multiplying together those prime factors of N which are common to k, and the product component being the product of WQ and the preceding current value, the arrangement being such that a value of Xk is obtained for any non-zero Integral value of N.
The processor may include a kernel arranged to calculate the current values, an accumulator arranged to operate concurrently with the kernel to sum Input data, and a selector adapted to select data to be loaded into the kernel from raw input data and summed data from the accumulator.
According to another aspect of the invention a processor is arranged to compute a value Xk from a series of input data xo..xn..xN_1 for selected values of k in the range 0≤k<N where
in a case where Wnk = Wnk ± N so that
xk =WQ(..WQ (WQxN-1+xN-2) +xN-3)...)+x1) +x0
where Q is any non-zero integer containing no prime factor coomon to which is not common to all selected values of k, the processor being arranged to calculate Xk by
1) summing those terms xn for which |nk|N = m for n = 0 to N - 1, for each volume of m between 0 and N - 1 in steps of Q ii) multiplying the summed xn terms for each m by W l mQlN to produce product terms iii) summing the product terms over all m to produce Xk.
According to another aspect of the Invention a processor is arranged to compute a value Xk from a series of input data xo..xn..xN-1 for selected values of k in the range 0≤ k<N where
in a case where Wnk = Wnk ± N so that
Xk=WQ(..WQ- (WQxN-1+xN-2) +xN_3)...)+x1) +x0
where Q is any non-zero integer containing no prime factor common to N which is not common to all selected values of k, the processor being arranged to calculate Xk by i) setting m = N-1,
11 ) multiplying by W0- to produce a product, iii ) summing those terms xn for which|nk| N m for n= 0 to N - 1, iv) adding said sum and said product to produce a new stored current value, v) setting m = m - 1 vi) repeating steps (ii) to (v) until m = 0, the stored current value then being equal to Xk.
One embodiment of the invention will now be described by way of example with reference to the accompanying drawings of which:-
Figure 1 shows matrix expansions of the Xk series for N = 5 and for various values of Q;
Figure 2 shows the case for N = 6 in matrix rotation;
Figure 3 is a block diagram of the elements of the processor; and
Figure 4 is a table showing the operation of the processor for the case N = 6.
Referring to the drawings, Figure 1a is a direct expansion of Equation (1) for the case N = 5. In Figure lb the powers of W have been written modulo N i.e. as the remainder after dividing by N. In this case, N happens to be prime, and therefore relatively prime to all k, and it will be observed that except for k = 0, each power of W appears once in each row of the W matrix. Figures 1c, d and e show
matrix expansions of the recursive form of the series with Q = 1, 2 and 3 respectively. The same terms are being evaluated, but in a different order. The rate at which the power of W increases down the W column matrix is equal to Q.
Figure 2(a) shows the case of N = 6 in matrix notation, with the powers of W written modulo N. N is not prime and consequently powers of W occur more than once in rows of the W matrix, so it cannot be re-expressed directly in the simple recursive form of Figures 1c-e. Instead, the elements of the x square matrix shown 1n Figure 2b for Q = 1 are sums of a number (F) of xn terms spaced along each row by F = 1 zero elements. The number of terms, F, is found by selecting those prime factors of N which are common to the prevailing k. For example, prime factors of N = 6 are 1, 2 and 3. For k = 2, say, factor 3 is not common, which leaves the factors 1 and 2, which, multiplied together give F = 2. Thus F = 2 for N = 6, k = 2, Q = 1. When N and k are relatively prime, as with N = 5, then F = 1 for all k and the matrix structure reverts to that of Figures 1c-e.
This more general matrix structure based on sums of F terms automatically incorporates the case for Xo which fits, into the pattern with F = N. (In this case of k - 0, it should be noted that all numbers are factors of zero). Despite the apparent complexity of the x matrix, there is no extra data to be handled, it is just that some data has to be summed before processing. The case for N = 6 is illustrated for the sake of simplicity, but in general N will be much larger -typically of the order of hundreds of thousands; the same rules apply however for all N. N is the transform length , a fundamental parameter that often directly affects system performance. The removal of the requirement that N be prime (which would previously have been necessary to achieve the recursive matrix form of Figures 1 c, d or e) allows greater choice and wider and simpler application of the control algorithm.
Figure 3 shows the computing structure. This could be in software or analogue or digital hardware but for convenience of description it will be treated as digital hardware. There are three components, an accumulator 1, a selector 2 and a kernel 3. The kernel constitutes the means for computing the terms WQX and the final expressions for Xk. The kernel and accumulator operate concurrently.
The input data xn are time samples of some signal which is to be analysed in the frequency domain, for example Doppler signals from
a radar or vibration from an engine. The corresponding frequency components Xn are normally computed for all of 0 k N although a subset only may be required in certain applications. N and k are chosen by the user according to the application in hand. Q is also chosen by the user. Its value is always modulo N, and must not be zero or contain any prime factors common to N that are not also common to each and every value taken by k. (Illegal values of Q do not allow a solution to the recursive form equation (2), since the powers of W required in the direct form, equation (1), cannot be generated). The particular value of Q may be chosen for simplicity (e.g.Q = 1), or to achieve some specific implementation advantage.
As indicated in Figure 3, the accumulator 1 operates to Load, Sum or Hold. The Load operation is used when it is necessary to reinitialise the accumulator, i.e. at the start of each Xk computation sequence. The current input value xn at A is loaded and held. 'Sum' adds the next xn to the stored value. 'Hold' simply holds the current stored value, with no loading. The data xn are input under the control of some control means (not shown) in the order required for the values of N, k and Q in use.
The selector 2 operates to select Zero, Accumulate or Raw for the input to the kernel 3. If Accumulate is selected the total from the accumulator 1 is fed into the kernel. If Raw is selected, the Raw input value xn is read off path 4, which is a bypass around the accumulator. The facility for selecting Raw data enables parallel processing to take place, as will be described below.
The kernel 3 also requires reinitialising before the start of each Xn computation sequence, and this is achieved by a 'Load' operation. Otherwise, the kernel Computes i.e. multiplies the value it holds (which will initially be zero) by WQ and adds the value selected by the Selector. The sum thus formed provides the new stored value.
The value at each point A,B,C,D in the processor is shown in the data table of Figure 4, which also shows the mode of operation of the three processor elements at each step in the computation, which is illustrated for N = 6, Q = 1.
At step 1, the accumulator is reinitialised (to zero) then loads the first input value, x5. At step 2, the accumulator adds the next input x3 to the stored value x5 and so on as shown. Steps 1 to 6 compute X3, with F = 3, the accumulator and kernel are then
reinitialised (Load) and steps 7 to 12 compute X2, with F = 2. At Steps 13 to 18 the accumulator continues to load and sum the Input data xn, but now the selector selects Raw, that is the data loaded Into the kernel is the raw data xn from the bypass path 4. The kernel thus computes X1, for which F = 1 so no accumulation is required and the accumulator meanwhile accumulates the data for the Xo term, for which F = 6. This accumulation is completed at Step 18, as the computation of X1 is completed by the kernel. The accumulator 'Holds' its value until Step 19 when it is loaded Into the reinitialised kernel and can be output directly at D as XQ. This parallel computation of X0 and X1 Increases the speed of computation.
Claims
1. A processor arranged to compute a value Xk from a series of Input data xo..xn..XN-1 for selected values of k in the range 0≤k<N where
In a case where Wnk = Wnk ± N so that
Xk=WQ(..WQ (WQxN-1 +xN_2) +xN-3)...)+x1) +x0
where Q is any non-zero integer containing no prime factor common to N which is not common to all selected values of k, the processor being arranged to calculate and store sequential current values, each current value being the sum of a product component and a sum component, the sum component being the sum of a group of selected data, the number in each group, which may be one, being derived by multiplying together those prime factors of N which are common to k, and the product component being the product of WQ and the preceding current value, the arrangement being such that a value of Xk is obtained for any non-zero integral value of N.
2. A processor according to Claim 1 comprising a kernel arranged to calculate said current values, an accumulator arranged to operate concurrently with said kernel to sum input data, and a selector adapted to select data to be loaded into said kernel from raw input data and summed data from said accumulator.
3. A processor arranged to compute a value Xk from a series of input data xo..xn..xN-1 for selected values of k in the range 0≤k<N where
Xk =WQ(..WQ (WQxN-1 +xN-2) +xN-3)...)+x1) +x0
where Q is any non-zero integer containing no prime factor common to N which Is not common to all selected values of k, the processor being arranged to calculate Xk by
4. A processor arranged to compute a value Xk from a series of input data x0..xn..xN-1 for selected values of k in the range 0≤k<N where
In a case where Wnk = Wnk ± N so that
Xk = WQ(..WQ (WQxN-1 +xN-2) +xN-3)...)+x1) +x0
where Q is any non-zero integer containing no prime factor common to N which is not common to all selected values of k, the processor being arranged to calculate Xk by
1) setting m = N-1, ii) multiplying by WQ to produce a product, iii) summing those terms xn for which|nk|N = m for n = 0 to
N - 1, iv) adding said sum and said product to produce a new stored current value, v) setting m = m - 1 vi) repeating steps (11) to (v) until m = 0, the stored current value then being equal to Xk.
5. A processor according to Claim 4 wherein two or more of steps (ii) to (v) are performed concurrently.
6. A processor substantially as hereinbefore described with reference to the accompanying drawings.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8611124 | 1986-05-07 | ||
GB868611124A GB8611124D0 (en) | 1986-05-07 | 1986-05-07 | Accumulating recursive computation |
Publications (1)
Publication Number | Publication Date |
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WO1987007053A1 true WO1987007053A1 (en) | 1987-11-19 |
Family
ID=10597457
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/GB1987/000297 WO1987007053A1 (en) | 1986-05-07 | 1987-05-06 | Accumulating recursive computation |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0273921A1 (en) |
JP (1) | JPH01500779A (en) |
GB (2) | GB8611124D0 (en) |
WO (1) | WO1987007053A1 (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0629969A1 (en) * | 1993-06-14 | 1994-12-21 | Motorola, Inc. | Artificial neuron and method of using same |
EP0661646A2 (en) * | 1994-01-03 | 1995-07-05 | Motorola, Inc. | Neuron circuit |
US5553012A (en) * | 1995-03-10 | 1996-09-03 | Motorola, Inc. | Exponentiation circuit utilizing shift means and method of using same |
US5574827A (en) * | 1993-06-14 | 1996-11-12 | Motorola, Inc. | Method of operating a neural network |
US5644520A (en) * | 1995-05-31 | 1997-07-01 | Pan; Shao Wei | Accumulator circuit and method of use thereof |
US5685008A (en) * | 1995-03-13 | 1997-11-04 | Motorola, Inc. | Computer Processor utilizing logarithmic conversion and method of use thereof |
US5771391A (en) * | 1995-08-28 | 1998-06-23 | Motorola Inc. | Computer processor having a pipelined architecture and method of using same |
US6054710A (en) * | 1997-12-18 | 2000-04-25 | Cypress Semiconductor Corp. | Method and apparatus for obtaining two- or three-dimensional information from scanning electron microscopy |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2276960B (en) * | 1993-04-08 | 1997-06-25 | Marconi Gec Ltd | Processor and method for dft computation |
-
1986
- 1986-05-07 GB GB868611124A patent/GB8611124D0/en active Pending
-
1987
- 1987-05-06 WO PCT/GB1987/000297 patent/WO1987007053A1/en not_active Application Discontinuation
- 1987-05-06 GB GB08710679A patent/GB2191316A/en not_active Withdrawn
- 1987-05-06 EP EP19870902646 patent/EP0273921A1/en not_active Withdrawn
- 1987-05-06 JP JP50286487A patent/JPH01500779A/en active Pending
Non-Patent Citations (1)
Title |
---|
IEEE Proceedings, Volume 130, part F, No. 5, August 1983, (Old Woking, Surrey, GB), T.E. CURTIS et al.: "Hardware-based Fourier Transforms: Algorithms and Architectures", pages 423-433 see paragraph 2.2 * |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5781701A (en) * | 1993-06-14 | 1998-07-14 | Motorola, Inc. | Neural network and method of using same |
US5574827A (en) * | 1993-06-14 | 1996-11-12 | Motorola, Inc. | Method of operating a neural network |
US6151594A (en) * | 1993-06-14 | 2000-11-21 | Motorola, Inc. | Artificial neuron and method of using same |
EP0629969A1 (en) * | 1993-06-14 | 1994-12-21 | Motorola, Inc. | Artificial neuron and method of using same |
US5720002A (en) * | 1993-06-14 | 1998-02-17 | Motorola Inc. | Neural network and method of using same |
EP0661646A2 (en) * | 1994-01-03 | 1995-07-05 | Motorola, Inc. | Neuron circuit |
EP0661646A3 (en) * | 1994-01-03 | 1995-12-20 | Motorola Inc | Neuron circuit. |
US5553012A (en) * | 1995-03-10 | 1996-09-03 | Motorola, Inc. | Exponentiation circuit utilizing shift means and method of using same |
US5726924A (en) * | 1995-03-10 | 1998-03-10 | Motorola Inc. | Exponentiation circuit utilizing shift means and method of using same |
US5685008A (en) * | 1995-03-13 | 1997-11-04 | Motorola, Inc. | Computer Processor utilizing logarithmic conversion and method of use thereof |
US5644520A (en) * | 1995-05-31 | 1997-07-01 | Pan; Shao Wei | Accumulator circuit and method of use thereof |
US5771391A (en) * | 1995-08-28 | 1998-06-23 | Motorola Inc. | Computer processor having a pipelined architecture and method of using same |
US6054710A (en) * | 1997-12-18 | 2000-04-25 | Cypress Semiconductor Corp. | Method and apparatus for obtaining two- or three-dimensional information from scanning electron microscopy |
Also Published As
Publication number | Publication date |
---|---|
EP0273921A1 (en) | 1988-07-13 |
GB2191316A (en) | 1987-12-09 |
JPH01500779A (en) | 1989-03-16 |
GB8710679D0 (en) | 1987-06-10 |
GB8611124D0 (en) | 1986-06-11 |
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