WO1987003424A1 - Semiconductor devices - Google Patents

Semiconductor devices Download PDF

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Publication number
WO1987003424A1
WO1987003424A1 PCT/GB1985/000537 GB8500537W WO8703424A1 WO 1987003424 A1 WO1987003424 A1 WO 1987003424A1 GB 8500537 W GB8500537 W GB 8500537W WO 8703424 A1 WO8703424 A1 WO 8703424A1
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WO
WIPO (PCT)
Prior art keywords
layers
superlattices
barrier layer
gaas
super
Prior art date
Application number
PCT/GB1985/000537
Other languages
French (fr)
Inventor
Richard Alun Davies
Michael Joseph Kelly
Original Assignee
The General Electric Company, P.L.C.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US06/799,627 priority Critical patent/US4645707A/en
Application filed by The General Electric Company, P.L.C. filed Critical The General Electric Company, P.L.C.
Priority to PCT/GB1985/000537 priority patent/WO1987003424A1/en
Priority to JP60505180A priority patent/JPS63501459A/en
Publication of WO1987003424A1 publication Critical patent/WO1987003424A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/151—Compositional structures
    • H01L29/152—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
    • H01L29/155—Comprising only semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/88—Tunnel-effect diodes

Definitions

  • This invention relates to semiconductor devices.
  • the invention relates to semiconductor devices incorporating a superlattice.
  • Superlattices comprise a periodic structure consisting of alternating ultra-thin layers of two different semiconductor materials, the semiconductor materials being chosen such that there is a misalignment of energy band edges between each pair of adjacent layers, with the layers of one of the materials constituting potential barriers to charge carriers passing through the superlattice.
  • the original work on these structures was performed by L. Esaki and L.L. Chang, and is described in Physical Review Letters, Volume 33, pages 495 to 498.
  • a recent review article on superlattices is given in Proceedings of the 17th International Conference on Physics of semiconductors, edited by Chadi and Harrison, Published by Springer Verlag in 1985, pages 473 to 483.
  • a semiconductor device in accordance with the invention achieves this object by comprising two super ⁇ lattices each comprising alternating layers of two -different semiconductor materials such that there is a misalignment of energy band edges between each pair of adjacent layers with the layers of one of the materials constituting potential barriers to charge carriers passing through each superlattice, said superlattices being coupled to each other by a barrier layer of semiconductor material forming respective heterojunctions with the adjacent layers of the superlattices ,said barrier layer having a lower transmission coefficient for said charge carriers than said layers of said one material, said superlattices defining the allowed energy levels of said charge carriers at either side of said barrier layer and the value of a potential applied across said barrier layer determining the current-voltage characteristics of the device.
  • Figure 1 is a schematic side view of a device in accordance with the invention, with the vertical scale greatly expanded for clarity;
  • Figure 2 shows the measured current voltage characteristic of the device
  • Figure 3 illustrates part of the true current voltage characteristic of the device
  • Figure 4 illustrates part of the conduction band for the central portion of the device, at four different applied bias voltages.
  • the device comprises two compositional superlattices 1 , 3 separated by a 8 nanometre thick barrier layer of Al n u.•»_ c _>Ga ⁇ U. (- c D ⁇ s 5.
  • Each superlattice 1 , 3 is constituted by ten layers of A1 Q t eac - approximately 3 nanometres thick, alternating with ten layers of GaAs 9 each approximately 6 nanometres thick.
  • Each GaAs layer 9 within the super ⁇ lattices 1 , 3 is doped with silicon.at a level of 4 X 10 17cm-3 over the central 2 nanometres.
  • Respective approximately 2 nanometre thick GaAs layers 11, 13 are formed at the end of each superlattice remote from the barrier layer 5, with respective 40 nanometre thick GaAs layers 15, 17 doped with silicon to 10 17cm-3 being formed at either side of the layers 11, 13.
  • Further capping layers 19, 21 of GaAs doped with silicon to 10 cm " are formed on the layers 15, 17 respectively, the whole device being formed on a GaAs substrate 23 separated from the layer 21 by a very thin layer 25 of AlAs, between 0.5 to 1 nanometre thick which acts as a barrier to defect diffusion from the substrate.
  • the device as described is grown by molecular beam epitaxy from the substrate 23. Respective electrical contacts (not shown) are then formed to the upper capping layer 19 and by etching to the lower capping layer 21.
  • the current voltage characteristics shown in Figure 2 may be measured.
  • the most notable features in these curves are the discontinuous voltage steps at certain currents which exhibit a hysteresis dependent on the direction of the current sweep. It is well known in the art of measurement of such semiconductor characteristic curves that self resonance due to the reactance of the device and the measuring circuit causes such measured characteristics to deviate from the true current voltage characteristic. Measurement of the derivative ⁇ V/ " dI shows that this derivative diverges as the discontinuity in voltage is approached, i.e. that the slope 'dl ⁇ V becomes zero. This behaviour indicates that the true I-V characteristic is of the general form shown in Figure 3, this characteristic showing a region of negative differential conductivity, the value of V shown in this Figure being the potential drop across the " layer 5, most of the voltage across the device being actually dropped across this layer.
  • the I-V characteristics of the device are temperature independent below about 100K. Above this temperature as can be seen in plots (b) and (c) in Figure 2 the voltage steps decrease with temperature and the hysteresis loops shrink and eventually disappear leaving a smooth characteristic at room temperature which is only slightly non-ohmic. In the ohmic regions away from the voltage steps the resistances measured at each temperature are very similar. The measurements shown in Figure 2 were taken under dark conditions, but were unchanged under illumination of the device.
  • the bound electron states in the wells overlap forming -minibands 1 of typical widths and separations of tens of illielectron volts.
  • the first two such minibands are shown in Figure 4, the first minibands 31 , or 32 having a width of E, and being separated from the second minibands 35, or 36 by respective energy gaps of E .
  • the doping levels for the GaAs layers 11 within the device are chosen such that the Fermi level E f lies near the middle of the first miniband 31 or 32 as shown, the doping being spaced away from the AlGaAs layers to minimise problems associated with deep donors.
  • the amount of negative differential conductance may be increased in several ways. Firstly the gap in energy E between the first and second minibands can be increased g by decreasing each well thickness within each superlattice
  • the current density of the device can be increased by making the layer 5 constituting the thick tunnel barrier thinner. This will also increase the relative amount of direct tunnelling and so increase the peak to valley ratio of the current swing again improving available power, efficiency and increasing the operating temperature. As however most of the applied bias must be dropped across this layer, the thickness of this layer cannot be reduced too much. A thickness of twice the barriers within the super- lattices 1,3 is regarded as a good compromise.
  • the practical upper limit on the operating frequency of the device is determined by the capacitance associated with the high field region around the thick barrier layer but the greater current density associated with thinner barrier layers allows a much smaller area device to be used for the same output power, thus giving a reduction in capacitance even for relatively thin layers.
  • the device described herebefore by way of example includes two compositional superlattices in the GaAs/AlGaAs system, many other combinations of material are possible, e.g. doping superlattices, and materials in the InAs/GaSb system. Furthermore the two superlattices need not be identical.
  • the barrier layer coupling the two superlattices is of the same material as but thicker than the layers of material constituting potential barriers within the two super ⁇ lattices
  • this barrier layer it is possible for this barrier layer to be of a different material, as long as it can form respective heterojunctions with the adjacent layers of the super ⁇ lattices.
  • the barrier layer is of a different material, it need not necessarily be thicker than the layers of material constituting the potential barriers within the two superlattices as long as it has a lower transmission coefficient for the charge carriers passing through the device than the potential barriers of the superlattices, i.e. such that a* significant part of a voltage applied across the device appears across the barrier layer.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Recrystallisation Techniques (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A semiconductor device incorporating two superlattices (1, 3) in the GaAs/AlGaAs system separated by a relatively thick layer (5) of GaAlAs. The device displays negative differential conductance.

Description

Semiconductor Devices
BACKGROUND OF THE INVENTION 1. Field of the invention
This invention relates to semiconductor devices. In particular the invention relates to semiconductor devices incorporating a superlattice. 2. Description of the Prior Art
Superlattices comprise a periodic structure consisting of alternating ultra-thin layers of two different semiconductor materials, the semiconductor materials being chosen such that there is a misalignment of energy band edges between each pair of adjacent layers, with the layers of one of the materials constituting potential barriers to charge carriers passing through the superlattice. The original work on these structures was performed by L. Esaki and L.L. Chang, and is described in Physical Review Letters, Volume 33, pages 495 to 498. A recent review article on superlattices is given in Proceedings of the 17th International Conference on Physics of semiconductors, edited by Chadi and Harrison, Published by Springer Verlag in 1985, pages 473 to 483. SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device incorporating a super¬ lattice, the device exhibiting negative differential conductance.
A semiconductor device in accordance with the invention achieves this object by comprising two super¬ lattices each comprising alternating layers of two -different semiconductor materials such that there is a misalignment of energy band edges between each pair of adjacent layers with the layers of one of the materials constituting potential barriers to charge carriers passing through each superlattice, said superlattices being coupled to each other by a barrier layer of semiconductor material forming respective heterojunctions with the adjacent layers of the superlattices ,said barrier layer having a lower transmission coefficient for said charge carriers than said layers of said one material, said superlattices defining the allowed energy levels of said charge carriers at either side of said barrier layer and the value of a potential applied across said barrier layer determining the current-voltage characteristics of the device.
BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic side view of a device in accordance with the invention, with the vertical scale greatly expanded for clarity;
Figure 2 shows the measured current voltage characteristic of the device; Figure 3 illustrates part of the true current voltage characteristic of the device; and
Figure 4 illustrates part of the conduction band for the central portion of the device, at four different applied bias voltages. DETAILED DESCRIPTION
Referring firstly to Figure 1 , the device comprises two compositional superlattices 1 , 3 separated by a 8 nanometre thick barrier layer of Alnu.•»_c_>GaΛU. (-cDΔs 5. Each superlattice 1 , 3 is constituted by ten layers of A1Q
Figure imgf000005_0001
t eac- approximately 3 nanometres thick, alternating with ten layers of GaAs 9 each approximately 6 nanometres thick. Each GaAs layer 9 within the super¬ lattices 1 , 3 is doped with silicon.at a level of 4 X 10 17cm-3 over the central 2 nanometres. Respective approximately 2 nanometre thick GaAs layers 11, 13 are formed at the end of each superlattice remote from the barrier layer 5, with respective 40 nanometre thick GaAs layers 15, 17 doped with silicon to 10 17cm-3 being formed at either side of the layers 11, 13. Further capping layers 19, 21 of GaAs doped with silicon to 10 cm" are formed on the layers 15, 17 respectively, the whole device being formed on a GaAs substrate 23 separated from the layer 21 by a very thin layer 25 of AlAs, between 0.5 to 1 nanometre thick which acts as a barrier to defect diffusion from the substrate.
The device as described is grown by molecular beam epitaxy from the substrate 23. Respective electrical contacts (not shown) are then formed to the upper capping layer 19 and by etching to the lower capping layer 21.
By applying a bias across the device via the electrical contacts, the current voltage characteristics shown in Figure 2 may be measured. The most notable features in these curves are the discontinuous voltage steps at certain currents which exhibit a hysteresis dependent on the direction of the current sweep. It is well known in the art of measurement of such semiconductor characteristic curves that self resonance due to the reactance of the device and the measuring circuit causes such measured characteristics to deviate from the true current voltage characteristic. Measurement of the derivative ^V/"dI shows that this derivative diverges as the discontinuity in voltage is approached, i.e. that the slope 'dl ^V becomes zero. This behaviour indicates that the true I-V characteristic is of the general form shown in Figure 3, this characteristic showing a region of negative differential conductivity, the value of V shown in this Figure being the potential drop across the "layer 5, most of the voltage across the device being actually dropped across this layer.
The I-V characteristics of the device are temperature independent below about 100K. Above this temperature as can be seen in plots (b) and (c) in Figure 2 the voltage steps decrease with temperature and the hysteresis loops shrink and eventually disappear leaving a smooth characteristic at room temperature which is only slightly non-ohmic. In the ohmic regions away from the voltage steps the resistances measured at each temperature are very similar. The measurements shown in Figure 2 were taken under dark conditions, but were unchanged under illumination of the device.
The characteristics of the device may be explained with reference to Figure 4 which shows the conduction band edge 29 at the centre of the device for four different values of applied bias voltage V. Refer¬ ring firstly to Figure 4 (i), as in each of the superlattices 1 , 3 the energies of the two conduction band minima for the layers 9 of A1Q -_Gan 7t_As and layers 11 of GaAs are different, the GaAs layers 11 constitute potential wells, confined by the Al„ 5 Ga 0 7*^S ^ayers 9 which each constitute thin potential barriers. As the layers 9, 11 are so thin that they are strongly coupled, the bound electron states in the wells overlap forming -minibands1 of typical widths and separations of tens of illielectron volts. The first two such minibands are shown in Figure 4, the first minibands 31 , or 32 having a width of E, and being separated from the second minibands 35, or 36 by respective energy gaps of E . The doping levels for the GaAs layers 11 within the device are chosen such that the Fermi level Ef lies near the middle of the first miniband 31 or 32 as shown, the doping being spaced away from the AlGaAs layers to minimise problems associated with deep donors. Within each superlattice 1, 3 metallic conduction occurs in the first miniband with most of the applied bias dropped across the thick tunnel barrier 37 constituted by the layer 5 separating the two super¬ lattices 1, 3- The amount of conduction through this barrier 37 will depend on the overlap in energy of the minibands at each side of the barrier as further described hereafter.
For low levels of bias, i.e. for values of V of less than E. as shown in Figure 4 (ii) electrons can tunnel from the first miniband 31 on one side of the barrier 37 to the first miniband 3 on the other side, so that the conduction appears Ohmic. Once the voltage drop across the tunnel barrier 37 exceeds the width of the first miniband 31 however as shown in Figure 4(iii) there are no states available for the electrons to tunnel into and conduction is only possible if the electrons lose energy by emitting phonons. Generally the width E, D of the first miniband 31 or 32 will be chosen to be less than the optic phonon energy for GaAs so as to prevent electrons losing energy in this manner. Thus the region of negative differential conductance indicated by the drop in current shown in Figure 3 for this applied voltage results. The current will increase again only,when as shown in Figure 4(iv) the bias is increased by an amount equal to the separation E of the first and second minibands g 31 and 35 or 32 and 36. At this point electrons may tunnel elastically through the barrier 37 from the first miniband
31 at one side of the barrier 37 to the second miniband
36 at the other side of the barrier.
The amount of negative differential conductance may be increased in several ways. Firstly the gap in energy E between the first and second minibands can be increased g by decreasing each well thickness within each superlattice
1,3 and increasing the barrier height constituted by the AlGaAs layers by increasing the aluminium content. This will reduce the current associated with thermal activation and increase the voltage range of. the negative differential re¬ sistance which is closely related to the energy E . This g will in turn increase the avilable power,efficiency and operating temperature of the device,when for example used in an oscillator. Values which can readily be realised are 5nm wide wells with 3nm barriers containing 45% aluminium.
The current density of the device can be increased by making the layer 5 constituting the thick tunnel barrier thinner. This will also increase the relative amount of direct tunnelling and so increase the peak to valley ratio of the current swing again improving available power, efficiency and increasing the operating temperature. As however most of the applied bias must be dropped across this layer, the thickness of this layer cannot be reduced too much. A thickness of twice the barriers within the super- lattices 1,3 is regarded as a good compromise. The practical upper limit on the operating frequency of the device is determined by the capacitance associated with the high field region around the thick barrier layer but the greater current density associated with thinner barrier layers allows a much smaller area device to be used for the same output power, thus giving a reduction in capacitance even for relatively thin layers. To reduce the threshold voltage for negative differential conductance ,and so increase the efficiency of the device it is necessary to reduce the series resistance of the device as much as possible. This may be achieved by reducing the number of layers within each superlattice to the minimum required to give minibands. Generally three periods of superlattice on each side of the thick barrier layer should be adequate. For the same reason doping levels should be high as possible. It will be appreciated that whilst in the device described herebefore by way of example, the charge carriers are electrons, a device in accordance with the invention in which the charge carriers are holes is equally possible. Such a device will of course operate due to the misalignment of the valence band edges of the materials constituting the device.
It will also be appreciated that whilst the device described herebefore by way of example includes two compositional superlattices in the GaAs/AlGaAs system, many other combinations of material are possible, e.g. doping superlattices, and materials in the InAs/GaSb system. Furthermore the two superlattices need not be identical.
It will also be appreciated that whilst in the device described herebefore by way of example the barrier layer coupling the two superlattices is of the same material as but thicker than the layers of material constituting potential barriers within the two super¬ lattices, it is possible for this barrier layer to be of a different material, as long as it can form respective heterojunctions with the adjacent layers of the super¬ lattices. Where the barrier layer is of a different material, it need not necessarily be thicker than the layers of material constituting the potential barriers within the two superlattices as long as it has a lower transmission coefficient for the charge carriers passing through the device than the potential barriers of the superlattices, i.e. such that a* significant part of a voltage applied across the device appears across the barrier layer.

Claims

1. A semiconductor device characterised in that it comprises two superlattices (1,3) each comprising alternating layers (7,9) of two different semiconductor materials such that there is a misalignment of energy band edges between each pair of adjacent layers with the layers (9) of one of the materials constituting potential barriers to charge carriers passing through each super¬ lattice, said superlattices being coupled to each other by a barrier layer (5) of semiconductor material forming respective heterojunctions with the adjacent layers of the superlattices (1,3), said barrier layer (5) having a lower transmission coefficient for said charge carriers than said layers (9) of said one material said super¬ lattices (1,3) defining the allowed energy levels of said charge carriers at either side of said barrier layer (5) and the value of a potential applied across said barrier layer (5) determining the current-voltage characteristics of the device.
2. A device according to Claim 1 in which said one material and the material of said carrier layer (5) is AlxGa1,-xAs and the other material in each super- lattice (1,3) is GaAs.
3. A device according to Claim 2 in which x is 0.45
4. A device according to Claim 2 in which x is 0.25
5. A device according to Claim 2 in which said layers (9) of GaAs are doped with silicon to put the Fermi level (E„) in the first miniband (31,32) for each superlattice (1,3).
6. A device according to Claim 4 in which said layers (9) of GaAs are doped in a region spaced away from the adjacent layers (7) of Al Ga, As.
7. A device according to anyone of the preceding claims in- which said barrier layer (5) is at least twice as thick as said layers (9) of said one material.
8. A device according to anyone of the preceding claims in which each of said superlattices (1,3) is of at least three periods.
9. A device according to anyone of the preceding claims in which the width (E.b) of the first miniband
(31,32) for each of said superlattices (1,3) is less than the optic phonon energy for said one material.
PCT/GB1985/000537 1985-11-19 1985-11-22 Semiconductor devices WO1987003424A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US06/799,627 US4645707A (en) 1985-11-19 1985-11-19 Semiconductor devices
PCT/GB1985/000537 WO1987003424A1 (en) 1985-11-22 1985-11-22 Semiconductor devices
JP60505180A JPS63501459A (en) 1985-11-22 1985-11-22 semiconductor equipment

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3828886A1 (en) * 1987-08-25 1989-03-16 Mitsubishi Electric Corp Device having a superlattice structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0005059A2 (en) * 1978-04-24 1979-10-31 Western Electric Company, Incorporated A semiconductor device having a layered structure and a method of making it
EP0133342A1 (en) * 1983-06-24 1985-02-20 Nec Corporation A superlattice type semiconductor structure having a high carrier density

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5990978A (en) * 1982-11-16 1984-05-25 Nec Corp Superlattice negative resistance element
JPS6039869A (en) * 1983-08-12 1985-03-01 Agency Of Ind Science & Technol Structure of semiconductor superlattice

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0005059A2 (en) * 1978-04-24 1979-10-31 Western Electric Company, Incorporated A semiconductor device having a layered structure and a method of making it
EP0133342A1 (en) * 1983-06-24 1985-02-20 Nec Corporation A superlattice type semiconductor structure having a high carrier density

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3828886A1 (en) * 1987-08-25 1989-03-16 Mitsubishi Electric Corp Device having a superlattice structure

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