WO1985001137A1 - Circuit arrangement for coupling single chip microprocessors - Google Patents

Circuit arrangement for coupling single chip microprocessors Download PDF

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Publication number
WO1985001137A1
WO1985001137A1 PCT/EP1984/000255 EP8400255W WO8501137A1 WO 1985001137 A1 WO1985001137 A1 WO 1985001137A1 EP 8400255 W EP8400255 W EP 8400255W WO 8501137 A1 WO8501137 A1 WO 8501137A1
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Prior art keywords
bus
data
line
chip microprocessors
address
Prior art date
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PCT/EP1984/000255
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German (de)
French (fr)
Inventor
Detlef Ludwig
Original Assignee
Krohne Messtechnik Gmbh & Co. Kg
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Publication of WO1985001137A1 publication Critical patent/WO1985001137A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Definitions

  • microprocessors can only be used to a limited extent for small and medium-sized control devices. They can be combined in an arrangement known from large computing systems, where each microprocessor has a special task, for example for controlling and monitoring a printer, an interface, a keyboard or the like.
  • control inputs required for the data exchange between the microprocessors according to the DMA method are, however, not present in the particularly inexpensive and compact single-chip processors.
  • they contain a program memory (ROM or EPROM), a read / write memory (RAM), a number of digital inputs / outputs (PORT) and one consisting of an arithmetic and control unit
  • DE-OS 31 37 313 discloses the coupling of two microprocessors for direct memory access with an address data bus connecting both microprocessors. However, a read-write memory and a bus adapter are required for data exchange.
  • OMP device required, which is controlled by the one, designed in the manner of a central processing unit microprocessor.
  • the invention is based on the object of “ developing a circuit arrangement which enables a particularly simple coupling of single-chip microprocessors in any number for a data transfer.
  • This object is achieved according to the invention in that all single-chip microprocessors are directly coupled to a common address data bus and a control bus, and to a time monitoring unit by a bus request line, a bus occupancy line and a reset line.
  • This switching arrangement has the essential advantage that data transfer between the single-chip microprocessors is possible via the common address data bus, the bus request and assignment being monitored and double assignment of the address data bus being prevented.
  • the control monitoring unit if there is a fault when requesting or occupying the bus, the control monitoring unit generates a reset signal which brings the single-chip microprocessors into their starting position.
  • the time monitoring unit can consist of retriggerable monoflops.
  • common data sources and sinks to the address data bus and the control bus, so that data transmission between these and the single-chip microprocessors is also possible.
  • Common data memories can also be used for the temporary storage of data that can be called up by the relevant single-chip microprocessor.
  • a circuit arrangement designed according to the invention is shown schematically in the drawing, for example.
  • Several single-chip microprocessors 1, for example with an integrated RAM, ROM and CPU unit, are coupled or connected to a common 8-bit multiplexed address data bus 2.
  • a control bus 3 consisting of three lines, one line signals the transfer of an address to a memory (ALE), while the other two lines indicate whether the single-chip microprocessor in question is recording (RD) or releasing (WR ).
  • All single-chip microprocessors 1 are further coupled to a time monitoring unit 7 by a common bus request line 4, a common bus occupancy line 5 and a common reset line 6, which can consist, for example, of retriggerable monoflops, of which one of the bus request line 4 and the bus occupancy line 5 is assigned.
  • a RAM and an interface are provided, for example, as common data sources and / or sinks coupled to the address data bus 2 and the control bus 3.
  • the data transfer between the single-chip microprocessors 1 can take place either directly or via a common data source and sink (RAM).
  • RAM common data source and sink
  • a data byte is first placed on the address data bus 2 as a static signal from the internal bus buffer memory of the single-chip microprocessor 1 which outputs the data. This signal can then be read in by the target microprocessor.
  • the address data bus output of the single-chip microprocessor 1 shows the same behavior as the ports which are also present. In this operating mode, no signals are generated on the control bus 3.
  • a prerequisite for such an immediate data transfer is that no other data transfer is carried out during the data transfer Is inserted ge S ingle-chip microprocessor 1 to the address data bus. 2
  • the corresponding control and monitoring takes place with the help of the bus request line 4 and the bus occupancy line 5, these serving here as an acknowledge line or request line.
  • the microprocessor 1 emitting the information first sends a signal into the bus occupancy line 5 and then asks the bus request line 4 whether the destination microprocessor 1 is ready for data exchange. After this has announced its willingness to accept data, the information-providing microprocessor statically places the data on the address data bus 2 and indicates this by a signal on the bus occupancy line 5.
  • the target processor 1 can now determine by querying the bus occupancy line 5 whether there is any information for it. As soon as it has read it in via the address data bus 2, it sends a signal into the bus request line 4 which indicates to the single-chip microprocessor which is providing the information that its offered data has been requested. This then releases the bus occupancy line 5, so that the address data bus 2 is again freely available for other data flows.
  • this static mode of operation can also be designed in such a way that several target microprocessors in parallel, ie. H. read in the same information simultaneously via the statically assigned address data bus 2.
  • a transfer via RAM as a buffer is advisable if larger amounts of data are to be moved or if the timing of the program does not allow immediate transfer.
  • the data from a single-chip microprocessor are written into an address area in the RAM defined for the target microprocessor or processors.
  • the target microprocessor (s) will get this data out of the RAM address areas assigned to you if necessary.
  • By storing a control value in the RAM they indicate whether further data is required or whether the reading of the data has ended.
  • blocking notes for certain address areas of the RAMS are possible, which are also stored as control words in the RAM.
  • the single-chip microprocessor 1 When transferring data to a common data source and sink, e.g. B. a RAM, the single-chip microprocessor 1 first asks whether the bus request line 4 is free. If it is free, it occupies it, otherwise it continues to ask via a waiting loop. Accordingly, the bus occupancy line 5 is then queried and occupied, as a result of which the address data bus 2 or the like for the data transfer to the RAM. free is. After the data transfer has ended, the bus occupancy line 5 is released for other data flows. In contrast, the bus request line 4 is already released as soon as the bus occupancy line 5 has been used. The data transfer from the RAM or another data source to a single-chip microprocessor 1 takes place in the same way, the direction of data flow being controlled in a known manner via the control bus 3.
  • a common data source and sink e.g. B. a RAM
  • the monoflop assigned to the bus request line 4 or the bus assignment line 5 sends a reset signal to the individual single-chip microprocessors 1 via the reset line 6.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Debugging And Monitoring (AREA)

Abstract

For the direct coupling of a plurality of single chip microprocessors (1) to a common address-data bus (2), the occupation of the address and data bus is monitored and controlled. To this effect, all the single-chip microprocessors (1) are connected by a bus request line (4), a bus busy line (5) and a reset line (6) to a time monitoring unit (7). The data transfer may be carried out between the single-chip microprocessors (1) directly or via a source and a data output coupled to the address-data bus (2).

Description

Schaltungsanordnung zur Kopplung von Sinqle-Chip- Mikroprozessoren Circuit arrangement for coupling Sinqle chip microprocessors
Mikroprozessoren sind wegen ihrer geringen Rechenleistung für kleinere und mittlere Steuerungseinrichtungen nur be¬ grenzt einsetzbar. Sie lassen sich in einer von großen Rechensystemen her bekannten Anordnung kombinieren, wo¬ bei jeder Mikroprozessor eine spezielle Aufgabe hat, bei¬ spielsweise dem Steuern und Überwachen eines Druckers, einer -Schnittstelle, einer Tastatur o. dgl. dient.Because of their low computing power, microprocessors can only be used to a limited extent for small and medium-sized control devices. They can be combined in an arrangement known from large computing systems, where each microprocessor has a special task, for example for controlling and monitoring a printer, an interface, a keyboard or the like.
Die für den Datenaustausch zwischen den Mikroprozessoren er¬ forderlichen Steuereingänge nach der DMA-Methode sind jedoch bei den besonders preiswerten und kompakten Single-Chip- Prozessoren nicht vorhanden. In der Regel beinhalten sie einen Programmspeicher (ROM cderEPROM), einen Schreib-Lese¬ speicher (RAM) , eine Anzahl von digitalen Ein-/Ausgängen (PORT) und eine aus Rechen- und Steuerwerk bestehendeThe control inputs required for the data exchange between the microprocessors according to the DMA method are, however, not present in the particularly inexpensive and compact single-chip processors. As a rule, they contain a program memory (ROM or EPROM), a read / write memory (RAM), a number of digital inputs / outputs (PORT) and one consisting of an arithmetic and control unit
Zentraleinheit (CPU). Aus der DE-OS 31 37 313 ist zwar die Kopplung von zwei Mikroprozessoren für einen direkten Spei¬ cher-Zugriff mit einem beide Mikroprozessoren verbindenden Adreß-Datenbus bekannt. Für den Datenaustausch ist jedoch ein Schreib-Lesespeicher und eine Busanpassungseinrich-Central processing unit (CPU). DE-OS 31 37 313 discloses the coupling of two microprocessors for direct memory access with an address data bus connecting both microprocessors. However, a read-write memory and a bus adapter are required for data exchange.
OMP tung erforderlich, die von dem einen, in der Art einer Zentraleinheit ausgebildeten Mikroprozessor gesteuert wird.OMP device required, which is controlled by the one, designed in the manner of a central processing unit microprocessor.
Demgegenüber liegt der Erfindung die Aufgabe zugrunde," eine Schaltungsanordnung zu entwickeln, die eine beson¬ ders einfache Kopplung von Single-Chip-Mikroprozessoren in einer beliebigen Anzahl für einen Datentransfer er¬ möglicht.In contrast, the invention is based on the object of “ developing a circuit arrangement which enables a particularly simple coupling of single-chip microprocessors in any number for a data transfer.
Diese Aufgabe wird erfindungsgemäß dadurch gelöst, daß alle Single-Chip-Mikroprozessoren unmittelbar an einen gemeinsamen Adreß-Datenbus und einen Controlbus sowie durch eine Busanforderungsleitung, eine Busbelegungs- leitung und eine Resetleitung an eine Zeitüberwachungs¬ einheit angekoppelt sind.This object is achieved according to the invention in that all single-chip microprocessors are directly coupled to a common address data bus and a control bus, and to a time monitoring unit by a bus request line, a bus occupancy line and a reset line.
Diese Schaltanordnung hat den wesentlichen Vorteil, daß zwischen den Single-Chip-Mikroprozessoren ein Datentransfe über den gemeinsamen Adreß-Datenbus möglich ist, wobei die Busanforderung und -belegung überwacht und eine Doppelbe¬ legung des Adreß-Datenbusses verhindert wird. Kommt es jedoch bei der Busanforderung oder -belegung zu einer Stö¬ rung, so erzeugt die Steuerüberwachungseinheit ein Reset- signal, welches die Single-Chip-Mikroprozessoren in ihre Ausgangsstellung bringt. Beispielsweise kann die Zeit¬ überwachungseinheit aus retriggerbaren Monoflops bestehen. Weiterhin besteht die Möglichkeit, an den Adreß-Datenbus und den Controlbus gemeinsame Datenquellen und -senken anzukoppeln, so daß auch eine Datenübertragung zwischen diesen und den Single-Chip-Mikroprozessoren möglich ist. Gemeinsame Datenspeicher können auch der Zwischenspeiche- rung von Daten dienen, die von dem betreffenden Single- Chip-Mikroprozessor abgerufen werden können.This switching arrangement has the essential advantage that data transfer between the single-chip microprocessors is possible via the common address data bus, the bus request and assignment being monitored and double assignment of the address data bus being prevented. However, if there is a fault when requesting or occupying the bus, the control monitoring unit generates a reset signal which brings the single-chip microprocessors into their starting position. For example, the time monitoring unit can consist of retriggerable monoflops. Furthermore, it is possible to couple common data sources and sinks to the address data bus and the control bus, so that data transmission between these and the single-chip microprocessors is also possible. Common data memories can also be used for the temporary storage of data that can be called up by the relevant single-chip microprocessor.
Eine erfindungsgemäß ausgebildete Schaltungsanordnung ist beispielsweise in der Zeichnung schematisch dargestellt. Mehrere Single-Chip-Mikroprozessoren 1, beispielsweise mit integrierter RAM-, ROM- und CPU-Einheit, sind an einen gemeinsamen 8 Bit gemultiplexten Adreß-Datenbus 2 angekoppelt bzw. angeschlossen. Bei einem aus drei Lei- tungen bestehenden Controlbus 3 dient eine Leitung der Signalisierung der Übernahme einer Adresse in einen Speicher (ALE), während die beiden anderen Leitungen anzeigen, ob der betreffende Single-Chip-Mikroprozessor Daten aufnimmt (RD) oder abgibt (WR).A circuit arrangement designed according to the invention is shown schematically in the drawing, for example. Several single-chip microprocessors 1, for example with an integrated RAM, ROM and CPU unit, are coupled or connected to a common 8-bit multiplexed address data bus 2. In the case of a control bus 3 consisting of three lines, one line signals the transfer of an address to a memory (ALE), while the other two lines indicate whether the single-chip microprocessor in question is recording (RD) or releasing (WR ).
Alle Single-Chip-Mikroprozessoren 1 sind weiterhin durch eine gemeinsame Busanforderungsleitung 4, eine gemeinsame Busbelegungsleitung 5 und eine gemeinsame Resetleitung 6 an eine Zeitüberwachungseinheit 7 angekoppelt, die bei- spielsweise aus retriggerbaren Monoflops bestehen kann, von denen jeweils einer der Busanforderungsleitung 4 und der Busbelegungsleitung 5 zugeordnet ist. Als an den Adreß-Datenbus 2 und den Controlbus 3 angekoppelte ge¬ meinsame Datenquellen und/oder -senken sind beispiels- weise ein RAM und eine Schnittstelle vorgesehen.All single-chip microprocessors 1 are further coupled to a time monitoring unit 7 by a common bus request line 4, a common bus occupancy line 5 and a common reset line 6, which can consist, for example, of retriggerable monoflops, of which one of the bus request line 4 and the bus occupancy line 5 is assigned. A RAM and an interface are provided, for example, as common data sources and / or sinks coupled to the address data bus 2 and the control bus 3.
Der Datentransfer zwischen den Single-Chip-Mikroprozesso¬ ren 1 kann entweder unmittelbar oder über eine gemeinsame Datenquelle und -senke (RAM) stattfinden.The data transfer between the single-chip microprocessors 1 can take place either directly or via a common data source and sink (RAM).
Bei einem unmittelbaren Datentransfer wird zunächst ein Datenbyte vom internen Bus-Puffer-Speicher des die Daten abgebenden Single-Chip-Mikroprozessors 1 als statisches Signal auf den Adreß-Datenbus 2 gelegt. Dieses Signal kann dann von dem Ziel-Mikroprozessor eingelesen werden.In the case of an immediate data transfer, a data byte is first placed on the address data bus 2 as a static signal from the internal bus buffer memory of the single-chip microprocessor 1 which outputs the data. This signal can then be read in by the target microprocessor.
Der Adreß-Datenbus-Ausgang des Single-Chip-Mikroprozessors 1 zeigt dabei das gleiche Verhalten wie die ebenfalls vor¬ handenen Ports. Auf dem Controlbus 3 werden bei dieser Betriebsweise keine Signale erzeugt.The address data bus output of the single-chip microprocessor 1 shows the same behavior as the ports which are also present. In this operating mode, no signals are generated on the control bus 3.
Voraussetzung für einen solchen unmittelbaren Datentrans¬ fer ist, daß während des Datentransfers kein anderer Single-Chip-Mikroprozessor 1 an den Adreß-Datenbus 2 ge¬ legt wird. Die entsprechende Steuerung und Überwachung geschieht mit Hilfe der Busanforderungsleitung 4 und der Busbelegungsleitung 5, wobei diese hier als Acknowledge- Leitung bzw. Request-Leitung dienen.A prerequisite for such an immediate data transfer is that no other data transfer is carried out during the data transfer Is inserted ge S ingle-chip microprocessor 1 to the address data bus. 2 The corresponding control and monitoring takes place with the help of the bus request line 4 and the bus occupancy line 5, these serving here as an acknowledge line or request line.
Der die Information abgebende Mikroprozessor 1 gibt zu¬ nächst ein Signal in die Busbelegungsleitung 5 und fragt danach die Busa forderungsleitung 4 ab, ob der Ziel ikro- prozessor 1 zum Datenaustausch bereit ist. Nachdem dieser seine Bereitschaft zur Datenaufnahme bekanntgegeben hat, legt der informationsabgebende Mikroprozessor die Daten statisch auf den Adreß-Datenbus 2 und zeigt dies durch ein Signal auf der Busbelegungsleitung 5 an. Der Ziel- prozessor 1 kann nunmehr durch Abfrage der Busbelegungs¬ leitung 5 feststellen, ob für ihn eine Information vor¬ handen ist. Sobald er sie über den Adreß-Datenbus 2 ein¬ gelesen hat, gibt er in die Busanforderungsleitung 4 ein Signal, das dem die Information gebenden Single-Chip- Mikroprozessor anzeigt, daß seine angebotenen Daten ab¬ gefragt sind. Dieser gibt dann die Busbelegungsleitung 5 frei, so daß der Adreß-Datenbus 2 für andere Datenflüsse wieder frei zur Verfügung steht.The microprocessor 1 emitting the information first sends a signal into the bus occupancy line 5 and then asks the bus request line 4 whether the destination microprocessor 1 is ready for data exchange. After this has announced its willingness to accept data, the information-providing microprocessor statically places the data on the address data bus 2 and indicates this by a signal on the bus occupancy line 5. The target processor 1 can now determine by querying the bus occupancy line 5 whether there is any information for it. As soon as it has read it in via the address data bus 2, it sends a signal into the bus request line 4 which indicates to the single-chip microprocessor which is providing the information that its offered data has been requested. This then releases the bus occupancy line 5, so that the address data bus 2 is again freely available for other data flows.
Mit Hilfe der Busbelegungsleitung 5 und der Busanforderungs¬ leitung 4 läßt sich auch überprüfen, ob der eine Mikroprozes sor alle angebotenen Daten eingelesen und der andere Mikro¬ prozessor alle verlangten Daten übergeben hat. Diese sta¬ tische Betriebsweise kann mit einem geeigneten Programm auch so ausgebildet sein, daß mehrere Zielmikroprozessoren parallel, d. h. gleichzeitig über den statisch belegten Adreß-Datenbus 2 die gleiche Information einlesen.With the help of the bus occupancy line 5 and the bus request line 4, it can also be checked whether the one microprocessor has read in all the data offered and the other microprocessor has transferred all the requested data. With a suitable program, this static mode of operation can also be designed in such a way that several target microprocessors in parallel, ie. H. read in the same information simultaneously via the statically assigned address data bus 2.
Ein Transfer über ein RAM als Zwischenspeicher hingegen ist zweckmäßig, wenn größere Datenmengen bewegt werden sollen oder der zeitliche Ablauf des Programms keine unmittelbare Übertragung zuläßt. Bei der mittelbaren Übertragung werden die Daten von einem Single-Chip-Mikroprozessor in einen für den oder die Zielmikroprozessoren festgelegten Adreß- bereich im RAM eingeschrieben. Der oder die Zielmikroprozes soren holen dich diese Daten bei Bedarf aus den ihnen zu- geordneten Adreßbereichen des RAM wieder heraus. Durch Einspeichern eines Kontrollwertes im RAM geben sie be¬ kannt, ob weitere Daten benötigt werden, oder ob das Lese der Daten beendet ist. Ferner sind Sperrvermerke für be¬ stimmte Adreßbereiche des RAMS möglich, die ebenfalls als Kontrollwörter im RAM abgespeichert sind.A transfer via RAM as a buffer, on the other hand, is advisable if larger amounts of data are to be moved or if the timing of the program does not allow immediate transfer. In the case of indirect transmission the data from a single-chip microprocessor are written into an address area in the RAM defined for the target microprocessor or processors. The target microprocessor (s) will get this data out of the RAM address areas assigned to you if necessary. By storing a control value in the RAM, they indicate whether further data is required or whether the reading of the data has ended. Furthermore, blocking notes for certain address areas of the RAMS are possible, which are also stored as control words in the RAM.
Bei einem Datentransfer zu einer gemeinsamen Datenquelle und -senke, z. B. ein RAM, fragt der Single-Chip-Mikro¬ prozessor 1 zunächst an, ob die Busanforderungsleitung 4 frei ist. Ist sie frei, belegt er sie, andernfalls fragt er über eine Warteschleife weiter an. Entsprechend wird danach die Busbelegungsleitung 5 abgefragt und belegt, wodurch der Adreß-Datenbus 2 für den Datentransfer zum RAM o.dgl. frei ist. Nachdem der Datentransfer beendet ist, wird die Busbelegungsleitung 5 für andere Datenflüsse freigegeben. Die Busanforderungsleitung 4 hingegen wird bereits freigegeben, sobald die Busbelegungsleitung 5 in Anspruch genommen worden ist. Der Datentransfer von dem RAM oder einer anderen Datenquelle zu einem Single-Chip- Mikroprozessor 1 geschieht in der gleichen Weise, wobei die Datenflußrichtung in bekannter Weise über den Control¬ bus 3 gesteuert wird.When transferring data to a common data source and sink, e.g. B. a RAM, the single-chip microprocessor 1 first asks whether the bus request line 4 is free. If it is free, it occupies it, otherwise it continues to ask via a waiting loop. Accordingly, the bus occupancy line 5 is then queried and occupied, as a result of which the address data bus 2 or the like for the data transfer to the RAM. free is. After the data transfer has ended, the bus occupancy line 5 is released for other data flows. In contrast, the bus request line 4 is already released as soon as the bus occupancy line 5 has been used. The data transfer from the RAM or another data source to a single-chip microprocessor 1 takes place in the same way, the direction of data flow being controlled in a known manner via the control bus 3.
Kommt es bei einer Busanforderung oder .Busbelegung zu Störungen, so gibt das der Busanforderungsleitung 4 bzw. der Busbelegungsleitung 5 zugeordnete Monoflop über die Resetleitung 6 ein Resetsignal an die einzelnen Single- Chip-Mikroprozessoren 1.If faults occur during a bus request or bus assignment, the monoflop assigned to the bus request line 4 or the bus assignment line 5 sends a reset signal to the individual single-chip microprocessors 1 via the reset line 6.
f OM f OM

Claims

Patentansprüche Claims
1. Schaltungsanordnung zur Kopplung von Single-Chip- Mikroprozessoren an einen Adreß-Datenbus, dadurch gekennzeichnet, daß alle Single-Chip-Mikroprozesso¬ ren (1) unmittelbar an einen gemeinsamen Adreß- Datenbus (2) und einen Controlbus (3) sowie durch eine Busanforderungsleitung (4), eine Busbelegungs¬ leitung (5) und eine Resetleitung (6) an eine Zeit¬ überwachungseinheit (7) angekoppelt sind.1. Circuit arrangement for coupling single-chip microprocessors to an address data bus, characterized in that all single-chip microprocessors (1) directly to a common address data bus (2) and a control bus (3) and by a bus request line (4), a bus occupancy line (5) and a reset line (6) are coupled to a time monitoring unit (7).
2. Schaltungsanordnung nach Anspruch 1, dadurch ge¬ kennzeichnet, daß die Zeitüberwachungseinheit (7) aus retriggerbaren Monoflops besteht.2. Circuit arrangement according to claim 1, characterized ge indicates that the time monitoring unit (7) consists of retriggerable monoflops.
3. Schaltungsanordnung nach Anspruch 1 oder 2 , dadurch gekennzeichnet, daß an den Adreß-Datenbus (2) und den Controlbus (3) gemeinsame Datenquellen und -senken angekoppelt sind.3. Circuit arrangement according to claim 1 or 2, characterized in that common data sources and sinks are coupled to the address data bus (2) and the control bus (3).
O PI O PI
PCT/EP1984/000255 1983-08-19 1984-08-20 Circuit arrangement for coupling single chip microprocessors WO1985001137A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0207051A2 (en) * 1985-05-09 1986-12-30 VOEST-ALPINE AUTOMOTIVE Gesellschaft m.b.H. Microcomputer system

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3516405A1 (en) * 1985-05-07 1986-11-20 Joachim Dipl.-Ing. 8000 München Oberzier Method and bus system for exchanging information between a computer and peripheral devices
JPH0823834B2 (en) * 1990-09-13 1996-03-06 三菱電機株式会社 Microcomputer
CN115454918B (en) * 2022-11-11 2023-02-03 成都航天通信设备有限责任公司 CX9261 chip configuration method based on FPGA

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3137313A1 (en) * 1981-09-16 1983-03-31 Siemens AG, 1000 Berlin und 8000 München Circuit arrangement for coupling two microprocessors

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3137313A1 (en) * 1981-09-16 1983-03-31 Siemens AG, 1000 Berlin und 8000 München Circuit arrangement for coupling two microprocessors

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Elektronik, Vol. 30, No. 1, 1981 Munchen (DE) BUDENBENDER: "Bussystem Wird Dezentral Gesteuert", pages 81 to 85, see page 83, left-hand column, line 52 to right-hand column, line 12; figures 2,3 *
Systems Computers Controls, Vol. 9, No. 6, 1978, Silver Spring (US) NORIYUKI KAMIBAYASHI et al.: "The Distributed Bus Control Scheme and Intelligent Interface for a Minicomputer Complex System, KOCOS", pages 35 to 43, see page 37, left-hand column, line 20 to page 38, left-hand column, line 37; figure 3 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0207051A2 (en) * 1985-05-09 1986-12-30 VOEST-ALPINE AUTOMOTIVE Gesellschaft m.b.H. Microcomputer system
EP0207051A3 (en) * 1985-05-09 1988-09-28 Voest-Alpine Automotive Gesellschaft Mbh Microcomputer system

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DE3329956C2 (en) 1985-06-20
EP0154649A1 (en) 1985-09-18
JPS60502073A (en) 1985-11-28
DE3329956A1 (en) 1985-03-07

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