WO1985000077A2

WO1985000077A2 - Self-aligned gate mesfet and the method of fabricating same

Info

Publication number: WO1985000077A2
Application number: PCT/US1984/000759
Authority: WO
Inventors: Robert E Lee; Harold M Levy
Original assignee: Hughes Aircraft Co
Priority date: 1983-06-17
Filing date: 1984-05-18
Publication date: 1985-01-03
Also published as: WO1985000077A3; IT1205592B; JPS60501635A; EP0146625A1; IT8448403A0

Abstract

An improved performance MESFET device incorporating a structure fabricated utilizing self-aligned gate process technology. The edges of the gate electrode (28) formed are separated from the edges (23, 25) of the dopant regions (26, 27) implanted in the device substrate (23) by a distance which optimizes device performance. In order to increase process yield, a layer of dielectric material (29) is deposited on the substrate surface and then annealed to protect the gate electrode and both stabilize and planarize the substrate surface.

Description

SELF-ALIGNED GATE MESFET AND
THE METHOD OF FABRICATING SAME
The Government has rights in this invention pursuant to Contract No. F33615-81-C-1427 awarded by the Department of the Air Force.

BACKGROUND OF THE INVENTION 1. Field of the Invention
The invention relates to an improved method for fabricating metal semiconductor field effect transistor (MESFET) devices, and, in particular, a method for fabricating a self-aligned gate MESFET wherein the separation between the gate electrode and the dopant self-aligned contact is controlled to optimize the parasitic source resistance to gate capacitance ratio thus improving device performance.

2. Description of the Prior Art
Factors which have limited the performance and yields obtainable in conventional FET processing techniques are the need to perform either (1) a precise recess etch to reduce the FET pinch-off voltage, or (2) a critical realignment of the gate electrode to an existing active channel region to reduce source resistance. A prior art technique solution to these problems is disclosed in the articles "A Self-Aligned
Source/Drain Planar Device for Ultrahigh-Speed GaAs
MESFET VLSIs" by N.

Yokoyama, et al., ISSCC Digest of
Technical Papers, pp. 218-219 (February 1981), and "Ti/W Silicide Gate Technology for Self-Aligned-GaAs
MESFET VLSI's" by Yokoyama, et al., International
Electron Device Meeting Proceeding, pp. 80 (1931). In particular, a fabrication process is described wherein an active channel layer is formed on a semi-insulating substrate and a refractory metal gate is used as a selfaligned mask for an implant which established the n+ contact regions. In this instance, the MESFET Pinch off voltage is controlled by the channel implant (no recess etch is required) and the source parasitic resistance is reduced by the self-aligned n+ contact implant.

A critical factor in using self-aligned gate techniques is the proximity of the n regions to the gate. A tradeoff exists between parasitic source-gate resistance and parasitic gate capacitance as the proximity of the ne contact close to the gate lowers the parasitic resistance (as discussed in Yokoyama et al. articles) but raises the gate capacitance and vice versa. Further, the position of the nf regions with respect to the gate also influences the breakdown voltage of the gate contact to semiconductor Schottky barrier.

The process described in the Yokoyama et al.

references approaches the tradeoff problem by varying the depth of the buried n+ implant relative to the channel implant. A problem with this approach is the relatively high resistivity layer between the ohmic contact and the peak of the n+ implant, a problem inherent in the use of a buried implant where a current path to the surface must exist. This reduces device switching speeds, increases power requirements in digital circuits and increases the noise factor while lowering the frequency response when the device is utilized in analog circuits.

SUMMARY OF THE INVENTION
The present invention provides an improved selfaligned gate process for fabricating metal semiconductor field effect transistors MESFETS and integrated circuits.

In particular, an active channel layer is formed on a semi-insulating semiconductor substrate, preferably
GaAs, and a refractory metal layer is deposited on the substrate surface. The gate electrode is fabricated by forming a mask of a predetermined width over the metal layer, the mask comprising a selectively non-etchable material. An undercut etch method is utilized to make the final gate width smaller than the width of the gate mask, the gate mask thereafter being utilized as the mask for the implantation of the dopant into the substrate. The gate mask is then removed and a dielectric layer is deposited over the surface of the substrate and then annealed, thus protecting and planarizing the substrate surface and increasing process yields.

Ohmic contacts are formed by etching openings in the insulating layer to allow contact to the n+ implant and device fabrication is completed by both the deposit of a second dielectric layer over the protection dielectric layer and the formation of a metal on the second dielectric layer.

The MESFET devices produced by the process of the present invention provides many advantages over the prior art. The gate formed by the undercut etch allows the spacing between the self-aligned contact and the gate electrode to be selected such that the ratio of parasitic resistance to gate capacitance is optimized thus increasing switching speeds, increasing breakdown voltages and lowering device power consumption in digital circuits while also lowering noise and increasing frequency response when the device is utilized in analog circuits. The resultant physical gate electrode is shorter than those produced by standard liftoff methods thus allowing the size (and capacitance) of the device to be correspondingly reduced.

The deposition of the dielectric layer on the substrate surface and the annealing thereof after the dopant implant increases process yields, thus reducing manufacturing costs, by protecting the gate metal electrode and the substrate surface from damage, while also stabilizing the semiconductor surface. The dielectric layer, in addition, planarizes the substrate surface so that subsequent process steps can be accomplished on substantially flat surfaces, increasing the accuracy, repeatability and yields of MESFET fabrication.

The MESFET devices produced by the fabrication process of the present invention have the necessary operating characteristics to be used in the manufacture of high speed digital circuits and in the manufacture of lower noise, higher frequency analog type devices used, such circuits and devices being used, for example, in computer, communication, missile and radar systems.

BRIEF DESCRIPTION OF THE DRAWING
For a better understanding of the invention as well as other advantages and further features thereof, reference is made to the following description which is to be read in conjunction with the accompanying drawing wherein the same reference numerals, it should be noted, identify identical components in each of the figures, and wherein:
FIG. 1 is a cross-sectional view of a GaAs MESFET fabricated in accordance with a prior art self-aligned gate process;
FIG. 2 is a cross-sectional view of on & embodiment of a GaAs MESFET fabricated in accordance with the improved self-aligned gate process of the present invention; and
FIG. 3-7 are cross-sectional views which illustrate the method of fabricating the MESFET of FIG. 2.

DETAILED DESCRIPTION OF THE INVENTION
It should be noted that although the detailed description that follows is related to a GaAs FET structure, specifically GaAs MESFET structures, it will be understood that the invention is suitable for other III-Vmaterials, such as indium phosphide (inn) used in similar applications and that the techniques described can be applied to other FET structures such as MOSFET structures when insulating layers can be achieved.

In order to put the present invention in perspective, a conventional prior art GaAs MESFET structure will first be described. FIG. 1 depicts such a prior art structure, as described in the above-mentioned #okoyama articles, the structure comprising a semiinsulating substrate 10, such as GaAs, typically having a resistivity of about 107 ohm-cm. Substrate 10 has an active layer of material 12 supported thereon, layer 12 being an active semiconductor region having an
N-type dopant. Layer 12 provides an active region for conduction and control of carriers. Electrodes 14 and 16 are in direct contact with layer 12 and, in FET devices, serve as source and drain electrodes, respectively. Gate electrode 18, having a width W of 1.5 iim, contacts a portion of layer 12 and is spaced apart from electrodes 14 and 16.

During the fabrication process, a titanium/tungsten (Ti/W) or tungsten silicide (W/Si) mixture is deposited by dc sputtering and etching is performed with a Freon and oxygen (C74+O2) gas plasma. The n+ layers 19 are made by self-aligned Si+ implantation using gate 18 as the implantation mask. Fabrication is completed by ohmic metalization with AuGe-Au in accordance with standard techniques. The edges 17 of the n+ regions 19 formed by the above described process are, it is observed, aligned with the edges 21 of gate electrode 18. The disadvantages of this alignment feature is that the relative closeness of the edges 21 relative to regions 19 reduces device performance due to the parasitic capacitance factors inherent with device utilization, and decreases the reverse breakdown of the gate.

In accordance with the present invention, an improved self-aligned gate FET structure is provided.

A MESFET device 20 incorporating the structure is shown in FIG. 2. It should be noted that although the device shown in FIG. 2 and fabricated in accordance with the steps shown in FIGS. 3-7 describe an enhancement mode (ENFET) type device, other type devices, including a depletion mode (DPET) device, can be fabricated utilizing the techniques of the present invention.

Device 20 comprises a GaAs substrate 22 having source and drain regions 26 and 27. An active channel 24 is formed at the upper surface of GaAs substrate 22 and a gate electrode 28 of width W2 is in contact with the surface of substrate 22. A silicon nitride layer 29 overlies the surface of substrate 22 and conductive ohmic metal contacts 30 and 32 make contact to source and drain regions 26 and 27, respectively, through holes etched in dielectric layer 29. The edges 23 and 25 of n+ regions 26 and 27, respectively, it can be seen, are not aligned with the edges of gate 28. In particular, the width of gate 28 is such that it is less than the separation between edges 23 and 25 of n+ regions 26 and 27, respectively.

For comparison purposes, the aformentioned separation between edges 23 and 25 is about 0.4 pm, the typical width W2 of gate electrodes 28 being on the order of 0.85 um. The advantages of having a separation between the gate electrode edges and n+ region edges 23 and 25 have been set forth previously, and will be described in more detail hereinafter. The MESFET 20 is completed by depositing an interconnection crossover dielectric layer 36, typically silicon oxynitride, on layer 29 and then etching holes into dielectric layer 36 to allow a top metal (typically chromium, platinum and gold) to form a second level of metal interconnect 38.

Refe#rring now to FIG. 3, in order to fabricate
MESFET 20 by the present invention, one starts with a substrate or body 22 of semi-insulating GaAs. It is noted that other materials can be used for substrate 22, including other III-V materials, such as InP, and mixed III-V semiconductor material such as undoped Alx Gal,xAs (gallium aluminum arsenide'). An active layer or channel 24 is formed on the surface of substrate 22 by introducing a layer of n type dopants by ion implantation techniques. In the preferred embodiment, silicon ions are implanted at an energy of about 100
KeV to a dosage in the range from about 1x1012 ions/cm2 to about 4x1012 ions/cm2.

The thickness of the active layer typically is in the range from about 500A to about 2000 . Other processes which can be used to form the active channel 24 include liquid phase epitaxy, vapor phase epitaxy metal-organic chemical vapor deposition of and molecular beam epitaxy. Ion implantation techniques are preferred for the- remaining process steps. Other n-type dopants which could be utilized to form active channel 24 include, for example, selenium sulphur or tellerium, implanted at energies and dosages which depend on the substrate material and quality and the type of MESFET device to be fabricated.

A layer of refractory metal gate material 26 is deposited on the surface of substrate 22 by rf or dc sputter deposition techniques. Layer 26, having a thickness in the range from about 1000ski to about 5000A, preferably comprises a titanium/tungsten alloy. Compositions of 30% titanium and 70% tungsten by weight have been sucessfully utilized. Other materials which can be utilized as the gate layer include, for example, tungsten, tantalum, titaniumtungsten silicide, tungsten silicide tantalum silicide, or molybdenum silicide.

Referring now to FIG. 4, a photoresist layer 40 is next applied to the surface of layer 26. The photoresist layer 40 is defined using conventional photolithography processes and developed to provide a mask which exposes area 42 of metal film 26 which, as will be set forth hereinafter, defines the edges of the implanted dopant of the MESFET device being fabricated.

A layer of etch resistant metal 44, such as nickel or aluminum, is formed over photoresist 40 and area 42 by evaporation deposition techniques. The process is carried out for a time sufficient to grow the layer 44 to a thickness in the range from about 1000 to about 2QOO .

Then, the photoresist layer 40 is dissolved using conventional techniques, a layer 46 of etch resistant metal having a width corresponding to the area 42 remaining as shown in FIG. 5.

Referring now to FIG. 6, the substrate 22 is placed in a plasma reactor with Freon and oxygen (CF4+02) in order to etch the unmasked portions of layer 26. It should be noted that although a plasma etch is preferred, wet chemical or vapor etching can also be utilized.

The etch rate can be controlled in a manner to encourage undercut etching, i.e., etching beneath the unmasked layer 26. Further, the etching process is such that the mask layer 46 is slightly undercut symmetrically in stages at a substantially uniform rate. It has been found that a value of the undercut, S, in the range from about 500A to about 2500A provides the optimum performance results for MESFET 20, a value of S in the range from 1000t to about 2000A having been determined to provide the best performance results.

After the etching process, the width of gate electrode 28 for an undercut of 2000liy ( 4000A total) is approximately 0.85 pm.

Mask undercutting can be controlled by ascertaining the etch rate time for the non-mask area of layer 26 and then using that rate to control the undercut rate.

This can be accomplished directly by process operator or automatically.

For the plurality of MESFET's being fabricated on a wafer, only one value of S need be selected to optimize the performance for that type of MESFET although S can have a standard deviation in the range from about 4noR to about 500 . If S is selected to be 2000A, for example, the deviation in S from MESFET to MESFET will not be sufficient to reduce the overall performance improvement in each MESFET fabricated.

Then substrate 22 is flood exposed to silicon ions (represented by the arrows 47) in order to form the heavily doped regions (n+ in the example illustrated) 27' and 27 corresponding to the source and drain regions, respectively. The silicon donor impurities are introduced by ion implantation of silicon ions at an energy of about 125KeV to a dosage of about 2x1013 ions/cm2.

The remaining metal layer 46 is then removed by an appropriate chemical selective solvent. Regions 27' and 27 have a thickness in the range from about 500t to about 3000ss.

Referring now to FIG. 7, substrate 22 is placed into a plasma enhanced vapor deposition reactor and a silicon nitride (Si3N4) protective layer 29 is deposited over the surface of substrate 22. Other known deposition reactions, such as the thermal reaction of silane (SiH4) and ammonia (NH3) may be employed. The process is carried out for a time sufficent to form the layer 29 to a thickness in the range from about 1000{ to about 2000#. The substrate is then annealed at approximately 8000F for approximately 10 minutes. The annealing step minimizes the damage caused to the substrate crystal structure after ion implantation (n+ in the example described) at high energy levels.

Other dielectrics which can be utilized include SiO2 and A1203.

Then, an anisotropic plasma etch, using either
C2F6, C3Fg or CHF3, removes portions of the Si3N4, and forms holes to provide for ohmic contact definition.

The holes are filled with ohmic contact material 30 and 32, typically a composition of gold and germanium, to allow for connection to the underlying source and drain semiconductor regions. The substrate is then heated to 3600F in order to improve the contact between material 30 and 32 and the adjacent n+ regions 27.

The surface 33 of layer 39 is substantially planar except for the relatively small "bump" area adjacent to electrode 28. A hole is etched (not shown) in layer 29 to enable a metal connect to gate electrode 28.

Although not shown in the figure since it is not part of the MESFET device 20 finally fabricated, each device on the wafer is isolated from the adjacent device to prevent electron leakage. In particular, a photoresist layer is deposited on the dielectric layer 20 to mask the conducting regions and boron ions are implanted around the sides of each device at an energy of about 80 KeV to a dosage of about lox1013 ions/cm2. After the implant, the photoresist mask is chemically removed.

Finally, using conventional procedures, a second dielectric layer 36 (FIG. 2) may be deposited over layer 29 to allow for crossover connections and metal layer 38, typically chromium, platinum, and gold, is deposited over layer 36, the metal layer 38 being defined and etched using conventional photolithographic processes, well known in the art, to complete the device 20 shown in FIG. 2.

EXAMPLE
Devices substantially depicted in FIG. 2 have been fabricated in accordance with the process steps described hereinabove with reference to FIGS. 3-7.

Typical devices have an active region (n-type) doped with Si to 1012 ions/cm2. The thickness of the active region varied from 500A to about 2000#, the dopant regions varied in thickness from about 500A to about 3000#, the undercut value S for the electrode gate varied from about 1000A to about 2000A, and the silicon nitride protective layer varied in thickness from about 1000t to about 2000#.

The measured electrical properties of two ENFET devices fabricated in accordance with the teachings of the present invention were as follows (both devices 28 um wide, threshold voltage 0.2 volts): For a 1.1 vm gate width, the drain-source current IDS = 17.8 ma/mm; the transconductance, gm = 90 mS/mm; gate voltage
VG = 0.6 volts; drain-source voltage VDS = 1 volt. For a 0.8 um gate width, IDS = 26.8 ma/mm; gm = 140 mS/mm at
VG = 0.6 volts and VDS = 1 volt.

The self-aligned gate process described hereinabove thus provides significant advantages over prior art
MESFET processes by increasing both device performance and process yields. Performance is significantly increased by providing a technique for optimizing the parasitic source resistance and parasitic gate capacitance ratio which normally limits device performance.

The measure of the speed capability of MESFETs, ft, is given by a gm/2sCg wherein gm = g, gm and gm
l+R5g# being the terminal and intrinsic transconductance respectively, Rs is the parasitic source resistance and Cg the total gate capacitance. Optimization is possible because as S is increased from zero, Cg decreases more rapidly than Rs increases, thus establishing that there is an optimum separation S (wider separations produce increased gate breakdown thus allowing higher gate voltages).

Thus, by controlling the separation between the edges of the dopant implant and the edges of the gate electrode in accordance with the teachings of the present invention, MESFET performance is enhanced without significantly increasing the cost of device fabrication. Comparing the switching speed of devices formed in accordance with the teaching of the present invention to devices performing the same function and fabricated with prior art techniques,

an ENFET ringoscillator fabricated in accordance with the invention provided a 25 psec gate delay (for a gate width 0.85 vm) as compared to the 50 psec delay of an oscillator fabricated by the prior art process described hereinabove (gate width 1.1 vim). The power dissipation was also significantly reduced from 6.5 mw/gate (at VD = 5 volts) to 3.3 mw/gate (at VD = 2.6 volts). Additional advantages in utilizing the process of the present invention is that the gate electrode width will always be smaller than the gate mask width, thus enabling device size to be further reduced from that available in the prior art.

The dielectric layer enables process yields to increase by stabilizing and passivating the substrate surface (prevents the arsenic component of the substrate from escaping during the annealing step following dopant implantation and also protects the substrate surface from exposure to the environment); protecting the gate electrode; and planarizing the substrate surface to allow subsequent processing steps to be accurately accomplished.

While the invention has been described with reference to its preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the true nature and scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its essential teachings.

Claims

What is Claimed is: 1. A structure for use in a self-aligned gate MESFET device comprising: (a) a substrate of semi-insulating III-V semiconductor material; (b) an active channel layer of Ill-V semiconductor material on at least a portion of the surface of said substrate; (c) first and second regions of said substrate implanted with a dopant;

and (d) a gate electrode contacting at least a portion of said active channel layer and positioned on said substrate surface between said first and second substrate implant regions, the edges of said gate electrode being separated from the edge of each dopant region by a distance S such that the width of said gate electrode is less than the separation between the edges of said first and second dopant regions, the distance S being selected such that the ratio of the parasitic resistance and capacitance between the gate electrode and the first and second dopant regions is optimized.

2. The structure of Claim 1 further including a layer of dielectric material formed on the surface of said substrate and overlying said gate electrode and said first and second dopant regions.

3. The structure of Claim 2 further including first and second ohmic contacts formed in said dielectric which contact said first and second dopant regions, respectively.

4. The structure of Claim 1 wherein saiO-semi- insulating substrate comprises GaAs.

5. The structure of Claim 4 wherein said dopant regions comprise silicon ions.

6. The structure of Claim 2 wherein said dielectric flayer comprises silicon nitride.

7. The structure of Claim 1 wherein said gate electrode comprises a refractory metal.

8. The structure of Claim 7 wherein said spacing S is in the range form about 500t to about 2000#.

9. The structure of Claim 1 wherein said spacing S is in the range from about 500 to about 2000 .

10. The structure of Claim I wherein the thickness of said active channel layer is in the range from about 500 to about 2000A.

11. The structure of Claim 2 wherein the thickness of said dielectric layer is in the range from about 1000 to about 2000t.

12. The structure of Claim 1 wherein the thickness of said gate electrode is in the range from about 2000A to about 5000t.

13. A method for fabricating a structure for use in a MESFET device comprising the steps of: (a) providing a substrate of semi-insulating 111-V material; (b) forming a channel implant layer on at least a portion of said substrate; (c) forming a layer of etchable gate-material on the surface of said substrate; (d) forming an etchable gate mask of width W1 on said gate material layer; (e) exposing said substrate to an etchant whereby the gate material layer not underlying said gate mask is removed and wherein a portion of the gate material underlying said gate mask is removed, a gate electrode having a width W2 thus being formed, W2 being less than W1:

: (f) implanting a dopant into said substrate into first and second regions not masked by said gate mask, the gate electrode edges being separated from the edges of said first and second regions by a distance S; and (g) removing the gate mask after the dopant implantation of said first and second regions, the distance S being selected such that the ratio of parasitic resistance and capacitance between the gate electrode and the first and second dopant regions is optimized.

14. The method of Claim 13 further including the step of forming a dielectric layer on the surface of said substrate, said dielectric layer overlying said gate electrode and said first and second dopant regions.

15. The method of Claim 14 further including the step of forming first and second ohmic contacts in said dielectric layer for contacting said first and second dopant regions, respectively.

16. The method of Claim 13 wherein said semi insulating substrate comprises GaAs.

17. The method of Claim 16 wherein said dopant regions comprise silicon ions.

18. The method of Claim 14 wherein said dielectric layer comprises silicon nitride.

19. The method of Claim 13 wherein said gate electrode comprises a refractory metal.

20. The method of Claim 19 wherein said gate electrode comprises a composition of tungsten and titanium.

21. The method of Claim 13 wherein said spacing S is in the range from about 500t to about 2000ss.

22. The method of Claim 13 wherein the thickness of said active channel layer is in the range from about 500# to about 2000 .

23. The method of Claim 14 wherein the thickness of said dielectric layer is in the range from about 1000# to about 2000 .

24. The method of Claim 13 wherein the thickness of said gate electrode is in the range from about 200081 to about 5000t.

25. The method of Claim 13 wherein said etchant is Cm4+02 plasma.