WO1984004437A1

WO1984004437A1 - Digital communications system

Info

Publication number: WO1984004437A1
Application number: PCT/AU1984/000072
Authority: WO
Inventors: Clifford Bellamy; Neil Clarke; Peter Gordon; Keith Heale; Patrick Miller; Barry Treloar
Original assignee: Univ Monash
Priority date: 1983-04-29
Filing date: 1984-04-30
Publication date: 1984-11-08
Also published as: EP0148191A1

Abstract

A local area network data communications system of the type providing communication between at least a pair of computer devices interfaced with associated communication nodes (52), said nodes including a transceiver (50, 51) wherein said nodes are commonly connected to a pair of communication lines (53, 54), said lines extending throughout the local area network, said lines carrying transmitted signals, each node being adapted to transmit or receive said data to and from said lines.

Description

DIGITAL COMMUNICATIONS SYSTEM BACKGROUND OF THE INVENTION

The present invention relates to a system of communication with between at least two computers devices and more particularly a digital data communication system incorporating one or more communication bus adaptors consisting of two or more micro-processors and communication interfaces to the bus pathway and to serial communication lines to terminals, computers and to remote bus adaptors forming part of the other local networks.

In the field of local area computer networks a broad class of networks use a common communication bus to connect several communicating entities called nodes in the manner disclosed in U.S. Patent Specification 4063220 assigned to Xerox Corporation. A feature of such a network is that a message transmitted by any node onto the common bus can be received by every other node. It is necessary to devise a method for regulating and controlling the use of the common bus by competing nodes (bus access method). Many methods have been described for example, token passing method or polling method; the one with which the invention is concerned is a method generally known as the "Carrier- sense Multiple Access with Collision-detection" method, abbreviated to "CSMA-C0". The essential features of CSMA-C0 are :

1. Before transmitting, each node monitors the state of the bus. A node begins to transmit only if the bus is sensed to be idle. 2. While transmitting a node tests the signal on the bus to detect interference from other nodes. This can occur if two or more nodes begin transmitting almost simultaneously. When this happens a "collision" is said to have occurred; i.e. two (or more) messages have "collided" on the bus.

3. After a collision all transmitting nodes stop transmitting and a back-off algorithm then determines which of them should start again. We are not concerned with the details of this algorithm, many of which have been devised.

4. It is possible that another collision will occur on the second atempt to transmit the message. If it does, the nodes stop, back-off, and go through the cycle again. The back-off algorithm must be designed so that the cycle does not repeat continuously.

The Carrier-sense Multiple-access method imposes certain requirements on the encoding and decoding sections of the transmitters and receivers used in the nodes:

1. The receiver must be able to proces both the transmissions from nearby nodes (large signal amplitude), and the most distant nodes on the bus (small signal amplitude); i.e. the receiver is required to have adequate cynamic range.

2. In order to detect collisions the receiver must be able to detect a distant (weak) signal in the presence of a strong signal.

3. It is desirable that the receiver be able to detect unequivocally whether the bus is busy or idle.

OBJECTS OF THE INVENTION

1. A principal objective of the present invention is the simple recovery of a timing reference signal (received clock) in a receiver;

2. The simple and unambiguous recovery of received data

3. The operation of the receiver is not affected by the polarity of the received signal; (i.e. the two wires of a balanced medium such as a twisted-wire pair can be reversed without affecting the ability of the receiver to operate) ;

4. Detection of collisions is very fast (within a few bit times), and does not require comparison of trans- itted and received signals;

5. To provide a receiver which needs no preamble signal on which to synchronize;

6. Most of the energy in the transmitted signal is contained in a relatively small bandwidth of frequency. This is important with transmission media such as twisted- wire pairs which are characterized by an attenuation function which increases fairly rapidly with increasing frequency;

7. The transmitted signal has not direct current components. This allows transformer-coupling between the nodes and the bus.

SUMMARY

A local area network data communications system of the type providing communication between at least a pair of computer devices interfaced with associated communication nodes 52, said nodes including a transceiver 50, 51, wherein said nodes are commonly connected to a pair of communication lines 53, 54, said lines extending throughout the local area network, said lines carrying transmitted signals, each node being adapted to transmit or receive said data to and from said lines. More specifically one communication line carries binary one signals and the other line carried binary zero signals.

In one aspect of the invention the data communication lines include non-interacting twisted wire pairs, as a pair of co-axial or twin-axial cables.

The nodes perform the encoding of benary data into a form suitable for transmitting on the communication lines having equal signal capacity as bandwidth, and the decoding of data received from both lines. The line coding method of the present invention does not require a "preamble" thus representing a saving in overheads particularly with short messages.

The two communication lines which are preferably balanced such as a twisted wire pair can be reversed without affecting the ability of the receiver or transmitter to operate.

In a further aspect of the invention the nodes include means to detect and signal the existence of

...-"-'-ό > simultaneous signal pulses on both lines thereby indicating a collision, and means to retransmit data after a predetermined delay.

BRIEF DESCRIPTION OF DRAWINGS

Figure 1 is a schematic block diagram showing cable pairs and node connections.

Figures 2 and 4 are a schematic diagram of a transmitter and receiver in a node respectively. Figures 3 and 5 show pulse diagrams.

DESCRIPTION OF SPECIFIC EMBODIMENT

Each node 52 is connected to non-interacting cables 53 and 54- The cables may be twisted pairs, co- or twin- axial cables.

Each node is controlled by one or more micro processors (not shown) to manage the storage of data in the node, the sequencing of packets of data and the control of the transmitter and receiver sections. For example, when a collision is indicated a node micro-processor is intercepted and a re-transmission procedure is commenced according to a program executed by the micro-processor. Transmitter in the node.

Inputs to the transmitter 50 are a clock signal, serial non-return-to-zero (NRZ) binary data synchronous with the clock signal, and optionally an enable signal.

The timing reference or clock signal is a symmetrical square wave signal of period T seconds whose positive transitions delimit each serial data bit; i.e, the data signal only changes state on positive transitions of the clock. Thus the clock signal is HIGH for the first half (T/2 seconds) of each data bit period and LOW for the second half.

The serial data signal as constituted by any arbitrary sequence of binary ones and zeros.

As shown in Figure 2 the ^•transmitter comprises two main sections: a ONES section 2,4 and 6, and a ZEROS section 3,5 and 7. The two sections are very similar.

The HIGH level pulse of width T/2 occurs at the

PI output of gate 2 when the input data is HIGH. This is called a ONES pulse. For the duration of each ONES pulse the line- driver 6 is enabled and drives a signal onto the ONES line of the bus via transformer winding 8a. 5 The ZEROS section of the transmitter operates in similar fashion when the input data is LOW. Input data passes through inverter 1 to gate 3 where it is combined with the clock signal to form a HIGH level pulse of width T/2 for each ZERO bit in the data. These are called ZEROS

10. pulses, and they enable line-driver 7 which drives the ZEROS line via transformer winding 9a. During the second half of each bit period the ZEROS line is not driven. The polarity in which the line-driver 7- drives the ZEROS line depends on the state of flip-flop 5. This T type flip-flop 5 reverses the output state on the trailing edge of each ZEROS pulse, and thereby causes the sequence of pulses on the ZEROS line to alternate in polarity. This is illustrated in Figure 3 • Asynchronous set and reset inputs to flip-flop 5 are driven from the receiver with signals RECEIVED 0 NEGATIVE ZERO and RECEIVED POSITIVE ZERO respectively. These ensure that at the start of a transmission the ZEROS pulse output by the transmitter is opposite in polarity to the last ZEROS pulse appearing on the ZEROS lineine (regardless of the source of the previous transmission) . 5 Receiver in the node.

The receiver 51 shown in Figure 4 comprises three main sections: a ONES section 10, 11, 12 and 13, a ZEROS section 16, 17, 18 and 19, very similar to the ONES section, and an output section 14, 15 and 20 through 25 in which 0 signals recovered in the two preceding sections are processed in various ways to produce the required outputs.

Input signals to the receiver are RECEIVED ONES (a ternary signal coupled from the ONES line by transformer winding 8b), and RECEIVED ZEROS (likewise a ternary signal 5 but coupled from the ZEROS line by transformer winding 9b). Primary output signals from the receiver are. RECEIVED CLOCK, RECEIVED DATA, and COLLISION. Secondary outputs from the receiver (used by the transmitter) are RECEIVED POSITIVE ONE, RECEIVED NEGATIVE ONE, RECEIVED POSITIVE ZERO, and RECEIVED NEGATIVE ZERO.

In the ONES section, received ONES which may have suffered attenuation and dispersion during transmission over the bus, are first amplified in a limiting differential amplifier 10. The output signal from amplifier 10 is still in basically a ternary form, i.e. alternating positive and negative polarity pulses around a reference level. Output pulses from the amplifier pass to comparator 11 which has balanced threshholds for detecting both positive and negative pulses. The output from comparator 11 changes from LOW to HIGH only when the output of amplifier 10 goes more . positive than the positive threshhold, and likewise changes from HIGH to LOW when the output of amplifier 10 goes more negative than the negative threshhold. The output from comparator 11 drives signal edge-detection circuitry 12 which produces a short positive pulse on each transition of its input waveform (both HIGH to LOW and LOW to HIGH transitions). These pulses trigger monostable multivibrator 13 whose monostable period typically is set to a value between 0.3T and 0.5T, where T is the period of one bit time. Thus the signal appearing at the output of multi¬ vibrator 13 is a reconstructed binary ONES signal. The out- put of 13 is combined with the output of comparator 11 in gates 14 and 15 to form the secondary output signals RECEIVED POSITIVE ONE and RECEIVED NEGATIVE ONE which are ' used by the encoder.

In the ZEROS section received ZEROS are similarly amplified by ampifier 16 and compared with fixed threshholds in comparator 17. The transition of comparator 17 output signal are extracted by edge detection circuit 18 and used to trigger monostable multivibrator 19 which is set to the same period as multivibrator 13. The signal RECEIVED ZEROS at the output of multivibrator 19 is passed to the output section and is also combined with the output of comparator 17 in gates 20 and 21 to form the secondary output signals

OMPI RECEIVED POSITIVE ZERO and RECEIVED NEGATIVE ZERO used by the transmitter.

In the output section the binary signals RECEIVED ONES and RECEIVED ZEROS are combined in various ways to produce the required outputs.

In gate 22 RECEIVED ONES and RECEIVED ZEROS are logically OR'ed together to recover the RECEIVED CLOCK signal.

Cross-coupled gates 23 and 24 form a set-reset flip- flop. RECEIVED ONES is the set input, RECEIVED ZEROS the reset input, and RECEIVED DATA is the output.

During a valid transmission, only one of RECEIVED ONES and RECEIVED ZEROS can be HIGH at any instant of time. If both signals are HIGH this condition is detected by gate 25 and signalled as COLLISION.

Claims

THE CLAIMS DEFINING THE INVENTION ARE AS FOLLOWS:

1. A local area network data communications system of the type providing communication between at least a pair of computer devices interfaced with associated communication nodes 52, said nodes including a transceiver 50, 51, wherein said nodes are commonly connected to a pair of communication lines 53, 54, said lines extending throughout the local area network, said lines carrying transmitted signals, each node being adapted to transmit or receive said data to and from said lines.

2_^ A system as claimed in claim 1 wherein one communication line carries binary one signals and the other line carries binary zero signals.

3. A system as claimed in claim 1 or claim 2 wherein the data comunication links include non-interacting twisted wire pairs, as a pair of co-axial or twin-axial cables.

4- A system as claimed in claim 1, 2 or 3 wherein the communication nodes perform the encoding of binary data into a form suitable for transmitting on the communication lines having equal signal capacity or bandwidth, and the decoding of data received from both lines.

5. A system as claimed in claim 3 wherein the communication lines include a twisted wire pair which are reversable in polarity without affecting the ability of the receiver or transmitter to operate.

6. A system as claimed in claim 2 wherein the communication nodes include means to detect and to signal the existence of simultaneous signal pulses on both lines thereby indicating a collision, and means to retransmit data after a predetermined delay.