WO1984001240A1 - Feedthrough structure for three dimensional microelectronic devices - Google Patents
Feedthrough structure for three dimensional microelectronic devices Download PDFInfo
- Publication number
- WO1984001240A1 WO1984001240A1 PCT/US1983/001389 US8301389W WO8401240A1 WO 1984001240 A1 WO1984001240 A1 WO 1984001240A1 US 8301389 W US8301389 W US 8301389W WO 8401240 A1 WO8401240 A1 WO 8401240A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- major surface
- substrate
- feedthrough
- conductive path
- feedthrough structure
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the invention relates to the structure of semi ⁇ conductor devices and particularly to the structure of microelectronic feedthroughs for three dimensional circuits.
- Feedthrough structures generally are well known.
- a common form of feedthrough is the thermal gradient zone melt (TGZM).
- TGZM thermal gradient zone melt
- U.S. patents Method of Making Deep Diodes, 3,901,736; Deep Diode Device and Method, 3,902,925; Deep Diode Devices and Method and Apparatus, 4,075,038; High Velocity Thermomigration Method of Making Deep Diodes, 3,898,106; The Stabilized Droplet Method of Making Deep Diodes Having Uniform Electrical Properties, 3,899,361; Method of Making Isolation Grids in Bodies of Semiconductor Material, 3,904,442; and Thermomigration of Metal-Rich Liquid Wires Through Semiconductor Materials, 3,899,362.
- Feedthroughs effected by the TGZM process typically have a cross sectional area on the order of one to two mils in diameter. Since no devices can be fabricated on the semiconductor surface occupied by the feedthrough, the presence of the feedthrough reduces the number of devices that can be placed on the semiconductor surface This result is contrary to the everpresent objective to increase the number and density of devices fabricated on a semiconductor device.
- the invention comprises a method and structure for reducing the surface area occupied by the end of the verticle feedthrough in a three dimensional semiconductor circuit device.
- a horizontal conducting path is laid down on a major surface of the substrate, with one end of the conducting path in electrical and physical contact with the feedthrough (e.g. a thermal gradient zone melt, TGZM).
- An epitaxial layer is then P ut down over the major surface covering the TGZM and burying the horizontal conducting path. Electrical contact is made to the other end of the buried horizontal conducting path by diffusion through the newly put down epitaxial layer, or by etching through the new epitaxial layer to the conducting path.
- the diffused region is of the same conductivity type as are the horizontal buried path and the TGZM.
- the cross sectional area of the diffusion region is 25 to 30 square microns compared to the 507 to 2027 square microns area of the TGZM. This results in substantial reduction of the surface area occupied by the ends of the TGZM feedthrough structure and allows more devices to be fabricated on the major surface of the semiconductor.
- FIG. 1 is a cross-sectional view of a section of a semiconductor substrate.
- FIG. 2 illustrates the placement of a feedthrough in the substrate.
- FIG. 3 shows the horizontal conducting means contacting one end of the feedthrough.
- FIG. 4 shows the addition of a thin epitaxial layer covering the feedthrough and horizontal conducting means.
- FIG. 5 shows the electrical connection between the horizontal conducting means and the top surface of the epitaxial layer.
- FIG. 1 shows a cross section of a small portion of semiconductor substrate 10.
- the substrate 10 has a first or top major surface 12 and a second or bottom major surface 14.
- Such a substrate may be stacked with others like it to form a high density three dimensional semiconductor device.
- active devices may be fabricated on both major surfaces 12 and 14 of substrate 10. In both cases it is often desirable to electrically connect a device on one substrate with a device on another substrate or to connect a device on a top major surface such as 12 with a device on a bottom major surface such as 14. Such interconnection is facilitated by the structure 20, as shown in FIG. 2, which comprises an electrically conductive path called a feedthrough. The feedthrough extends from one major surface 12 through the semiconductor substrate 10 to the other major surface 14.
- a semiconductor device on surface 12 may be electrically connected to a semi ⁇ conductor device on surface 14 by connecting the first device to the end 22 of feedthrough 20 lying on surface 12 and connecting the other device to the end 24 of feedthrough 20 which lies on surface 14.
- a semi ⁇ conductor device on surface 14 By connecting the first device to the end 22 of feedthrough 20 lying on surface 12 and connecting the other device to the end 24 of feedthrough 20 which lies on surface 14.
- the feedthrough structure is a convenient means to interconnect devices on opposite sides of a substrate, it does have the disadvantage of occupying substantial space on the major surfaces 12 and 14. Devices cannot be fabricated in the area occupied by the feedthrough nor in the small annular area surrounding the feedthrough. The total space lost can be significant if a number of feedthroughs are present in a single wafer.
- the feedthrough 20 will have a diameter of from 1 to 2 mils, i.e. an area of about 507 square microns to about 2027 square microns.
- a shallow conducting means such as conducting path 30 is fabricated in surface 12.
- the path 30 can be as long as desired and practical and the path may terminate in end 31 wherever convenient and compatible with the contemplated circuit.
- One end of path 30 must contact feedthrough 20 as shown at 32.
- the path 30 is electrically conductive, and of the same conductivity type as is feedthrough 20.
- a thin epitaxial layer 40 is applied as illustrated in FIG. 4 to cover the major surface 12, the end 22 of feedthrough 20, and the conducting path 30.
- Epitaxial layer 40 is of the same conductivity type as is substrate 10, and is relatively thin. The layer 40 may range from 0.5 to 20.0 microns in thickness.
- a conductive path 50 as shown in FIG. 5 is fabricated and extends from surface 42 to path 30. This path 50 may be formed by diffusion through the epitaxial layer 40.
- Path 50 is of the same conductivity as the TGZM and of opposite conductivity as the sub- strate 10. Typically, path 50 may be 5 microns square covering an area of about 25 square microns. This represents a significant decrease from the area of surface 12 occupied by the TGZM which was from 507 to 2027 square microns.
- the surface area of layer 40, located directly above feedthrough 20, is available for fabrication of semiconductor devices.
- the conductive path 50 is located at the distal end 31 of conductive path 30.
- path 30 could be tailored to place conductive path 50 at any desired location.
- all paths 30 on a given substrate could be made to terminate near the perimeter of the substrate. All paths 50 would correspondingly be located near the perimeter of the substrate, leaving the interior area of the substrate totally free of feedthrough connections. If preferred for a particuar application, paths 30 could be eliminated and paths 50 could be formed through layer 40 directly above (or below) the end 22 (or 24) of feedthrough 20. Such a path is shown as path 52 shown in broken lines in FIG. 5. In either case, the percentage of the surface area of surface 42 which is occupied by feedthrough structure is drastically reduced from the percentage of the surface area of surface 12 which is occupied by feedthrough structure. The per ⁇ centage reduction can be on the order of 2_00J2 or 98.7%.
- the substrate 10 will be 10 to 20 mils thick and comprised of a semiconductor of any type IV, type III-V, or type II-VI compound.
- the crystal orientation in silicon is normally ⁇ 100> for the feedthrough direction.
- the major surfaces 12 and 14 are ⁇ 100> oriented surfaces.
- conductive path 50 (and 52) shown extending from surface 42 to path 30 (or to feed- through 20) is shown as a diffused region.
- the conductive paths 50 or 52 could also be formed by etching through layer 40 by conventional techniques and providing a conductor also by conventional techniques, from surface 42 to path 30 (or feed ⁇ through 20).
- the spirit and scope of the invention are intended to be limited only by the appended claims.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A method and structure for reducing the surface area occupied by feedthrough in a semiconductor substrate. A buried horizontal conducting path (30) is laid down on a major surface (12) of a substrate (10), with one end (32) of the conducting path (30) in electrical and physical contact with the feedthrough (20) (e.g. a thermal gradient zone melt TGZM). An epitaxial layer (40) is put down over the TGZM and over the buried horizontal conducting path (30). Electrical contact is made to the distal end (31) of the buried horizontal conducting path (30) by diffusion through the newly put down epitaxial layer (40) or by etching to the conducting path. The diffused region (50) is of the same dopant characteristics and conductivity type as are the horizontal path (30) and TGZM. The cross-sectional area of the diffusion region (50) is 25 to 30 square microns compared to the 507 to 2027 square microns area of the TGZM. This results in substantial reduction of the surface area occupied by feedthrough structures and allows more devices to be fabricated on the surface of the substrate.
Description
FEEDTHROUGH STRUCTURE FOR THREE DIMENSIONAL MICROELECTRONIC DEVICES
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the structure of semi¬ conductor devices and particularly to the structure of microelectronic feedthroughs for three dimensional circuits.
2. Description of the Prior Art
Feedthrough structures generally are well known. A common form of feedthrough is the thermal gradient zone melt (TGZM). For additional information on the TGZM process, one is referred to the following U.S. patents: Method of Making Deep Diodes, 3,901,736; Deep Diode Device and Method, 3,902,925; Deep Diode Devices and Method and Apparatus, 4,075,038; High Velocity Thermomigration Method of Making Deep Diodes, 3,898,106; The Stabilized Droplet Method of Making Deep Diodes Having Uniform Electrical Properties, 3,899,361; Method of Making Isolation Grids in Bodies of Semiconductor Material, 3,904,442; and Thermomigration of Metal-Rich Liquid Wires Through Semiconductor Materials, 3,899,362. Feedthroughs effected by the TGZM process typically have a cross sectional area on the order of one to two mils in diameter. Since no devices can be fabricated on the semiconductor surface occupied by the feedthrough, the presence of the feedthrough reduces the number of
devices that can be placed on the semiconductor surface This result is contrary to the everpresent objective to increase the number and density of devices fabricated on a semiconductor device.
It is therefore an object of the present invention to minimize the surface area of a semiconductor which is occupied by feedthrough structure, thereby permitting an increase in the density, and number, of devices which can be fabricated on the surface.
SUMMARY OF THE INVENTION
The invention comprises a method and structure for reducing the surface area occupied by the end of the verticle feedthrough in a three dimensional semiconductor circuit device. A horizontal conducting path is laid down on a major surface of the substrate, with one end of the conducting path in electrical and physical contact with the feedthrough (e.g. a thermal gradient zone melt, TGZM). An epitaxial layer is then Put down over the major surface covering the TGZM and burying the horizontal conducting path. Electrical contact is made to the other end of the buried horizontal conducting path by diffusion through the newly put down epitaxial layer, or by etching through the new epitaxial layer to the conducting path. The diffused region is of the same conductivity type as are the horizontal buried path and the TGZM. The cross sectional area of the diffusion region is 25 to 30 square microns compared to the 507 to 2027 square microns area of the TGZM. This results in substantial reduction of the surface area occupied by the ends of the TGZM feedthrough structure and allows more devices to be fabricated on the major surface of the semiconductor.
FIG. 1 is a cross-sectional view of a section of a semiconductor substrate.
FIG. 2 illustrates the placement of a feedthrough in the substrate.
FIG. 3 shows the horizontal conducting means contacting one end of the feedthrough.
FIG. 4 shows the addition of a thin epitaxial layer covering the feedthrough and horizontal conducting means.
FIG. 5 shows the electrical connection between the horizontal conducting means and the top surface of the epitaxial layer.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT To meet the ever increasing packaging density demanded in various applications of semiconductor electronics the semiconductor industry has begun to fabricate rather sophisticated devices by stacking multiple substrates one on top of the other. Such circuits are often referred to as three-dimensional devices. Electrical connections are frequently made between the devices on one substrate and devices on another substrate. This interconnection is accomplished by a feedthrough structure. A feed¬ through is an electrically conductive path which extends vertically through the substrate substantially perpendicular to the major surfaces of the substrate. FIG. 1 shows a cross section of a small portion of semiconductor substrate 10. The substrate 10 has a first or top major surface 12 and a second or bottom major surface 14. Such a substrate may be stacked with others like it to form a high density three dimensional semiconductor device. Also, active devices may be fabricated on both major surfaces 12 and 14 of
substrate 10. In both cases it is often desirable to electrically connect a device on one substrate with a device on another substrate or to connect a device on a top major surface such as 12 with a device on a bottom major surface such as 14. Such interconnection is facilitated by the structure 20, as shown in FIG. 2, which comprises an electrically conductive path called a feedthrough. The feedthrough extends from one major surface 12 through the semiconductor substrate 10 to the other major surface 14. A semiconductor device on surface 12 may be electrically connected to a semi¬ conductor device on surface 14 by connecting the first device to the end 22 of feedthrough 20 lying on surface 12 and connecting the other device to the end 24 of feedthrough 20 which lies on surface 14. Such an interconnect is well known and described in the earlier referenced literature.
While the feedthrough structure is a convenient means to interconnect devices on opposite sides of a substrate, it does have the disadvantage of occupying substantial space on the major surfaces 12 and 14. Devices cannot be fabricated in the area occupied by the feedthrough nor in the small annular area surrounding the feedthrough. The total space lost can be significant if a number of feedthroughs are present in a single wafer. Typically the feedthrough 20 will have a diameter of from 1 to 2 mils, i.e. an area of about 507 square microns to about 2027 square microns.
The amount of surface area occupied by feedthrough structure and hence unavailable for fabrication of circuit devices, can be significantly reduced by the method and structure illustrated in FIGS. 3, 4 and 5.
First a shallow conducting means such as conducting path 30 is fabricated in surface 12. The path 30 can be as long as desired and practical and the path may terminate in end 31 wherever convenient and compatible with the contemplated circuit. One end of path 30 must contact feedthrough 20 as shown at 32. The path 30 is electrically conductive, and of the same conductivity type as is feedthrough 20.
Next, a thin epitaxial layer 40 is applied as illustrated in FIG. 4 to cover the major surface 12, the end 22 of feedthrough 20, and the conducting path 30. Epitaxial layer 40 is of the same conductivity type as is substrate 10, and is relatively thin. The layer 40 may range from 0.5 to 20.0 microns in thickness. Finally, a conductive path 50 as shown in FIG. 5 is fabricated and extends from surface 42 to path 30. This path 50 may be formed by diffusion through the epitaxial layer 40. Path 50 is of the same conductivity as the TGZM and of opposite conductivity as the sub- strate 10. Typically, path 50 may be 5 microns square covering an area of about 25 square microns. This represents a significant decrease from the area of surface 12 occupied by the TGZM which was from 507 to 2027 square microns. The surface area of layer 40, located directly above feedthrough 20, is available for fabrication of semiconductor devices.
As shown in FIG. 5, the conductive path 50 is located at the distal end 31 of conductive path 30. With this configuration, path 30 could be tailored to place conductive path 50 at any desired location.
Specifically, all paths 30 on a given substrate could be made to terminate near the perimeter of the substrate. All paths 50 would correspondingly be located near the perimeter of the substrate, leaving the interior area of the substrate totally free of feedthrough connections. If preferred for a particuar application, paths 30
could be eliminated and paths 50 could be formed through layer 40 directly above (or below) the end 22 (or 24) of feedthrough 20. Such a path is shown as path 52 shown in broken lines in FIG. 5. In either case, the percentage of the surface area of surface 42 which is occupied by feedthrough structure is drastically reduced from the percentage of the surface area of surface 12 which is occupied by feedthrough structure. The per¬ centage reduction can be on the order of 2_00J2 or 98.7%.
2027
Whenever a feedthrough such as 20 is formed in a substrate 10, microscopic structural defects appear in the substrate 10 immediately surrounding the feed¬ through 20. These defects effectively increase the area of surface 12 which is unsuited for fabrication of devices. Thus, as a design rule of thumb, it is typical that no devices are fabricated closer than about 25 microns from the feedthrough. The percentage improvement noted above is thus a conservative figure. Because the layer 40 covers over and fills in these defects, it is expected that the above discussed method will improve the net yield of substrates utilizing the TGZM process.
Typically the substrate 10 will be 10 to 20 mils thick and comprised of a semiconductor of any type IV, type III-V, or type II-VI compound. To produce well con¬ trolled feedthroughs, the crystal orientation in silicon is normally <100> for the feedthrough direction. Thus the major surfaces 12 and 14 are <100> oriented surfaces. While the invention has been described with particular reference to FIGS. 1 through 5, the figures and description are for purposes of illustration only and are not to be interpreted as limitations upon the invention. Many changes in material and structure may be made by one having ordinary skill in the art, without departing from the spirit and scope of the invention.
OMPI
As an example, conductive path 50 (and 52) shown extending from surface 42 to path 30 (or to feed- through 20) is shown as a diffused region. The conductive paths 50 or 52 could also be formed by etching through layer 40 by conventional techniques and providing a conductor also by conventional techniques, from surface 42 to path 30 (or feed¬ through 20). The spirit and scope of the invention are intended to be limited only by the appended claims.
OMPI
Claims
1. In a semiconductor substrate having a first major surface and a second major surface and a feed¬ through structure extending through said substrate from said first major surface to said second major surface, the improvement comprising: an epitaxial layer, of the same conductivity type as said substrate, applied to at least one of said first and second major surfaces covering said feed¬ through structure and forming a new major surface; and a first conductive path of the same con¬ ductivity type as said feedthrough structure formed in said epitaxial layer and extending from said new major surface to the underlying major surface of said substrate; said first conductive path being in electrical communication with said feedthrough structure and having a cross-sectional area substantially less than the cross-sectional area of said feedthrough structure.
2. The improvement according to Claim 1 further comprising a second conductive path having a first end and a second end: said first end joining said second path to said feedthrough structure and said second end joining said second path to said first path; whereby said first path is in electrical communication with said feedthrough structure.
3. The improvement according to Claim 1 or
Claim 2 wherein said feedthrough structure is formed by the thermal gradient zone melt process.
4. The improvement according to Claim 1 or
Claim 2 wherein said first conductive path is formed by diffusion.
5. A method for reducing the surface area occupied by the feedthrough structure of a semiconductor substrate comprising the steps of: applying a relatively thin epitaxial layer of the same conductivity type as said substrate to a major surface of said substrate so as to cover said feedthrough structure and form a new major surface; forming an electrically conductive path through said epitaxial layer and extending from said new major surface to the underlying major surface of said substrate; said electrically conductive path being in electrical communication with said feedthrough structure.
6. A method for reducing the surface area occupied by the feedthrough structure of a semiconductor substrate comprising the steps of: forming a first electrically conductive path in a major surface of said substrate, said first electrically conductive path having a first end joining said feedthrough structure and a second end located remote from said feedthrough structure; applying a relatively thin epitaxial layer, of the same conductivity type as said substrate, to said major surface so as to cover said feedthrough structure and said first electrically conductive path and forming a new major surface; and
. OMPI forming a second electrically conductive path through said epitaxial layer and extending from said new major surface to the underlying second end of said first electrically conductive path; with the cross- sectional area of said second electrically conductive path being much less than that of the feedthrough structure; whereby said second electrically conductive path is in electrical communication with said feedthrough structure and occupies less area of said new major surface than said feedthrough structure occupied of the original uncovered major surface of said substrate.
7. The method of Claim 6 wherein said second electrically conductive path is formed by diffusion.
OMPI
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US41727682A | 1982-09-13 | 1982-09-13 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1984001240A1 true WO1984001240A1 (en) | 1984-03-29 |
Family
ID=23653295
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1983/001389 WO1984001240A1 (en) | 1982-09-13 | 1983-09-08 | Feedthrough structure for three dimensional microelectronic devices |
Country Status (3)
Country | Link |
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EP (1) | EP0118553A1 (en) |
IT (1) | IT8348952A0 (en) |
WO (1) | WO1984001240A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0390274A1 (en) * | 1989-03-29 | 1990-10-03 | Koninklijke Philips Electronics N.V. | Semiconductor device comprising unidimensional doping conductors and method of manufacturing such a semiconductor device |
DE10205026C1 (en) * | 2002-02-07 | 2003-05-28 | Bosch Gmbh Robert | Semiconductor substrate used for vertical integration of integrated circuits comprises a first conductor strip on its front side, and a region formed by insulating trenches and electrically insulated from the substrate |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3787252A (en) * | 1968-07-05 | 1974-01-22 | Honeywell Inf Systems Italia | Connection means for semiconductor components and integrated circuits |
FR2295570A1 (en) * | 1974-12-20 | 1976-07-16 | Ibm | ELECTRICAL ASSEMBLY FOR INTEGRATED CIRCUITS AND ITS ASSEMBLY PROCESS |
US3982268A (en) * | 1973-10-30 | 1976-09-21 | General Electric Company | Deep diode lead throughs |
-
1983
- 1983-09-08 EP EP83903072A patent/EP0118553A1/en not_active Withdrawn
- 1983-09-08 WO PCT/US1983/001389 patent/WO1984001240A1/en unknown
- 1983-09-09 IT IT8348952A patent/IT8348952A0/en unknown
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3787252A (en) * | 1968-07-05 | 1974-01-22 | Honeywell Inf Systems Italia | Connection means for semiconductor components and integrated circuits |
US3982268A (en) * | 1973-10-30 | 1976-09-21 | General Electric Company | Deep diode lead throughs |
FR2295570A1 (en) * | 1974-12-20 | 1976-07-16 | Ibm | ELECTRICAL ASSEMBLY FOR INTEGRATED CIRCUITS AND ITS ASSEMBLY PROCESS |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0390274A1 (en) * | 1989-03-29 | 1990-10-03 | Koninklijke Philips Electronics N.V. | Semiconductor device comprising unidimensional doping conductors and method of manufacturing such a semiconductor device |
DE10205026C1 (en) * | 2002-02-07 | 2003-05-28 | Bosch Gmbh Robert | Semiconductor substrate used for vertical integration of integrated circuits comprises a first conductor strip on its front side, and a region formed by insulating trenches and electrically insulated from the substrate |
Also Published As
Publication number | Publication date |
---|---|
EP0118553A1 (en) | 1984-09-19 |
IT8348952A0 (en) | 1983-09-09 |
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