WO1984001218A1

WO1984001218A1 - Automatic temperature measuring circuitry

Info

Publication number: WO1984001218A1
Application number: PCT/US1983/001487
Authority: WO
Inventors: Neil L Brown
Original assignee: Brown Instr Syst
Priority date: 1982-09-24
Filing date: 1983-09-24
Publication date: 1984-03-29
Also published as: EP0120943A1; EP0120943A4; CA1205650A

Abstract

An AC temperature measurement circuit utilizing a standard platinum resistance thermometer (14) (SPRT) which is supplied with a constant current (IREF) through a precision resistance (13). The voltage across the SPRT is multiplied by a fixed gain by means of a high gain AC feedback amplifier (18). The ratio of the output of the fixed gain AC feedback amplifier (23) to the AC reference voltage (ET) across the precision reference resistance is effectively determined using a digital-to-analog (D/A) transformer(15). The resistance value of the SPRT (14) is then determined as a function of the reference resistance value, the value of the fixed gain, and the value of such ratio. Appropriate means (16) are provided to determine the temperature represented by the resistance value of the SPRT.

Description

AUTOMATIC TEMPERATURE MEASURING CIRCUITRY

Introduction

This invention relates generally to circuitry for measuring temperature and, more particularly, to bridge circuitry utilizing precision resistance thermometers for providing automatic measurement of temperature.

Background of the Invention Standard platinum resistance thermometers (SPRT) have been used to measure temperature, the resistance of such elements being related to temperature in accordance with standard equations as defined with reference to the International Practical Temperature Scale (IPTS). Since such elements provide accurate measurements of temperature as needed in many applications, there has existed a further need for making rapid measurements of the resistances of such devices in an automatic fashion.

Automatic measurement of such resistances to the required degree of accuracy have previously been suggested by those in the art utilizing direct current methods. However, the use of DC . circuitry is not practical in most applications requiring high accuracy because of the problems encountered with respect to thermally generated emf's and detector noise levels. Accordingly, attention has been directed toward the use of AC bridge circuits which would eliminate such problems.

Previously suggested AC bridge circuits (both manual and automatic embodiments thereof) have generally used one of two basic approaches. A first approach maintains essentially the same current through the standard platinum resistance thermometer and through a reference resistor and then measures the ratio of the voltages thereacross. The voltage ratio measurements are conventionally made by using adjustable ratio transformers. Such an approach has been described, for example, in the article by

SUBSTITUTE SHEET

IPO Hill and Miller, Proc. Inst. Electr. Eng., Vol. 110, No. 453 (1963). Such article describes a double bridge configuration analogous to Kelvin double bridge circuitry using two complete adjustable voltage ratio transformers. An automatically operated version of such bridge circuit has also been made available by Automatic Systems Laboratories, Ltd. of Leighton Buzzard, England.

A later version of an AC bridge circuit using a three-stage ratio transformer in which two stages are driven by unity-gain buffer amplifiers to provide the required input impedance has been

10 suggested in the article by Cutkosky, Jour. Res. of Nat. Bur. Stds., Vol 74C, Nos. 1 and 2, 15 (1970). An automated version of such bridge circuit, controlled by an appropriate micro-processor, was later described by Cutkosky and used 15 Hz. or 30 Hz. square wave excitation and a five-stage transformer to achieve the ^r--^r required input impedance in parallel with a reference resistor.

The latter circuitry is described in the article by Cutkosky, IEEE Trans. Instr. & Meas., Vol 1M-29, No. 4 (1980).

In the later Cutkosky design the input impedance is progressively increased from stage to stage by connecting each 0 stage in parallel with five equal resistors all connected in series with each other and in series with the SPRT device. The value of each resistor becomes progressively more critical from the first to the fifth stage and the fifth stage resistor represents the required reference resistor. 5 Another approach suggested by the art adjusts the relative magnitudes of the currents in order to maintain the voltages across the reference resistor and the standard platinum resistance thermometer equal. Such approach became feasible with the development of a DC current comparator which could provide DC 0 measurement of high precision. Such a DC comparator has been described, for example, in the article by McMartin and Kusters, IEEE Trans. Inst. & Meas., 1M-15, No. 4 (1966).

All of the previously suggested designs utilize the inherent stability and accuracy of ratio transformers and require only a

SUBSTITUTE SHEET

OMPI V IP single reference resistor in order to achieve performances substantially superior to purely resistive bridges which normally require a multiplicity of critical resistance values and resistance ratios and which are sensitive to thermal coefficients

5 and thermal emf's. In order to achieve automated operation for the bridge balancing process, such designs required numerous electro-mechanical relays. Because the switching circuits were carrying significant currents, they could not tolerate the use of solid state switches, such as field effect transistors .(FET's)

10 which have finite resistances in their "ON" states.

Brief Summary of the Invention

In accordance with the invention a basic bridge circuit utilizes constant current reference circuitry for providing a 15 constant reference current through a precision reference resistance and through a standard platinum resistance thermometer (SPRT) element. The voltage across the SPRT element is supplied to a fixed-gain amplifier circuit the output of which is in turn supplied to a digital-to-analog (D/A) measurement circuitry. The 20 D/A circuit permits an effective determination of the ratio of the .. output from the fixed-gain amplifier circuit and a reference voltage across a known reference resistance in the constant current reference circuit. The resistance of the standard platinum resistance thermometer can then be determined in terms of 25 the value of the fixed-gain of the fixed-gain amplifier circuit, ;.7 the value of the reference resistance, and the value of such voltage ratio.

Such circuitry, as described in more detail below, provides for a completely automated measurement of the SPRT resistance with 30 very high accuracy, which resistance can be readily converted ;-^*. using appropriate micro-processor circuitry, for example, to a temperature reading which has an extremely low error. The overall circuitry is designed so that suitable solid state switches and transformers of relatively simple construction can be used,

_SUBST TUTE SHEE

OMPI

^/ WIPO thereby providing relatively high-speed operation having relatively low noise and high reliability.

Description of the Invention The invention can be described in more detail with the help of the accompanying drawings wherein

FIG. 1 depicts a block diagram of an embodiment of the invention;

FIG. 2 depicts a more specific partial block and partial schematic diagram of the embodiment of FIG. 1;

FIG. 3 depicts a more specific partial block and partial schematic diagram of a portion of the embodiment of FIG. 1;

FIG. 4 depicts a timing diagram helpful in explaining the operation of FIG. 3; FIG. 5 depicts the interconnection of the reference circuit of FIG. 1;

FIG. 6 depicts a partial block and partial schematic diagram showing more particularly the D/A converter of FIGS. 1 and 2; FIG. 7 depicts in diagrammatic form the switches used in the D/A converter of FIG. 6; and

FIG. 8 depicts a partial block and partial schematic diagram showing the automatic quadrature balance circuitry of FIG. 3.

The simplified block diagram of FIG. 1.can be used to illustrate the principles of operation of the circuitry of the invention. As can be seen therein, AC source 10 supplies an AC voltage through a primary winding HA of a first stage of a transformer 11, the secondary winding 11B of which provides a drive voltage Erj to a reference current circuit 12 which in turn supplies a constant current IREF to a standard platinum resistance thermometer (SPRT) element 14 having a resistance R-j* which is proportional to the temperature.

The voltage ET; across SPRT element 14 is supplied to a

._UEST1TUTE SHEET - 5 -

fixed-gain AC feedback amplifier circuit 15 (identified as having a fixed-gain Gp) which produces an output voltage Ej_j. Such voltage is supplied to D/A measurement circuit 16 which is arranged so that when a plurality of switches therein are suitably set (as discussed in more detail below), the voltage E_a therefrom can be made substantially equal to the voltage E_ .

The reference circuit 12 includes a reference resistance 13 through which the current IREF flows, the voltage across such reference resistance being designated as Ejj-gp.

The voltage Ex across SPRT element 14 can be defined by the current therethrough and the resistance thereof as

^EREF RT

E-p =^•

RRFE

Since the voltage E_j-. is related to the voltage E*^*** by the gain Gp of fixed-gain amplifier 15, the resistance of SPRT element 14 can be expressed as follows:

^Eb ^RREF

RT =

EREF ^GF

Since the resistance of reference resistor 13 and the gain of amplifier 15 are known and predetermined, if the ratio of the voltages E^*-,/EREP can be determined, the resistance of the thermometer element can also be determined.

If the voltage E_a is set equal to the voltage E^ by the controlled operation of the D/A measurement circuit via the detection/integration circuitry 17 and control logic 18 (as discussed below), the resistance of SPRT element 14 can be

SUBSTITUTE SHEET expressed as

^Ea ^RREF

RX =

^EREF ^GF

It is found that, if the switches in D/A measurement circuit 16 are set by control logic 18 for such condition, such switches in effect represent a binary number the decimal equivalent of which is proportional to the value of the ratio E_a/ER F- Accordingly, the resistance of the SPRT element 14 can be calculated (using suitable computational logic such as available through the use of a microprocessor) from the known values of R EF ^and Gp and from the value of the ratio

^Ea/EREF suitably determined from the settings of the switches in the D/A measurement circuit 16. Using appropriate look-up tables, or suitably devised algorithms known to the art for example, the microprocessor can thereupon determine the temperature in accordance with the known International Practical Temperature Scale which defines the relationship between the SPRT resistance R and temperature.

A more specific configuration of an overall resistance thermometer circuit is shown in FIG. 2 in which AC source 10 is a suitable sine wave oscillator 20 which supplies the primary winding HA of the first stage of transformer 11 with a sine wave signal at a suitably selected frequency which in the particular embodiment being described herein, for example, is 384 Hz. The secondary winding 11B of transformer 11 provides the input drive voltage E_ for the reference current circuit 12 which includes reference resistor 13 and a standard platinum resistance thermometer 14 as shown. The reference winding 11C of the second stage of transformer 11 and a high gain AC feedback amplifier 18 are connected as shown so that the current IREF through SPRT

SUBSTITUTE SHEET 14 is constant and provides a voltage E thereacross. The voltage Ex is supplied to fixed-gain AC feedback amplifier circuit 15. Such circuitry includes an input transformer 22, op-amp 23 and output transformer 25. A feedback winding 26 of output transformer 25 provides the output voltage E5 of circuit 15. The overall circuit has high -Q and is sharply tuned to provide a relatively high gain such that Eb=GfEχ. A specific circuit for implementing the fixed-gain AC feedback amplifier circuitry 15 of FIG. 2 is described in my copending application, Serial No. , entitled "Band-Pass Amplifier

Filters", filed concurrently with, and having the same filing date as, this application, such application being incorporated by reference. As explained therein such circuit has a peak amplitude at the operating frequency of the system (e.g., 384 Hz) and the overall phase shift introduced by the transformers and op-amp is substantially less than 180° at frequencies at which the closed loop gain is unity.

The D/A measurement circuit 16 comprises a first two-stage transformer having stages identified as T\_a and T15 in FIG. 2 followed by a second two-stage transformer having stages identified as Ϊ2_a and Ϊ2b ⁱⁿ FIG. 2. The settings of variable winding 11D of stage Tj]-, and of variable winding HE of stage Ϊ2 ^as determined by control logic 18 produces the desired voltage E_a. When (E_a-E^) is effectively reduced to zero, such voltages are equal as desired.

As can be seen in FIG. 2, the relationship of E_a to E EF can be determined in accordance with the number of turns on windings 11C, HD and HE as follows:

N_a + N_bk

EREF ^NREF

SUBSTITUTE SHEET where N_a are the turns on winding HD of T__ , fc, are the turns on winding HE of T25, NREJΓ are the turns on winding HC of T^*-, and k is the stepdown ratio of Tj to

T₂-

The number of turns N_a and N^ are determined by the settings of a plurality of FET switches (discussed in more detail below for a specific embodiment of the D/A circuit 16) represented in FIG. 2 by settings S_a and S_ . Such settings are controlled by control logic 18 which utilizes a successive

10 approximation technique until the value of E_a is equal to

E-, in a first operation which provides switch settings representing the most significant bits (MSB) of the binary number, followed by a second operation which provides the least significant bits (LSB), as discussed below.

^*-*5 A suitable technique utilizing a successive approximation for providing the desired operation to produce the settings for switches S_a and Sj-. has been described in detail in my copending application, Serial No. . , entitled "Systems for

Providing Digital Representations of Analog Values," filed 0 concurrently with, and having the same filing date as, this application, such application being thereby incorporated by reference. The overall circuitry for such operation is generally reproduced in its general form in FIG. 3 and, as explained in the ^■ aforesaid copending application, has two distinct modes of 5 operation.

The purpose of such circuitry during the first mode of operation is to provide to a successive approximation register

(SAR), which controls the settings of D/A switches, an indication as to whether the output of the D/A converter is greater or less 0 than the output of the bridge, i.e., is E_a greater or less than E^*-,. Consequently, during this mode the input switch

S_c and the mode control switches S _a through S**^ are in the position shown. The difference E_e between Efc and

SUBSTITUTE SHEET E_a will be in phase or 180° out of phase depending on whether E_j, is greater or less than E_a. Such "error" signal is amplified in a preamplifier 30, detected in the phase sensitive detector 31 and the resulting DC signal is then applied to a relatively fast "finite" time integrator 32 the output thereof being supplied to a comparator OP-AMP 33. The reset switch Sj of the integrator circuit is momentarily closed to reset the integrator at the beginning of each clock pulse to the successive approximation register. The time constant of he integrator is selected (e.g., 100 microseconds) and the clock frequency is one-half the bridge excitation frequency. The output of the comparator is applied to the data input of the SAR thus determining the setting of the switches in the D/A circuit (shown in more detail in FIG. 6) and, hence, drives the output of the D/A circuit towards equality with the bridge output. Such setting represents the most significant bits of the binary number, the decimal equivalent of which is proportional to the desired ratio

V^EREF-

The above mode of operation occurs during the time interval T^* as shown in the timing diagram of FIG. 4. During Ti the inputs to the band pass amplifier 34 and the low pass Bessel filter 35 of FIG. 3 are grounded to avoid overload.

During the second mode of operation which occurs during intervals T through T5 of FIG. 4, the analog output represented by the residual error signal (E_e) remaining after the first mode of operation has been completed has been converted to a binary output using a dual slope integrator 36, as discussed in the aforesaid depending application and as also described in copending application Serial No. 147,220, filed on May 6, 1980. At the beginning of time interval T2 the mode switches Sι_a through S^ are set to position 2. In such position the residual error signal is amplified by the preamplifier and the band pass amplifier 34 in cascade, and synchronous detector 31 is connected to the output of the band pass amplifier. Interval

SUBSTITUTE SHEET T2 is used to allow the band pass amplifier, the synchronous detector 31 and the Bessel filter 35 to stabilize. During the intervals T_j and T2 the dual slope integrator 36 is maintained at zero output by opening switch S_e and closing reset switch Sf. At the end of T2 the output of the Bessel filter is a steady DC voltage proportional to E_e. At the beginning of T3 switches S_e and Sf are reversed resulting in the output of the dual slope integrator providing a ramp output signal at a rate and in a direction depending on the magnitude and phase of the error signal, as shown in FIG. 4. At the end of T3, switch S_e opens and S_c is set by the control logic to either position 2 or position 3, depending on the polarity of the output of the dual slope integrator. This results in a low level reference AC signal E_r or minus E_r whose magnitude is equal to four times the magnitude represented by the least significant bit output of the D/A circuit. This results in a relatively large output of opposite polarity from the Bessel filter which is allowed to reach steady state output during time interval T4. At the end of T4 the switch S_e is closed resulting in the dual slope integrator providing an output which ramps back towards zero voltage. The time interval T5 is proportional to the residual error signal and is measured from the end of T4 to the time of zero crossing as detected by the comparator OP-AMP 33. A clock output of a selected frequency (e.g. 98304 Hz) is generated by means of an appropriate clock circuit (such a circuit may utilize a phase-lock loop frequency multiplier locked to the 387 Hz. bridge excitation signal, for example). Such clock signal is gated to the input of a suitable binary counter (not shown during T5 thereby resulting in a count which is proportional to such time interval. Since changes in gain of any of the circuits described in FIG. 3 affect both E_e and E_r equally, they have no real effect on the final result.

Specific circuitry for the preamplifier 30, the band pass

SUBSTITUTE SHEET amplifier 34, the phase sensitive detector 31 and the low pass Bessel filter 35, as well as the finite time integrator 32 and the dual slope integrator 36 is shown in the aforesaid copending application, Serial No. , filed concurrently herewith, and need not be described in greater detail here.

Referring back to the reference current circuit of FIG. 2, the AC feedback amplifier 18 has a very high open loop gain (e.g., in a particular embodiment an open loop gain of 2.5 x 10') at the operating frequency of the circuit (384Hz.) and has an amplitude and phase response with frequency which permit it to operate in a closed loop with 100% feedback with excellent stability. A suitable reference current IR F ^of ••• ^mA» f°^r example, can be obtained by making EREF equal to 10 volts (rms) and RREF equal to 10,000 ohms. When the SPRT is at its maximum value of 125 ohms, for example, the output of AC feeedback amplifier 18 will be 0.125 volts and the input will be 5 x 10^~9 volts. Consequently, the open circuit voltage between the voltage terminal of the reference resistor and ground will differ from the open circuit voltage between Vj and V2 across RREF by only one part in 5 x lO^-**-^. Thus the reference voltage E F clearly represents an accurate version of the voltage across the reference resistance.

The reference resistor can be, for example, a 10,000 ohms oil filled metal film on glass type resistor made by Vishay Corporation of Malvern, Pennsylvania. Such a reference resistance is temperature controlled to within ±0.003°C.

FIG. 5 shows in more detail how the reference current circuit is interconnected. The coaxial connections used as shown therein considerably reduce errors due to inductive effects and noise pickup from all external sources. Also, the method of interconnection was selected so that the capacitance of the coaxial leads does not affect the operating results of the circuit since such capacitance is in parallel with a very low impedance source such as the output of AC feedback amplifier 18, and is also

in parallel with the input of amplifier 18 which has virtually zero input, and is in parallel with Rx whose resistance is so low that the capacitance of its coaxial leads does not cause serious quadrature effects. Dielectric loss in such leads (20 foot length) results in a shunt resistance of approximately lθ9 ohms with a resulting error of 0.125 ppm for a 25 ohm thermometer. The quadrature signal resulting from the lead capacitance can be automatically balanced by a suitable quadrature balance circuit 37 in FIG. 3, as discussed below.

10 Accordingly, the reference current circuit will cause a reference current IREF to flow through the SPRT which is very accurately given by the ratio of EREF/^RREF-

The reference voltage circuit consists of the second stage transformer winding HC in parallel with the voltage terminal ^**--' Vi of the reference resistor and ground. Since this results in a small current flowing in V_j, the reference voltage can be defined as the voltage between the reference junction J and ground (see FIG. 5). It can be shown that the output voltage E_π across any winding W_n is given by 0

En = EREF U+e)

^WREF 5 where R F is the same as winding HB and e_^ is the fractional ratio error. The fractional ratio can be expressed as follows:

SUBSTITUTE SHEET where R- and Rχ2 ^are lead resistances, UB ^anc**

^R11C ^are winding resistances as shown in FIG. 5. Z is the excitation impedance of transformer stage T _ (FIG. 2). For exemplary values of R-Q + RQB = 0.75 ohms, Rχ2 +

^R11C ⁼ -- °* ^m- ^anc-* *^^or ^ ⁼ 2500 ohms resistive (effectively the worst case) the fractional error e is 2.998 x 10-*--. Since this fractional ratio error is extremely small and is therefore, negligible, the aforesaid equation can be rewritten as follows:

,n

^En - ^EREF

WREF

Thus the voltage E_n (i.e. the voltage across winding HD for any particular setting S_a - FIG. 2) is equal to the reference voltage EREF times the turns ratio W_Π/WREF of the winding HC to the reference winding HB^*j_.

A D/A measurement circuit 15 is shown in FIG. 6 as comprising a two-stage transformer (Tι_a and T _ ) having, in the particular version described, six output windings S^* through S of 32, 16, 8, 4, 2, and 1 turns forming six bits. A second two-stage transformer has two input windings W^* and W2, each having 128 turns, driven by single turn output windings on the first two-stage transformer. Consequently, the output voltage on winding W3 of 64 turns on the second transformer is one-half the output on winding W4 of the first two-stage transformer, thus continuing the binary weighted ratios on the 7 windings of the second two-stage transformer to form a a total of 13 binary stages. The states of switches S]_ through S13 in FIG. 6 represent the binary value of the sum of the 13 voltages across such windings. Thus, the D/A converters are current summing devices.

Each of the switches can be, for example, implemented by a pair

SUBSTITUTE SHEET of field effect transistors (FETs) and as shown in FIG. 7 each of the switches Si - S13 can be equivalently formed of such FET pair. The FET of each pair is turned ON or OFF directly by its associated control line from control logic 18 while the other is driven to the opposite state by inverting the control line logic as shown in FIG. 7. Appropriate transistors of the VMOS type can be utilized such as those sold under the model designation IVN 5001AND made and sold by Intersil Corporation of

Thus, in FIG. 6 the switches are appropriately controlled so as to provide a summed voltage E^ across the switches

S1-S13 which is equal to the bridge output voltage E_ . The decimal equivalent of the binary number in such condition then is proportional to the ratio of the D/A output voltage E_a to the reference voltage EREF ^as desired. As discussed above, the overall digitization process is controlled by conventional logic and timing circuits. Other logic operations are controlled by a microprocessor which can be used to set up the bridge for a selected mode of operation, to start the digitization process, to read and process the data when the digitization is complete. Processed data can be displayed or transmitted to external devices via optional interfaces within the skill of the art. Microprocessors as known can be controlled by manual inputs to a front panel keypad, for example, or optionally controlled by external devices through appropriate interfaces. Thus, in a particular embodiment the initial successive approximation measurement provides 13 most significant bits while the second measurement (dual slope integration) provides 13 least significant bits so as to produce an overall 26-bit bridge output which can be converted to the resistance in accordance with the following equation:

RREF N

RX ₌

5 x 230

SUBSTITUTE SHEET where R F I^{S tne} reference resistance and N is the 26-bit bridge output expressed in decimal form.

Conversion of the resistance to temperature is accomplished by the standard IPTS-68 equations for SPRT operation. A microprocessor can perform the calculation of resistance to temperature while the bridge is digitizing.

A quadrature component in the error signal E_e can cause errors despite the fact that the phase sensitive detector 312 as shown in FIG. 3 theoretically has zero response to quadrature. For example, if such quadrature component is large enough it can cause an overload in the band pass amplifier or detector which results in non-linear operation with erroneous response to small in-phase signals. For such purpose an automatic quadrature balancing circuit 37 as shown in FIG. 3 can be used. A particular embodiment of such a circuit is shown in more detail in FIG. 8 and represents a negative feedback loop which forces the quadrature component of the input voltage

to zero at the output without modifying the in-phase component.

The input voltage is supplied to the positive input of an OP-AMP 40 utilizing a tuned circuit 41 which provides a broadly tuned amplifier which results in an input to a linear analog multiplier 42. The other input to the multiplier is a sine wave voltage which is in exact quadrature with the bridge input voltage which is obtained as a quadrature reference input from the bridge reference signal.

The output of multiplier 42 will contain a DC component which is exactly proportional to the quadrature component at the other input to multiplier 42. Such DC component causes the integrator circuit 43 to change. The output of the integrator is an input to a second multiplier 44 (substantially identical to multiplier 42) the other input of which is also the quadrature sine wave signal. The output of multiplier 44 will be a quadrature voltage

SUBSTITUTE SHEET proportional to its input. The negative feed-back current through resistor 45 will exactly cancel the quadrature current flowing in the input resistor 46 thus reducing the quadrature component at the output signal EQUT ^to zero. Such a circuit can be utilized in FIG. 3 should a quadrature component be present to cause errors.

SUBSTITUTE SHEET

Claims

WHAT IS CLAIMED IS:

1. An AC temperature measurement system comprising a temperature resistance element having a resistance value which varies with temperature; a reference resistance element having a predetermined fixed value and connected in series with said temperature resistance element; means for supplying a substantially constant AC current through said temperature resistance element and said reference resistance element;

AC feedback amplifier circuit menas responsive to the AC voltage across said temperature resistance element for amplifying said AC voltage by a fixed gain to produce an amplified AC voltage output; means for providing an AC reference voltage across said reference resistance element; means for effectively determining the value of the ratio of said AC voltage output to said AC reference voltage; means for determining the resistance value of said. temperature resistance element as a function of said reference resistance value, said fixed gain, and the ratio of said AC voltage output to said AC reference voltage; and means responsive to said temperature resistance value for determining the temperature represented thereby.

2. A system in accordance with claim 1 wherein said temperature resistance element is a standard platinum resistance thermometer and said reference resistance element is a precision resistor.

3. A system in accordance with claim 2 wherein said AC feedback

SUBSTITUTE SHEET amplifier circuit means includes: an input transformer circuit responsive to the AC voltage across said temperature resistance element for providing an input transformer signal; an amplifier-filter circuit responsive to said input transformer signal and having closed loop amplitude/phase response characteristics such that said circuit has a fixed gain for providing an output signal having a peak amplitude at the selected operating frequency of said system; an output transformer responsive to said output signal for providing said fixed gain amplified AC voltage output, said output transformer further including a feedback winding for supplying a feedback, portion of said amplified AC voltage output to said input transformer for combining with said AC voltage across said temperature resistance element; the overall phase shift introduced by said input transformer, said amplifier-filter circuit and said output transformer being substantially less than 180° at frequencies at which the closed loop gain of said system is unity.

4. A system in accordance with claim 3 wherein said ratio determining means includes: transformer means having a variable winding means and means for controlling the setting of the number of turns of said variable winding means so as to produce a variable winding voltage output; said transformer means further including a reference winding which provides said AC reference voltage; means for comparing said variable winding voltage output with the amplified AC voltage output of said fixed gain AC feedback amplifier circuit means, said controlling means being responsive to the difference between said compared voltage outputs for controllably setting the number of turns of said variable winding means so that said variable winding voltage output is equal to

SUBSTITUTE SHEET said amplified voltage output, the ratio of said variable winding voltage output to said AC reference voltage being determined by the ratio of the number of turns of said variable winding means to the number of turns of said reference winding, whereby when said variable winding voltage output is equal to said AC voltage output, the ratio of the number of turns of said variable winding means to said reference winding effectively determines the ratio of said AC voltage output to said AC reference voltage.

5. A system in accordance with claim 4 where said transformer means is a digital-to-analog transformer means which includes a first two stage transformer having a plurality of first discrete windings each having an associated two position switch for controllably summing the voltages across a selected number of said first discrete winding depending on the positions of said switches; a second two stage transformer having a plurality of second discrete windings each having an associated two position switch for controllably summing the voltages across a selected number of said second discrete windings depending on the positions of said switches; the settings of said switches providing a digital representation of the ratio of said variable winding voltage output to said reference voltage.

6. A system in accordance with claim 1 wherein said constant AC current supplying means includes an A-C feedback amplifier circuit having a high open loop gain connected to said reference resistance element and to said temperature resistance element.

_SUBSTITUTE SHEET ^_τ

V- V.-IP

7. A system in accordance with claim 6 wherein the interconnections between the reference resistance element, the high gain AC feedback amplifier and the temperature resistance element of said reference circuit means are coaxial connective leads arranged so that quadrature effects due to the capacitances of said leads are substantially reduced.

8. A system in accordance with claim 5 wherein said controlling means includes means responsive to the difference between said fixed gain amplified voltage output and the voltage summed across said first and second discrete windings in a first operating mode for providing an output representing the most significant bits of said digital representation of said ratio and responsive in a second operating mode for providing an output representing the least significant bits of said digital representation of said ratio.

9. A system in accordance with claim 8 wherein said control means operating in said first operating mode includes finite time integrating means.

10. A system in accordance with claim 9 wherein said control means operating in said second operating mode includes a dual slope integrating means.

11. A system in accordance with claim 10 wherein said controlling means further includes an automatic quadrature balancing circuit responsive to the difference between said fixed gain amplified voltage output and the voltage output summed across said first and second discrete windings for reducing quadrature

_•DESTITUTE SHEET 21 -

effects in said difference to zero.