WO1984000835A1 - First-in, first-out (fifo) memory configuration for queue storage - Google Patents
First-in, first-out (fifo) memory configuration for queue storage Download PDFInfo
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- WO1984000835A1 WO1984000835A1 PCT/US1983/000190 US8300190W WO8400835A1 WO 1984000835 A1 WO1984000835 A1 WO 1984000835A1 US 8300190 W US8300190 W US 8300190W WO 8400835 A1 WO8400835 A1 WO 8400835A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F2205/10—Indexing scheme relating to groups G06F5/10 - G06F5/14
- G06F2205/108—Reading or writing the data blockwise, e.g. using an extra end-of-block pointer
Abstract
A first-in, first-out queue has a random access memory (RAM) for storing a plurality of information words, seriatim. A controller is used to insure that only after a complete message, comprising the information words, has been received will a word of that message be read out. Three pointers are used to effect this result. A read pointer addresses the location in the RAM from where a word may be read. A write pointer addresses the location in the RAM where a word may be entered. A third pointer addresses the location in the RAM where the last word of a complete message is stored.
Description
FIRST-IN, FIRST-OUT (FIFO) MEMORY CONFIGURATION FOR QUEUE STORAGE
Technical_Field
This invention relates to digital communications systems and, in particular, to FIFO memories enabling multiword messages to be written therein one word at a time and to be read out therefrom as complete messages. Ba c k gro und of the Invention
In telecommunications transmission systems, there arises sometimes a need to store information from a transmitter because the receiver is busy. The information, however, must be recovered from storage in the same order in which transmitted. This process is known as first-in, first-out (FIFO). In U. S. Patent No. 3,979,733 granted
September 7, 1976 to Mr. A. G. Fraser, there was disclosed a FIFO queue. A read register, in the aforesaid Fraser patent, has recorded therein the address of the next memory cell to be read. Likewise, a write register has recorded therein the address of the next memory cell available for storing data. A comparison of the read and write registers indicates whether the memory cells are all full, all empty or partially empty.
It is frequently desired to use a FIFO queue as a communication path between a data producing process and a separate data consuming process. These processes are typically independent of one another and may not even be controlled from a common clock source. That is, the two processes may be asynchronous with respect to one another. Tie path carries messages from the data producing process to the data consuming process and it is frequently required to guarantee that the consuming process obtain only complete messages.
A problem arises if the data producing process has to abandon a message after inserting some of it into the FIFO queue. In that case, the consuming process may already have started the message. This situation arises, for example, when the data producing process is a transmission line with error detection equipment and the consuming process is a computer. If an error is detected partially through an arriving message, it is usually desired that the message be discarded and not processed by the computer.
In the aforesaid Fraser patent, however, there is no way of knowing when a complete message has been received. In the absence of such knowledge it is common practice to use two memories. The first memory is used to assemble one complete message at a time. The second memory is used to operate as a FIFO system in which the unit of storage is a message. Such an arrangement usually requires high speed processing circuitry which then becomes a bottleneck limiting throughput. Further, because two memories are used, circuitry is necessarily dupl icat ed . Summary of the Invention
In accordance with the illustrative embodiment of the present invention there is disclosed a first-in, first-out memory system comprising a controller for storing, seriatim, a plurality of information words in a memory device. Only when a complete message has been stored will the controller allow the aforesaid information words to be read-out in the first-in, first-out sequence. More particularly, the storage device is a random access memory (RAM) with a capacity for storing N information words, where N is an integer. Such a memory is known as a cyclic memory. The controller comprises three pointer registers: W, R, and L. The W and R pointer registers hold addresses of the RAM locations previously accessed. The L pointer register holds the address of the RAM location where a complete message ends.
When an information word is to be entered in the RAM for storage, the W pointer register is incremented to W+1 modulo N and the address W+1 is compared with the address in the R pointer register. If the values of the two addresses are not equal, the information word is entered in the storage location in the RAM whose address is W+1. Thereafter, the address in the W pointer register is changed inside the controller to W+1.
When an information word is to be read from the RAM, the address in the R pointer register is compared with the address in the L pointer register. If the values of the two addresses are not equal, the address in the R pointer register is incremented by one to R+l modulo N. The information word, addressed by the R pointer, namely, the location in the RAM addressed by R+1, is read from the RAM. Thereafter, the address in the R pointer register inside the controller is updated to indicate the new address R+1.
When a complete message has been entered in the RAM, the address of the location where the message ends is entered in the L pointer register. That is, the address in the W pointer register is copied into the L pointer register, thereby effectively moving, the L pointer to address the location in the RAM where the complete message ends .
When an error in transmission is detected during the entry of information words in the memory and part way through a message, the previously entered partial message must be discarded. This result is achieved by copying the address in the L pointer register into the W pointer register.
An advantage of the present invention is the use of a single random access memory for the first-in, first-out queue and a single control circuit to implement the necessary queue management. Furthermore, very high speed components are not required and there no longer arises a processing bottleneck. Additionally, because only
complete messages are read-out, synchronization problems are avoided.
Brief Description of the Drawings
FIG. 1 shows a block diagram of a first-in, first-out queue for storing information words and for reading out the words only when a complete message has been stored;
FIG. 2 shows a block diagram of a message received by the first-in, first-out queue; and FIG. 3 shows a diagram illustrating the use of the memory in FIG. 1. Detailed Description
Referring to FIG. 1, there is shown a random access memory (RAM) 12 for storing information received over a transmission line 11. The information may be transmitted as a message comprising a plurality of information words. One such message is shown in FIG. 2. The format of a message may vary depending on the particular use. The message in FIG. 2 comprises a header 32, data 34, and end of message flag 36. The information words are stored in RAM 12, in FIG. 1, in the order in which they are received over line 11. After all the information words in a complete message have been entered in RAM 12, they are available for retrieval by a utilization means 14, such as a digital computer, a switching machine, and the like. When the message is retrieved from RAM 12, the first information word to be entered therein is read out first. That is, a first-in, first-out queue is realized using a random access memory, RAM 12.
As messages of data arrive, they are entered simultaneously into error detector 16 and buffer 18. If there exists no error resulting from transmission, lead 17 is enabled. Simultaneously, enabling input control and logic circuit 20 receives information about the beginning and end of messages from buffer 18 to be described hereinbelow.
The use of RAM 12 may be explained by referring to FIG. 3. RAM 12 may be thought of as a circular storage device where information words, comprising a variable number of bits may be stored. Thus, if the number of information words that may be stored in RAM 12 is denoted by N, the information words are entered sequentially in locations 0,1,2 ... N-1. After the location with address N-1 has been filled, the next location to be filled will have address 0. That is, successive locations can be addressed using modulo N arithmetic.
A pointer R addresses the location of the last word that was read from RAM 12. When a word is to be read out from RAM 12, pointer R is incremented by 1 modulo N and the contents of that word at location R+1 is read. Likewise, a pointer W addresses the location where a word of information was last entered. Thus, when a word of information is to be entered into RAM 12, pointer W is incremented by 1 and the word is entered in the location whose address is W+l modulo N. The locations between R+1 modulo N and W represent the words of information available to be read from RAM 12. According to the present invention, messages comprising a plurality of words of information are entered in RAM 12 when received but will not be available for being read from RAM 12 until all information in a message is entered therein. This is achieved by the use of a third pointer L .
When a complete message is received, the end of message flag 36, FIG. 2, carrying a special code is interpreted in the input control circuit 20, FIG. 1. This condition is transmitted over bus 21 to a programmable logic array (PLA) or a read only memory (ROM) 22. Referring to FIG. 3 again, when a complete message is received, the contents of pointer W is copied into pointer L. That is, pointer L addresses the location of the last information word in the complete message.
Before a word is read from RAM 12, pointers R and L are compared. If they point to the same location, the queue does not have a complete message, and a word cannot be read from RAM 12. If pointers R and L address different locations, pointer R is incremented by 1 and the contents of location R+1 modulo N is read from RAM 12.
Because the memory is circular and is a random access memory, it is necessary to prevent destruction of valid data by insuring that pointer W will not be advanced beyond pointer R. According to the present invention, pointer W is maintained so that when incremented by 1, W+1 modulo N will never be equal to pointer R. That is, there is provided a cushion of one word location.
Referring again to FIG. 1, there is shown a pointer memory 40 which holds three addresses: pointers W, L, and R. In the illustrative embodiment, each pointer is twelve bits long. Pointer register 42 is large enough to hold a single pointer. Adder 44 is designed to add either zero or one modulo N to its input value, namely, an address indicated by pointer W, L or R. RAM 12 has one word location for every information word from buffer 18. Further RAM 12 has as many locations as can be addressed by a single pointer. Thus, in the illustrative embodiment, because each pointer has twelve bits, each pointer can address 4,096 words (212) in RAM 12, that is,
N = 4,096, in this illustration. Register 10 is wide enough to store a single word of information read from
RAM 12. Comparator 46 compares the values of two addresses and produces an output. If the two addresses are equal, the output from comparator 46 is one, otherwise, the output therefrom is zero. Flip-flop 48 stores the output from comparator 46 and that output is made available over lead 49 to ROM 22.
The pointers W, R and L, as stated hereinbefore, address locations in RAM 12 so that information may be written therein or read therefrom. Pointers W and R move
cyclicly through RAM 12, one location at a time. As stated hereinbefore, RAM 12 may be conceptualized as a circular buffer having three pointers, W, R and L.
Pointer memory 40 is addressed by leads 25. The address, comprising two bits, indicates the pointer W, R, or L. Depending on the pointer location addressed, a pointer appears at the Q port and on bus 41. When a pointer, which appears on bus 51, is to be entered in pointer memory 40, the location is indicated by address leads 25 and the control lead 27 is enabled. The pointer on bus 41 appears at the D port of pointer register 42 and at the D port of comparator 46.
The pointer on bus 41 at the D port is copied into pointer register 42 by enabling the control lead 29. The contents of pointer register 42 is always present at its Q port and on bus 43.
As stated hereinabove, adder 44 adds either zero or one modulo N to its input. The pointer, from pointer register 42, appears at the D port of adder 44 and the quantity, either a zero or a one, appearing on the input lead 31, are added. The resulting sum, pointer +0 (or 1) modulo N, appears at the output port Q and on bus 45. Bus 45 branches into three separate buses: 51, to the D port of pointer memory 40; 53, to the address port A of the RAM 12; and 55, to the D2 port of comparator 46.
Words which are to be entered in RAM 12 appear at the D port thereof. The pointer indicating the address of the memory cell into which the word is to be entered appears at the A port thereof. When the control lead 33 is enabled, the word at the D port is entered into the memory cell of RAM 12 addressed by the pointer on bus 53.
Words which are to be read from RAM 12 are addressed by the pointer on bus 53 again through the A port. Thereafter, the words appear at the Q port of
RAM 12 and via bus 15 at the D port of register 10. When control lead 35 is enabled, the word which was read from RAM 12 is entered into register 10 and appears at the 0. port thereof and on bus 13. The input values at the D1 and D2 ports of comparator 46 are compared. If the input values are equal, the output is one; otherwise, the output is zero. The output from comparator 46 is transmitted via bus 47 to the D port of flip-flop 48. When control lead 37 is enabled, the output from comparator 46 is entered in flip-flop 48. The value of flip-flop 48 is continuously present on lead 49 to the ROM 22.
ROM 22 and control register 24 together form a control circuit 26. When utilization means 14 is ready to receive a message, a signal is transmitted over bus 61 to output control and logic circuit 60. Thereafter, output control circuit 60 issues a read command over lead 63 to the ROM 22 . D e pe nd ing on the s t a tu s o f the e i gh t leads 21, 23, 49 and 63 at the input to ROM 22, an instruction is read therefrom and is transferred to control register 24 simultaneously with a clock pulse on lead 65. The contents of register 24, namely the instructions from ROM 22, define the state of the device during the next clock period. Thus, the register 24 holds the current values for the twelve leads 23, 25, 27, 29, 31, 33, 35 and 37. The leads 23 carry a number, comprising four bits, which is fed back as an input to PLA 22 in order that the following state may be generated. The next state as defined by the next instruction from ROM 22 depends upon both the previous state identified by the number on leads 23 and the new inputs on control leads 21, 49 and 63. Reading Information from the FIFO Queue
In response to a command from utilization means 14, during a first clock period, control circuit 26 causes the address of the R pointer to be transmitted over leads 25 to the pointer memory 40. Simultaneously
therewith, control lead 29 is enabled thereby causing the aforesaid R pointer to be entered in pointer register 42. In a second clock period, the lead 31 carries the value zero so that the R pointer is passed intact through adder 44 and appears at the D2 port of comparator 46. During the same second clock period, leads 25 carry the address of the L pointer to pointer register 40 and the
L pointer appears at the D1 port of comparator 46 The output from comparator 46 is entered in flip-flop 48 by enabling lead 37. If the queue is empty or does not have a complete message, pointers L and R are equal and the value on lead 49 is one. If the queue, however, has either a partially read message or at least one complete message, the value on lead 49 is zero. During the third clock period, the value on lead 31 is a one and the adder 44 is allowed to settle down. The value of the output, R+1, from adder 44 appears on bus 53 and points to the word to be read from RAM 12. During the fourth clock period, if the value on lead 49 was zero during the second clock period, the lead 35 is enabled and a word, which was read from RAM 12 during the third clock period, is entered into register 10. The word is continuously available at the Q port of register 10 and on bus 13. Lead 35 also carries an input signal to the output control logic circuit 60 where it signifies when one word has been read.
During the aforesaid third clock period the incremented R pointer, namely R+1, appears on bus 51 at the D port of pointer memory 40. During the fourth clock period, leads 25 carry the address of the R pointer and lead 27 is enabled, thereby causing the incremented R pointer, R+1, on bus 51 to be entered as the new R pointer in pointer memory 40. Writing Information into the FIFO Queue In response to a word being received on line 11, input control circuit 20 transmits this status over leads 21 to control circuit 26. Thereafter, during the
first clock period, leads 25 carry the address of the W pointer in pointer memory 40 and the W pointer thus addressed is entered in pointer register 42 by enabling lead 29. During the second clock period, the lead 31 carries the value one so that the output from adder 44 is W+1 which appears at the D2 port of comparator 46. Simultaneously, the leads 25 carry the address of the R pointer in pointer memory 40 and the R pointer thus addressed appears at the D1 port of comparator 46. During the third clock period, the value of the signal on the lead 31 remains at one and the output from comparator 46 is entered in flip-flop 48 by enabling lead 37. If the output from comparator 46, namely, the contents of flip-flop 48, is zero, it means the R pointer and W+1 are not equal and the word at the D port of RAM 12 may be entered therein.
Thus, during the fourth clock period, if the R pointer and W+l are not equal, the word at the D port of RAM 12 is entered in the location addressed by W+1 at the A port thereof by enabling lead 33. Lead 33 also carries an input signal to the input control circuit 20 and signifies when a word from buffer 18 has been entered in RAM 12.
During the same fourth clock period, leads 25 carry the address of the W pointer in pointer memory 40 and lead 27 is enabled so that the incremented value, W+1, of the W pointer on bus 51 may be entered in the pointer memory 40. Signalling the Entry of a Complete Message When a complete message as been received, as indicated by the end of message flag 36, of FIG. 2, leads 21, in FIG. 1, carry this status to the control circuit 26. In response thereto, the L pointer is updated. This updating requires two clock periods. During the first clock period, leads 25 carry the address of the W pointer in pointer memory 40. The lead 29 is enabled and the W pointer is copied into the
pointer register 42. During the second clock period lead 31 carries the value zero. Thus, the W pointer appears on bus 51. The leads 25 carry the address of the L pointer in pointer memory 40. Lead 27 is enabled thereby copying the value of the W pointer on bus 51 into the L pointer. Resetting the FIFO Queue
The FIFO queue is reset, or initialized, to render the queue empty by copying the value of the R pointer into the L and W pointer locations in pointer memory 40. This process requires three clock periods.
During the first clock period, the leads 25 carry the address of the R pointer in pointer memory 40 and the R pointer is entered in pointer register 42 by enabling lead 29.
During the second clock period, the value on lead 31 is zero so that the R pointer appears on bus 51. The leads 25 carry the address of the L pointer and by enabling lead 27 the value of the R pointer is copied into the L pointer location in pointer memory 40.
Likewise, during the third clock period, the value on lead 31 remains at zero so that the R pointer continues to appear on bus 5l. The leads 25 carry the address of the W pointer and by enabling lead 27 the value of the R pointer is copied into the W pointer location. Contention Resolution
If both write command leads 21 and read command lead 63 are simultaneously enabled, the control circuit 26 gives priority to the write command leads 21, even if the FIFO queue is full and the operation cannot be completed. The next operation should be the read command on lead 63. Input Control Process
As stated hereinabove, when an information word is received it is placed in buffer 18 and in error detector 16. With the complete entry of each word in buffer 18, input control circuit 20 transmits a command over leads 21 to ROM 22 thereby causing the information
word in buffer 18 to be transferred therefrom and entered into RAM 12.
As stated hereinabove, after each information word is entered in error detector 16, the presence or absence of a transmission error is detected therein. If no transmission error had been detected, lead 17 is enabled. Meanwhile, each word entered in buffer 18 is compared with an end of message flag. When an end of message is detected, that condition is transmitted over bus 19 to input control circuit 20.
When lead 17 is enabled and an end of message signal is received over bus 19 from buffer 18, the input control circuit 20 transmits a command over leads 21 to ROM 22. In response thereto, the address in the W pointer is copied into the L pointer, thereby signifying the entry of a complete message in RAM 12. Thereafter, this me s s ag e may be read from RAM 12.
Should an error in transmission be detected in error detector 16, however, lead 17 will not be enabled. In the absence of a signal on lead 17, a different command is transmitted from input control circuit 20 over leads 21 to ROM 22. In response thereto, the address in the L pointer is copied into the W pointer, thereby returning the W pointer to an initial position. As a result, no erroneous information words are retained in RAM 12.
Claims
1. A first-in, first-out memory system comprising means for storing a message comprising a plurality of information words, and means for controlling
1) the entry of said information words in said storage means, and
2) the reading of said information words from said storage means in the same order in which said information words were entered therein, only after all said information words of said message have been stored.
2. The first-in, first-out memory system according to claim 1 wherein said memory is a random access memory.
3. The first-in, first-out memory system according to claim 1 wherein said means for controlling the entry of said information words comprises a first pointer for addressing the location in said storage means where said information word is to be stored.
4. The first-in, first-out memory system according to claim 1 wherein said means for controlling the reading of said information words comprises a second pointer for addressing the location in said storage means from where said information word is to be read.
5. The first-in, first-out memory system according to claim 4 wherein said means for controlling the entry of said information words and the reading of said information words further comprises a third pointer for addressing the location in said storage means where the last of said information words in said complete message is stored.
6. The first-in, first-out memory system according to claim 5 further comprising means for discarding said message or a part thereof before one of said information words is read.
7. A first-in, first-out queue comprising a random access memory for storing information words, and a controller for permitting the read-out of said words after a complete message comprising a plurality of said words has been stored in said random access memory, and said controller comprises a programmable logic array (PLA) or read only memory (ROM) and a register.
8. The first-in, first-out queue according to claim 7 wherein said controller further comprises a pointer memory for storing three pointers.
9. The first-in, first-out queue acording to claim 9 wherein said controller further comprises a pointer register for storing any one of said pointer, an adder for either adding to said pointer from said pointer register the number one, thereby incrementing the value of said pointer from said pointer register, or adding to said pointer from said pointer register the number zero, a comparator having two input signals thereto, a first input signal being the value of said pointer read from said pointer memory and a second input signal being an output signal from said adder, and means for storing the resulting output signal from said comparator.
10. A first-in, first-out memory system for multiword messages comprising an addressable cyclic memory a W pointer register for writing words into said memory at the address of the W pointer, an R pointer register for reading words from said memory at the address of the R pointer, an L pointer register for identifying the last word of a multiword message, means for incrementing the W pointer register, and comparing the W pointer register to the R pointer
register before storing a new message word and only if the incremented W pointer and the R pointer are not the same, means for comparing the contents of the R pointer register with the contents of the L pointer register, and incrementing the R pointer register and reading the memory word addressed by the R pointer register only if the R and L pointers are not the same, means responsive to an end of message signal for copying the contents of the W pointer register into the L pointer register, and means responsive to an error in a new memory word for copying the contents of the L pointer register into the W pointer register.
Priority Applications (1)
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DE8383900887T DE3371428D1 (en) | 1982-08-13 | 1983-02-15 | First-in, first-out (fifo) memory configuration for queue storage |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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US06/407,877 US4507760A (en) | 1982-08-13 | 1982-08-13 | First-in, first-out (FIFO) memory configuration for queue storage |
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WO1984000835A1 true WO1984000835A1 (en) | 1984-03-01 |
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PCT/US1983/000190 WO1984000835A1 (en) | 1982-08-13 | 1983-02-15 | First-in, first-out (fifo) memory configuration for queue storage |
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US (1) | US4507760A (en) |
EP (1) | EP0118446B1 (en) |
JP (1) | JPS59501435A (en) |
CA (1) | CA1191277A (en) |
DE (1) | DE3371428D1 (en) |
WO (1) | WO1984000835A1 (en) |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1986003608A1 (en) * | 1984-12-06 | 1986-06-19 | American Telephone & Telegraph Company | Queue administration method and apparatus |
EP0218073A2 (en) * | 1985-10-11 | 1987-04-15 | International Business Machines Corporation | Voice buffer management |
EP0241129A2 (en) * | 1986-03-06 | 1987-10-14 | Advanced Micro Devices, Inc. | Addressing arrangement for a RAM buffer controller |
EP0272869A2 (en) * | 1986-12-19 | 1988-06-29 | Fujitsu Limited | Dual port type semiconductor memory device realizing a high speed read operation |
EP0273083A1 (en) * | 1986-12-30 | 1988-07-06 | International Business Machines Corporation | Non-locking queueing mechanism |
EP0312239A2 (en) * | 1987-10-14 | 1989-04-19 | Nortel Networks Corporation | Message fifo buffer controller |
WO1991013397A1 (en) * | 1990-02-28 | 1991-09-05 | Sf2 Corporation | A method and apparatus for transferring data through a staging memory |
US5133062A (en) * | 1986-03-06 | 1992-07-21 | Advanced Micro Devices, Inc. | RAM buffer controller for providing simulated first-in-first-out (FIFO) buffers in a random access memory |
US5315708A (en) * | 1990-02-28 | 1994-05-24 | Micro Technology, Inc. | Method and apparatus for transferring data through a staging memory |
GB2370661A (en) * | 2000-12-29 | 2002-07-03 | Mitel Semiconductor Ltd | Data queues |
GB2382899A (en) * | 2000-12-29 | 2003-06-11 | Zarlink Semiconductor Ltd | Data queue system |
US6775245B1 (en) | 1998-10-27 | 2004-08-10 | Seiko Epson Corporation | Data transfer control device and electronic equipment |
Families Citing this family (92)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2142797B (en) * | 1983-05-24 | 1987-06-24 | Canon Kk | Apparatus enabling efficient utilization of a memory for storing image data of plural pages |
US4599692A (en) * | 1984-01-16 | 1986-07-08 | Itt Corporation | Probabilistic learning element employing context drive searching |
US4593367A (en) * | 1984-01-16 | 1986-06-03 | Itt Corporation | Probabilistic learning element |
US4620286A (en) * | 1984-01-16 | 1986-10-28 | Itt Corporation | Probabilistic learning element |
JPH07118187B2 (en) * | 1985-05-27 | 1995-12-18 | 松下電器産業株式会社 | First-in first-out storage |
US4803654A (en) * | 1985-06-20 | 1989-02-07 | General Datacomm Industries, Inc. | Circular first-in, first out buffer system for generating input and output addresses for read/write memory independently |
US4751675A (en) * | 1985-08-19 | 1988-06-14 | American Telephone And Telegraph Company, At&T Bell Laboratories | Memory access circuit with pointer shifting network |
US4942515A (en) * | 1986-03-31 | 1990-07-17 | Wang Laboratories, Inc. | Serial communications controller with FIFO register for storing supplemental data and counter for counting number of words within each transferred frame |
US5151999A (en) * | 1986-03-31 | 1992-09-29 | Wang Laboratories, Inc. | Serial communications controller for transfer of successive data frames with storage of supplemental data and word counts |
US4833651A (en) * | 1986-07-24 | 1989-05-23 | National Semiconductor Corporation | High-speed, asynchronous, No-Fall-Through, first-in-first out memory with high data integrity |
US4847812A (en) * | 1986-09-18 | 1989-07-11 | Advanced Micro Devices | FIFO memory device including circuit for generating flag signals |
US4995005A (en) * | 1986-09-18 | 1991-02-19 | Advanced Micro Devices, Inc. | Memory device which can function as two separate memories or a single memory |
US4773071A (en) * | 1986-10-02 | 1988-09-20 | Grumman Aerospace Corporation | Memory for storing response patterns in an automatic testing instrument |
US4839866A (en) * | 1987-05-29 | 1989-06-13 | Texas Instruments Incorporated | Cascadable first-in, first-out memory |
US4878197A (en) * | 1987-08-17 | 1989-10-31 | Control Data Corporation | Data communication apparatus |
US4873671A (en) * | 1988-01-28 | 1989-10-10 | National Semiconductor Corporation | Sequential read access of serial memories with a user defined starting address |
JPH02159624A (en) * | 1988-12-13 | 1990-06-19 | Nec Corp | First-in first-out register device |
US5027330A (en) * | 1988-12-30 | 1991-06-25 | At&T Bell Laboratories | FIFO memory arrangement including a memory location fill indication |
US4953157A (en) * | 1989-04-19 | 1990-08-28 | American Telephone And Telegraph Company | Programmable data packet buffer prioritization arrangement |
US5016221A (en) * | 1989-12-01 | 1991-05-14 | National Semiconductor Corporation | First-in, first-out (FIFO) memory with variable commit point |
US5459839A (en) * | 1991-09-05 | 1995-10-17 | International Business Machines Corporation | System and method for managing queue read and write pointers |
DE69124606T2 (en) * | 1991-10-17 | 1997-08-21 | Ibm | Adaptive FIFO memory control |
US5504913A (en) * | 1992-05-14 | 1996-04-02 | Apple Computer, Inc. | Queue memory with self-handling addressing and underflow |
US5450544A (en) * | 1992-06-19 | 1995-09-12 | Intel Corporation | Method and apparatus for data buffering and queue management of digital motion video signals |
US6009244A (en) * | 1993-02-23 | 1999-12-28 | Canon Kabushiki Kaisha | Image communication apparatus handling concurrent storing and reading requests |
US5509006A (en) * | 1994-04-18 | 1996-04-16 | Cisco Systems Incorporated | Apparatus and method for switching packets using tree memory |
US5519704A (en) * | 1994-04-21 | 1996-05-21 | Cisco Systems, Inc. | Reliable transport protocol for internetwork routing |
US5471487A (en) * | 1994-04-26 | 1995-11-28 | Unisys Corporation | Stack read/write counter through checking |
US5621896A (en) * | 1994-06-01 | 1997-04-15 | Motorola, Inc. | Data processor with unified store queue permitting hit under miss memory accesses |
US5687316A (en) * | 1994-07-29 | 1997-11-11 | International Business Machines Corporation | Communication apparatus and methods having P-MAC, I-MAC engines and buffer bypass for simultaneously transmitting multimedia and packet data |
US5867666A (en) * | 1994-12-29 | 1999-02-02 | Cisco Systems, Inc. | Virtual interfaces with dynamic binding |
US5797005A (en) * | 1994-12-30 | 1998-08-18 | International Business Machines Corporation | Shared queue structure for data integrity |
US5519701A (en) * | 1995-03-29 | 1996-05-21 | International Business Machines Corporation | Architecture for high performance management of multiple circular FIFO storage means |
WO1997003444A1 (en) * | 1995-07-10 | 1997-01-30 | Xilinx, Inc. | System comprising field programmable gate array and intelligent memory |
US6097718A (en) | 1996-01-02 | 2000-08-01 | Cisco Technology, Inc. | Snapshot routing with route aging |
US6147996A (en) | 1995-08-04 | 2000-11-14 | Cisco Technology, Inc. | Pipelined multiple issue packet switch |
DE69525531T2 (en) * | 1995-09-04 | 2002-07-04 | Hewlett Packard Co | Data processing system with a ring-shaped queue in a page memory |
US6182224B1 (en) | 1995-09-29 | 2001-01-30 | Cisco Systems, Inc. | Enhanced network services using a subnetwork of communicating processors |
US6917966B1 (en) | 1995-09-29 | 2005-07-12 | Cisco Technology, Inc. | Enhanced network services using a subnetwork of communicating processors |
US7246148B1 (en) | 1995-09-29 | 2007-07-17 | Cisco Technology, Inc. | Enhanced network services using a subnetwork of communicating processors |
US6091725A (en) * | 1995-12-29 | 2000-07-18 | Cisco Systems, Inc. | Method for traffic management, traffic prioritization, access control, and packet forwarding in a datagram computer network |
US6035105A (en) | 1996-01-02 | 2000-03-07 | Cisco Technology, Inc. | Multiple VLAN architecture system |
GB9606928D0 (en) | 1996-04-02 | 1996-06-05 | Memory Corp Plc | Memory devices |
GB9609833D0 (en) * | 1996-05-10 | 1996-07-17 | Memory Corp Plc | Memory device |
US6243667B1 (en) | 1996-05-28 | 2001-06-05 | Cisco Systems, Inc. | Network flow switching and flow data export |
US6308148B1 (en) | 1996-05-28 | 2001-10-23 | Cisco Technology, Inc. | Network flow data export |
US6212182B1 (en) | 1996-06-27 | 2001-04-03 | Cisco Technology, Inc. | Combined unicast and multicast scheduling |
US6434120B1 (en) * | 1998-08-25 | 2002-08-13 | Cisco Technology, Inc. | Autosensing LMI protocols in frame relay networks |
US5822752A (en) * | 1996-07-15 | 1998-10-13 | International Business Machines Corporation | Method and apparatus for fast parallel determination of queue entries |
JP3268980B2 (en) * | 1996-09-02 | 2002-03-25 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Data buffering system |
US6304546B1 (en) | 1996-12-19 | 2001-10-16 | Cisco Technology, Inc. | End-to-end bidirectional keep-alive using virtual circuits |
US6122272A (en) * | 1997-05-23 | 2000-09-19 | Cisco Technology, Inc. | Call size feedback on PNNI operation |
US6356530B1 (en) | 1997-05-23 | 2002-03-12 | Cisco Technology, Inc. | Next hop selection in ATM networks |
US6862284B1 (en) | 1997-06-17 | 2005-03-01 | Cisco Technology, Inc. | Format for automatic generation of unique ATM addresses used for PNNI |
US6078590A (en) * | 1997-07-14 | 2000-06-20 | Cisco Technology, Inc. | Hierarchical routing knowledge for multicast packet routing |
US6157641A (en) * | 1997-08-22 | 2000-12-05 | Cisco Technology, Inc. | Multiprotocol packet recognition and switching |
US6212183B1 (en) | 1997-08-22 | 2001-04-03 | Cisco Technology, Inc. | Multiple parallel packet routing lookup |
US6512766B2 (en) | 1997-08-22 | 2003-01-28 | Cisco Systems, Inc. | Enhanced internet packet routing lookup |
US6343072B1 (en) | 1997-10-01 | 2002-01-29 | Cisco Technology, Inc. | Single-chip architecture for shared-memory router |
US7570583B2 (en) * | 1997-12-05 | 2009-08-04 | Cisco Technology, Inc. | Extending SONET/SDH automatic protection switching |
US6111877A (en) | 1997-12-31 | 2000-08-29 | Cisco Technology, Inc. | Load sharing across flows |
US6424649B1 (en) | 1997-12-31 | 2002-07-23 | Cisco Technology, Inc. | Synchronous pipelined switch using serial transmission |
US6853638B2 (en) * | 1998-04-01 | 2005-02-08 | Cisco Technology, Inc. | Route/service processor scalability via flow-based distribution of traffic |
US6920112B1 (en) | 1998-06-29 | 2005-07-19 | Cisco Technology, Inc. | Sampling packets for network monitoring |
US6370121B1 (en) | 1998-06-29 | 2002-04-09 | Cisco Technology, Inc. | Method and system for shortcut trunking of LAN bridges |
US6377577B1 (en) | 1998-06-30 | 2002-04-23 | Cisco Technology, Inc. | Access control list processing in hardware |
US6182147B1 (en) | 1998-07-31 | 2001-01-30 | Cisco Technology, Inc. | Multicast group routing using unidirectional links |
US6308219B1 (en) | 1998-07-31 | 2001-10-23 | Cisco Technology, Inc. | Routing table lookup implemented using M-trie having nodes duplicated in multiple memory banks |
US6389506B1 (en) | 1998-08-07 | 2002-05-14 | Cisco Technology, Inc. | Block mask ternary cam |
US6101115A (en) * | 1998-08-07 | 2000-08-08 | Cisco Technology, Inc. | CAM match line precharge |
DE19850650C2 (en) * | 1998-11-03 | 2000-09-07 | Texas Instruments Deutschland | Method of transferring data |
US6771642B1 (en) | 1999-01-08 | 2004-08-03 | Cisco Technology, Inc. | Method and apparatus for scheduling packets in a packet switch |
US7065762B1 (en) | 1999-03-22 | 2006-06-20 | Cisco Technology, Inc. | Method, apparatus and computer program product for borrowed-virtual-time scheduling |
US6757791B1 (en) | 1999-03-30 | 2004-06-29 | Cisco Technology, Inc. | Method and apparatus for reordering packet data units in storage queues for reading and writing memory |
US6603772B1 (en) | 1999-03-31 | 2003-08-05 | Cisco Technology, Inc. | Multicast routing with multicast virtual output queues and shortest queue first allocation |
US6760331B1 (en) | 1999-03-31 | 2004-07-06 | Cisco Technology, Inc. | Multicast routing with nearest queue first allocation and dynamic and static vector quantization |
EP1050812A1 (en) * | 1999-05-03 | 2000-11-08 | STMicroelectronics SA | Storage of data in a computer memory |
US6789144B1 (en) * | 1999-05-27 | 2004-09-07 | Advanced Micro Devices, Inc. | Apparatus and method in a network interface device for determining data availability in a random access memory |
US6484224B1 (en) | 1999-11-29 | 2002-11-19 | Cisco Technology Inc. | Multi-interface symmetric multiprocessor |
US6977895B1 (en) * | 2000-03-23 | 2005-12-20 | Cisco Technology, Inc. | Apparatus and method for rate-based polling of input interface queues in networking devices |
US6732223B1 (en) | 2000-04-03 | 2004-05-04 | Micron Technology, Inc. | Method and apparatus for address FIFO for high-bandwidth command/address busses in digital storage system |
US6735207B1 (en) | 2000-06-13 | 2004-05-11 | Cisco Technology, Inc. | Apparatus and method for reducing queuing memory access cycles using a distributed queue structure |
US20020184381A1 (en) * | 2001-05-30 | 2002-12-05 | Celox Networks, Inc. | Method and apparatus for dynamically controlling data flow on a bi-directional data bus |
US7076543B1 (en) | 2002-02-13 | 2006-07-11 | Cisco Technology, Inc. | Method and apparatus for collecting, aggregating and monitoring network management information |
WO2004040579A1 (en) * | 2002-08-22 | 2004-05-13 | Thomson Licensing S.A. | Smart card write-only register |
US6845053B2 (en) * | 2002-11-15 | 2005-01-18 | Micron Technology, Inc. | Power throughput adjustment in flash memory |
US20070260777A1 (en) * | 2003-11-25 | 2007-11-08 | Timpe Barrie R | Queues for information processing and methods thereof |
US7694061B2 (en) * | 2004-09-08 | 2010-04-06 | Fisher-Rosemount Systems, Inc. | Discarding a partially received message from a data queue |
JP4451837B2 (en) * | 2004-12-10 | 2010-04-14 | 富士通株式会社 | Data transfer apparatus and data transfer method |
US20060129714A1 (en) * | 2004-12-10 | 2006-06-15 | Fujitsu Limited | Method and apparatus for transferring data |
US20080049036A1 (en) * | 2006-08-24 | 2008-02-28 | Mediatek Inc. | Multimedia Playback System, FIFO Memory System, and Method for Storing Multimedia Data |
US8229596B2 (en) * | 2008-05-16 | 2012-07-24 | Hewlett-Packard Development Company, L.P. | Systems and methods to interface diverse climate controllers and cooling devices |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2907004A (en) * | 1954-10-29 | 1959-09-29 | Rca Corp | Serial memory |
US3553691A (en) * | 1969-08-14 | 1971-01-05 | James W Lassiter | Long range position determination system |
US3633173A (en) * | 1970-03-16 | 1972-01-04 | Hughes Aircraft Co | Digital scan converter |
US3818461A (en) * | 1972-04-10 | 1974-06-18 | Litton Systems Inc | Buffer memory system |
FR2260141A1 (en) * | 1974-02-01 | 1975-08-29 | Honeywell Bull Soc Ind | Data transfer control for data processor - is used between periodic and non-periodic units employing buffer memory |
US3979733A (en) * | 1975-05-09 | 1976-09-07 | Bell Telephone Laboratories, Incorporated | Digital data communications system packet switch |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3553651A (en) * | 1967-12-06 | 1971-01-05 | Singer General Precision | Memory storage system |
US4163291A (en) * | 1975-10-15 | 1979-07-31 | Tokyo Shibaura Electric Co., Ltd. | Input-output control circuit for FIFO memory |
US4151609A (en) * | 1977-10-11 | 1979-04-24 | Monolithic Memories, Inc. | First in first out (FIFO) memory |
NL7713706A (en) * | 1977-12-12 | 1979-06-14 | Philips Nv | INFORMATION BUFFER MEMORY OF THE "FIRST-IN, FIRST-OUT" TYPE WITH A VARIABLE INPUT AND A VARIABLE OUTPUT. |
-
1982
- 1982-08-13 US US06/407,877 patent/US4507760A/en not_active Expired - Lifetime
-
1983
- 1983-02-15 WO PCT/US1983/000190 patent/WO1984000835A1/en active IP Right Grant
- 1983-02-15 JP JP58501022A patent/JPS59501435A/en active Granted
- 1983-02-15 EP EP83900887A patent/EP0118446B1/en not_active Expired
- 1983-02-15 DE DE8383900887T patent/DE3371428D1/en not_active Expired
- 1983-08-08 CA CA000434061A patent/CA1191277A/en not_active Expired
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2907004A (en) * | 1954-10-29 | 1959-09-29 | Rca Corp | Serial memory |
US3553691A (en) * | 1969-08-14 | 1971-01-05 | James W Lassiter | Long range position determination system |
US3633173A (en) * | 1970-03-16 | 1972-01-04 | Hughes Aircraft Co | Digital scan converter |
US3818461A (en) * | 1972-04-10 | 1974-06-18 | Litton Systems Inc | Buffer memory system |
FR2260141A1 (en) * | 1974-02-01 | 1975-08-29 | Honeywell Bull Soc Ind | Data transfer control for data processor - is used between periodic and non-periodic units employing buffer memory |
US3979733A (en) * | 1975-05-09 | 1976-09-07 | Bell Telephone Laboratories, Incorporated | Digital data communications system packet switch |
Non-Patent Citations (2)
Title |
---|
IBM Technical Disclosure Bulletin, Vol. 20, No. 8, published January 1978 (New York, US) CHAPMAN et al.: "Data Management in a Circular Buffer", pages 3309-3310 * |
IBM Technical Disclosure Bulletin, Vol. 24, No. 3, published August 1981 (New York, US) CARY et al.: "Data Buffer Management", pages 1502-1503 * |
Cited By (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1986003608A1 (en) * | 1984-12-06 | 1986-06-19 | American Telephone & Telegraph Company | Queue administration method and apparatus |
US4682284A (en) * | 1984-12-06 | 1987-07-21 | American Telephone & Telegraph Co., At&T Bell Lab. | Queue administration method and apparatus |
EP0218073A2 (en) * | 1985-10-11 | 1987-04-15 | International Business Machines Corporation | Voice buffer management |
EP0218073A3 (en) * | 1985-10-11 | 1988-02-24 | International Business Machines Corporation | Voice buffer management |
US4841574A (en) * | 1985-10-11 | 1989-06-20 | International Business Machines Corporation | Voice buffer management |
EP0241129A2 (en) * | 1986-03-06 | 1987-10-14 | Advanced Micro Devices, Inc. | Addressing arrangement for a RAM buffer controller |
US5133062A (en) * | 1986-03-06 | 1992-07-21 | Advanced Micro Devices, Inc. | RAM buffer controller for providing simulated first-in-first-out (FIFO) buffers in a random access memory |
EP0241129A3 (en) * | 1986-03-06 | 1990-05-30 | Advanced Micro Devices, Inc. | Addressing arrangement for a ram buffer controller |
EP0272869A2 (en) * | 1986-12-19 | 1988-06-29 | Fujitsu Limited | Dual port type semiconductor memory device realizing a high speed read operation |
EP0272869A3 (en) * | 1986-12-19 | 1990-05-23 | Fujitsu Limited | Dual port type semiconductor memory device realizing a high speed read operation |
EP0273083A1 (en) * | 1986-12-30 | 1988-07-06 | International Business Machines Corporation | Non-locking queueing mechanism |
US4980852A (en) * | 1986-12-30 | 1990-12-25 | International Business Machines Corporation | Non-locking queueing mechanism for enabling a receiver device to read from a queue without access synchronization with a sending device |
EP0312239A3 (en) * | 1987-10-14 | 1991-02-13 | Nortel Networks Corporation | Message fifo buffer controller |
EP0312239A2 (en) * | 1987-10-14 | 1989-04-19 | Nortel Networks Corporation | Message fifo buffer controller |
WO1991013397A1 (en) * | 1990-02-28 | 1991-09-05 | Sf2 Corporation | A method and apparatus for transferring data through a staging memory |
US5315708A (en) * | 1990-02-28 | 1994-05-24 | Micro Technology, Inc. | Method and apparatus for transferring data through a staging memory |
US6775245B1 (en) | 1998-10-27 | 2004-08-10 | Seiko Epson Corporation | Data transfer control device and electronic equipment |
GB2370661A (en) * | 2000-12-29 | 2002-07-03 | Mitel Semiconductor Ltd | Data queues |
GB2370661B (en) * | 2000-12-29 | 2003-05-14 | Mitel Semiconductor Ltd | Method of, and apparatus for, storing a data packet |
GB2382899A (en) * | 2000-12-29 | 2003-06-11 | Zarlink Semiconductor Ltd | Data queue system |
GB2382898A (en) * | 2000-12-29 | 2003-06-11 | Zarlink Semiconductor Ltd | Managing queued data |
GB2382899B (en) * | 2000-12-29 | 2003-12-17 | Zarlink Semiconductor Ltd | A data queue system |
US6760795B2 (en) | 2000-12-29 | 2004-07-06 | Zarlink Semiconductor Limited | Data queue system |
GB2382898B (en) * | 2000-12-29 | 2005-06-29 | Zarlink Semiconductor Ltd | A method of managing data |
Also Published As
Publication number | Publication date |
---|---|
JPH037300B2 (en) | 1991-02-01 |
CA1191277A (en) | 1985-07-30 |
EP0118446B1 (en) | 1987-05-06 |
US4507760A (en) | 1985-03-26 |
JPS59501435A (en) | 1984-08-09 |
DE3371428D1 (en) | 1987-06-11 |
EP0118446A1 (en) | 1984-09-19 |
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