WO1982004499A1 - Monolithic integrated circuit - Google Patents

Monolithic integrated circuit Download PDF

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Publication number
WO1982004499A1
WO1982004499A1 PCT/DE1982/000038 DE8200038W WO8204499A1 WO 1982004499 A1 WO1982004499 A1 WO 1982004499A1 DE 8200038 W DE8200038 W DE 8200038W WO 8204499 A1 WO8204499 A1 WO 8204499A1
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WO
WIPO (PCT)
Prior art keywords
zone
transistor
collector
area
conductivity type
Prior art date
Application number
PCT/DE1982/000038
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German (de)
French (fr)
Inventor
Gmbh Robert Bosch
Original Assignee
Gademann Lothar
Michel Hartmut
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gademann Lothar, Michel Hartmut filed Critical Gademann Lothar
Publication of WO1982004499A1 publication Critical patent/WO1982004499A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
    • H01L27/075—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
    • H01L27/0755—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
    • H01L27/0761—Vertical bipolar transistor in combination with diodes only

Definitions

  • the invention is based on a monolithically integrated circuit arrangement according to the preamble of the main claim.
  • Monolithically integrated circuit arrangements of this type are already known, in which the diode is introduced into a special insulation trough and its one electrode is connected to the collector of the transistor via a metallization. These arrangements have the disadvantage that the complex IC technology with the many steps is necessary and that only circuit arrangements with the blocking voltages customary in IC technology can be implemented.
  • the monolithically integrated circuit arrangement according to the invention with the characteristic lierknalen of the main claim has the advantage that the separation diffusion customary in IC technology is eliminated and a higher level of integration is achieved with a simple planar method becomes.
  • reverse voltages of up to a few 100 volts, preferably 600 to 700 volts can be achieved by this technique, which cannot be achieved in conventional IC technology.
  • FIG. 1 The circuit diagram of the monolithically integrated circuit arrangement according to the invention shown in FIG. 1 shows an npn transistor 10 and a diode 11 which is connected with its cathode to the collector of the transistor 10.
  • a semiconductor die 12 consists of an n + -type substrate; 13 and an n-conducting epitaxial bar 14.
  • the free surface of the epitaxial bar 14 is covered with a passivation bar 15 made of silicon dioxide, into which windows for the attachment of contacts are introduced at various points.
  • the collector of the transistor 10 is formed by the n-type epitaxial layer 14.
  • the base zone of transistor 10 is formed by a first p-type zone 16 diffused into collector zone 14, while the emitter zone of transistor 10 is formed by a base zone 16 diffused n + -conducting zone 17 is formed.
  • the cathode of the diode 11 is formed by the n-type collector zone 14 of the transistor 10, while the anode of the diode 11 is formed by a second p-type zone 18 diffused into the collector zone 14.
  • a third p-type zone 19, which forms a guard ring, is diffused into the collector zone 14 around the p-type zone 18.
  • the guard ring 19 is connected to the collector zone 14 of the transistor 10 via a metallization 20.
  • the guard ring 19 prevents backlash of the diode 11 on the base 16 of the transistor 10.
  • the p-type zones 16, 18 and 19 are diffused together into the epitaxial layer 14.
  • the particular advantage of the monolithically integrated circuit arrangement according to the invention is that chip area is saved and that, in contrast to IC technology, higher blocking voltages can be achieved.
  • the advantage of this monolithic arrangement in comparison with a circuit arrangement with discrete elements is the simplified honing technique.
  • the diode 11 monolithically integrated in the manner described can also be combined with the known Darlington circuits. The inverse structure is also possible.
  • the metallization 20 is also ring-shaped and is contacted with the guard ring 19 via a ring-shaped contact window.
  • the connection to the collector opening 14 is brought about by an extension or widening 20a of the metallization 20, by contacting this extension or widening with the collector zone 14 via a contact window 21 provided in the passivation layer 15.
  • Further metallizations are designated with 22, 23 and 24.
  • the metallization 22 is the emitter metallization
  • the metallization 25 is the base metallization of the transistor 10
  • the metallization 24 is the metallization of the anode of the diode 11.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

In a semiconductor chip (12), there is arranged an integrated circuit with an npn transistor (10) and one diode (11). The diode (11) is connected to the collector of the transistor (10) through its cathode. The collector area of the transistor (10) is formed by a layer with an n?- type conductivity (14). The base area of the transistor (10) is formed by a first p type conductivity area (16) and diffused in the collector area (14) while the transmitter area of the transistor (10) is formed by an n?+ type conductivity area (17) diffused in the base area (16). The cathode of the diode (11) is formed by the n?- collector area (14) of the transistor (10) while the anode of the diode (11) is formed by a second p type conductivity area (18) diffused in the collector area. Further, there is diffused, in the collector area (14) around the second area (18) having a p type conductivity, a third p type conductivity area (19) which forms a guard-ring. This area (19) is connected with the collector area (14) of the transistor (10) by a metallization (20).

Description

Monolithisch integrierte SchaltungsanordnungMonolithically integrated circuit arrangement
Stand der TechnikState of the art
Die Erfindung geht aus von einer monolithisch integrierten Schaltungsanordnung nach der Gattung des Eauptanspruchs. Es sind bereits monolithisch integrierte Schaltungsanordnungen dieser Art bekannt, bei denen die Diode in eine besondere Isoiationswanne eingebracht und ihre eine Elektrode mit den Kollektor des Transistors über eine Metallisierung verbunden ist. Diese Anordnungen haben den lϊachteil, daß die aufwendige IC-Technik mit den vielen Terfahrensschritten notwendig ist und nur Schaltungsanordnungen mit den bei der IC-Technik üblichen Sperrspannungen realisierbar sind. Vorteile der Erfindung:The invention is based on a monolithically integrated circuit arrangement according to the preamble of the main claim. Monolithically integrated circuit arrangements of this type are already known, in which the diode is introduced into a special insulation trough and its one electrode is connected to the collector of the transistor via a metallization. These arrangements have the disadvantage that the complex IC technology with the many steps is necessary and that only circuit arrangements with the blocking voltages customary in IC technology can be implemented. Advantages of the invention:
Die erfindungsgemäße monolithisch integrierte Schaltungsancrdnung mit den kennzeichnenden lierknalen des Hauptanspruchs hat demgegenüber den Vorteil, daß die in der IC- Technik übliche Trenndiffusion entfällt und mit einem einfachen Planarverfahren eine höhere Integration erreicht wird. Außerdem können durch diese Technik Sperrspannungen bis zu einigen 100 Volt, vorzugsweise 600 bis 700 Volt, erreicht werden, die in der üblichen IC-Technik nicht erzielt werden können.The monolithically integrated circuit arrangement according to the invention with the characteristic lierknalen of the main claim has the advantage that the separation diffusion customary in IC technology is eliminated and a higher level of integration is achieved with a simple planar method becomes. In addition, reverse voltages of up to a few 100 volts, preferably 600 to 700 volts, can be achieved by this technique, which cannot be achieved in conventional IC technology.
Zeichnungdrawing
Ein Ausführungsbeispiel der erfindungsgemäßen monolithisch integrierten Schaltungsanordnung ist in der Zeichnung dargestellt und in der nachfolgenden Beschreibung näher erläutert. Es zeigen: Eig. 1 das elektrische Schaltbild der erfindungsgemäßen monolithisch integrierten Schaltungsanordnung, Eig. 2 einen Schnitt durch die erfindungsgemäße monolithisch integrierte Schaltungsanordnung.An embodiment of the monolithically integrated circuit arrangement according to the invention is shown in the drawing and explained in more detail in the following description. It shows: Eigen. 1 shows the electrical circuit diagram of the monolithically integrated circuit arrangement according to the invention, Eig. 2 shows a section through the monolithically integrated circuit arrangement according to the invention.
Beschreibung des AusführungsbeispielsDescription of the embodiment
Das in Fig. 1 dargestellte Schaltbild der erfindungsgemäßen monolithisch integrierten Schaltungsanordnung zeigt einen npn-Transistor 10 und eine Diode 11, die mit ihrer Kathode an den Sollektor des Transistors 10 angeschlossen ist.The circuit diagram of the monolithically integrated circuit arrangement according to the invention shown in FIG. 1 shows an npn transistor 10 and a diode 11 which is connected with its cathode to the collector of the transistor 10.
Fig. 2 zeigt die Realisierung dieser Schaltungsanordnung in monolithisch integrierter Technik. Ein Halbleiterplättchen 12 besteht aus einem n+-Ieitenden Substraτ; 13 und einer n-- leitenden Epitaxialschient 14. Die Epitaxialscnicht 14 ist an ihrer freien Oberfläche mit einer Passivierungsschient 15 aus Siliziumdioxid bedeckt, in die an verschiedenen Stellen Fenster für die Anbringung von Kontakten eingebracht sind. Die Kollektcrsone des Transistors 10 ist durch die n--leitende Epitaiciaischicht 14 gebildet. Die Basiszone des Transistors 10 ist durch eine in die Kollektorzone 14 eindiffundierte erste p-leitende Zone 16 gebildet, während die Emitterzone des Transistors 10 durch eine in die Basiszone 16 eindiffundierte n+-leitende Zone 17 gebildet ist. Die Kathode der Diode 11 wird durch die n--leitende Kollektorzone 14 des Transistors 10 gebildet, während die Anode der Diode 11 durch eine zweite, in die Kollektorzone 14 eindiffundierte p-leitende Zone 18 gebildet wird. Um die p-leitende Zone 18 herum ist in die Kollektorzone 14 eine dritte p-leitende Zone 19 eindiffundiert, die einen Guardring bildet. Der Guardring 19 ist über eine Metallisierung 20 mit der Kollektorzone 14 des Transistors 10 verbunden. Der Guardring 19 verhindert eine Hückwirkung der Diode 11 auf die Basis 16 des Transistors 10. Die p-leitenden Zonen 16, 18 und 19 werden gemeinsam in die Epitaxialschicht 14 eindiffundiert.2 shows the implementation of this circuit arrangement in monolithically integrated technology. A semiconductor die 12 consists of an n + -type substrate; 13 and an n-conducting epitaxial bar 14. The free surface of the epitaxial bar 14 is covered with a passivation bar 15 made of silicon dioxide, into which windows for the attachment of contacts are introduced at various points. The collector of the transistor 10 is formed by the n-type epitaxial layer 14. The base zone of transistor 10 is formed by a first p-type zone 16 diffused into collector zone 14, while the emitter zone of transistor 10 is formed by a base zone 16 diffused n + -conducting zone 17 is formed. The cathode of the diode 11 is formed by the n-type collector zone 14 of the transistor 10, while the anode of the diode 11 is formed by a second p-type zone 18 diffused into the collector zone 14. A third p-type zone 19, which forms a guard ring, is diffused into the collector zone 14 around the p-type zone 18. The guard ring 19 is connected to the collector zone 14 of the transistor 10 via a metallization 20. The guard ring 19 prevents backlash of the diode 11 on the base 16 of the transistor 10. The p-type zones 16, 18 and 19 are diffused together into the epitaxial layer 14.
Der besondere Vorteil der erfindungsgemäßen monolithisch integrierten Schaltungsanordnung besteht darin, daß Chipflächegespart wird und daß im Gegensatz zur IC-Technik höhere Sperr spannungen realisiert werden können. Der Vorteil dieser monolithischen Anordnung im Vergleich mit einer Schaltungsanordnung mit diskreten Elementen ist die vereinfachte Hontagetechnik. Die in der beschriebenen Weise monolithisch integrierte Diode 11 kann auch mit den bekannten Darlington Schaltungen kombiniert werden. Es ist auch die inverse Struktur möglich.The particular advantage of the monolithically integrated circuit arrangement according to the invention is that chip area is saved and that, in contrast to IC technology, higher blocking voltages can be achieved. The advantage of this monolithic arrangement in comparison with a circuit arrangement with discrete elements is the simplified honing technique. The diode 11 monolithically integrated in the manner described can also be combined with the known Darlington circuits. The inverse structure is also possible.
Im Bereich des Guardrings 19 ist die Metallisierung 20 ebenfalls ringförmig ausgebildet und über ein ringförmig ausgebildetes Eontaktfenster mit dem Guardring 19 kontaktiert. Die Verbindung mit der Kollektcrzcne 14 wird durch einen Ausläufer oder eine Verbreiterung 20a der Metallisierung 20 bewirkt, indem dieser Ausläufer oder diese Verbreiterung über ein in der Passivierungsschicht 15 angebrachtes Kontaktfenster 21 mit der Kollektorzone 14 kontaktiert ist. Weitere Metallisierungen sind mit 22, 23 und 24 bezeichnet. Die Metallisierung 22 ist dabei die Emittermetallisierung, die Metallisierung 25 ist die Basismetallisierung des Transistors 10, während die Metallisierung 24 die Metallisierung der Anode der Diode 11 ist. In the area of the guard ring 19, the metallization 20 is also ring-shaped and is contacted with the guard ring 19 via a ring-shaped contact window. The connection to the collector opening 14 is brought about by an extension or widening 20a of the metallization 20, by contacting this extension or widening with the collector zone 14 via a contact window 21 provided in the passivation layer 15. Further metallizations are designated with 22, 23 and 24. The metallization 22 is the emitter metallization, the metallization 25 is the base metallization of the transistor 10, while the metallization 24 is the metallization of the anode of the diode 11.

Claims

Ansprüche Expectations
1. In einem Halbleiterplättchen untergebrachte monolithisch integrierte Schaltungsanordnung mit einem Transistor und mit einer Diode, die in die Kollektcrleitung des Transistors in Flußrichtung geschaltet ist, wobei die Kollektorsone des Transistors. (10) durch eine Schicht (14) eines ersten Leitfähigkeitstyps in dem Halbleiterplättchen (12), die Basiszone des Transistors (10) durch eine in die Kollektorzone (14) eindiffundierte erste Zone (16) eines zweiten, zur Kollektorsone (14) entgegengesetzter. Leitfähigkeitstyps und die Emitterzone des Transistors (10) durch eine in die Basiszone (16) eindiffundierte Zone (17) vom ersten Leitfähigkeitstyp gebildet ist, dadurch gekennzeichnet, daß die an den Kollektor des Transistors (10) angeschlossene Elektrode der Diode (11) durch die Kollektcrzone (14) des Transistors (10) und die andere Elektrode der Diode (11) durch eine zweite, in die Kollektorzone (14) eindiffun dierre Zone (18) von zweiten Leitfähigkeitstyp gebildet 1. Housed in a semiconductor die monolithically integrated circuit arrangement with a transistor and with a diode which is connected in the collector line of the transistor in the direction of flow, the collector sonar of the transistor. (10) through a layer (14) of a first conductivity type in the semiconductor wafer (12), the base zone of the transistor (10) through a first zone (16) diffused into the collector zone (14) of a second, opposite to the collector zone (14). Conductivity type and the emitter zone of the transistor (10) is formed by a zone (17) of the first conductivity type diffused into the base zone (16), characterized in that the electrode of the diode (11) connected to the collector of the transistor (10) by the Collector zone (14) of the transistor (10) and the other electrode of the diode (11) are formed by a second zone (18) of the second conductivity type which diffuses into the collector zone (14)
2. Schaltungsanordnung nach Anspruch 1, dadurch gekenn zeichnet, daß zur Trennung des Transistors (10) von der Diode (11) in die Kollektorzone (14) sine drirte Zone (19) vom zweiten Leitfähigkeitstyp eindiffundiert ist, die durch den Zwischenraum zwischen der ersten (16) und der zweiten (18) Zone vom zweiten Leitfähigkeitstyp hindurch verläuft und über eine Ketallisierung (20) mit der Kollektorzone (14) des Transistors (10) verbunden ist.2. Circuit arrangement according to claim 1, characterized in that for the separation of the transistor (10) from the diode (11) in the collector zone (14) sine third zone (19) of the second conductivity type is diffused through the gap between the first (16) and the second (18) zone of the second conductivity type passes through and is connected to the collector zone (14) of the transistor (10) via a metalization (20).
3. Schaltungsanordnung nach Anspruch 2, dadurch gekennzeichnet, daß die dritte Zone (19) des zweiten Leit fähigkeitstyps die zweite Zone (18) des zweiten Leit fähigkeitstyps ringförmig umschließt.3. A circuit arrangement according to claim 2, characterized in that the third zone (19) of the second conductivity type surrounds the second zone (18) of the second conductivity type in a ring.
4. Schaltungsanordnung nach einem der Ansprüche bis 3,. dadurch gekennzeichnet, daß die erste (16), die zweite (18) und gegebenenfalls die dritte (19) Zone des zweiten Leitfähigkeitstyps dieselbe Diffusionstiefe, dasselbe Diffusicnsprofil und dieselbe Oberflächenkonsenration 4. A circuit arrangement according to one of claims to 3. characterized in that the first (16), the second (18) and possibly the third (19) zone of the second conductivity type have the same diffusion depth, the same diffusion profile and the same surface concentration
PCT/DE1982/000038 1981-06-09 1982-06-26 Monolithic integrated circuit WO1982004499A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3122855810609 1981-06-09
DE19813122855 DE3122855A1 (en) 1981-06-09 1981-06-09 "MONOLITHICALLY INTEGRATED CIRCUIT ARRANGEMENT"

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WO1982004499A1 true WO1982004499A1 (en) 1982-12-23

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DE (1) DE3122855A1 (en)
WO (1) WO1982004499A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4236557C2 (en) * 1992-10-29 2002-08-01 Semikron Elektronik Gmbh Power semiconductor device
JP4761644B2 (en) * 2001-04-18 2011-08-31 三菱電機株式会社 Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0011964A1 (en) * 1978-11-15 1980-06-11 Fujitsu Limited Semiconductor device including a diode and a bipolar transistor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0011964A1 (en) * 1978-11-15 1980-06-11 Fujitsu Limited Semiconductor device including a diode and a bipolar transistor

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM Technical Disclosure Bulletin, Vol. 15, No. 1, published in June 1972, Armonk, New York (US), H.H. BERGER u.a.: Diistor", see page 233 and figure *
IBM Technical Disclosure Bulletin, Vol. 8, No. 12, published in May 1966, Armonk, New York (US) AGUSTA u.a.: "Component Interconnection for Integrated Circuits", see page 1843-1844 and figures A and B *

Also Published As

Publication number Publication date
EP0081494A1 (en) 1983-06-22
DE3122855A1 (en) 1983-01-05

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