Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04Q—SELECTING
  • H04Q9/00—Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom
  • H04Q9/14—Calling by using pulses
  • H04Q9/16—Calling by using pulses by predetermined number of pulses
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01F—MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME
  • G01F1/00—Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow
  • G01F1/68—Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow by using thermal effects
  • G01F1/684—Structural arrangements; Mounting of elements, e.g. in relation to fluid flow
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R22/00—Arrangements for measuring time integral of electric power or current, e.g. electricity meters
  • G01R22/06—Arrangements for measuring time integral of electric power or current, e.g. electricity meters by electronic methods
  • G01R22/10—Arrangements for measuring time integral of electric power or current, e.g. electricity meters by electronic methods using digital techniques
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R22/00—Arrangements for measuring time integral of electric power or current, e.g. electricity meters
  • G01R22/06—Arrangements for measuring time integral of electric power or current, e.g. electricity meters by electronic methods
  • G01R22/061—Details of electronic electricity meters
  • G01R22/066—Arrangements for avoiding or indicating fraudulent use
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
  • G01R35/04—Testing or calibrating of apparatus covered by the other groups of this subclass of instruments for measuring time integral of power or current

Definitions

• the present invention also relates to a system for monitoring of energy consumption in an electrical path at a remote station.
• electrical installations such as in commercial buildings, apartments, condominiums, etc. where a single utility meter is provided at an electrical service entrance.
• a single utility meter is provided at an electrical service entrance.
• individual energy consumption in the apartments or other units of the building cannot be individually monitored or billed. This tends to promote waste as the occupants of the apartments have no individual control over total energy consumption and consequently little or no economic incentive to conserve energy.
• the central station computer receives data from the current sensor represen tating current consumption and data representing voltage in the electrical path and calculates power, storing and processing it to provide a periodic indication of energy consumption which may be used for information or billing purposes.
• the system of the invention provides this function.
• Fig. 14 is a flowchart of a sensor interrupt program
• Figs. 25A . . . 25M together form a flowchart of the OIP program illustrated in Fig. 9;
• Fig. 1 shows a central computer system 23 which communicates with a plurality of modular remote stations 11 through a master controller 19, a controller interface 15, an A-D converter 21 and a plurality of section switches 17.
• the computer system 23 is a conventional commercially available system. One which has been found to be particularly suitable for use with the invention is known as the North Star Horizon. It includes a central processing unit (CPU) 27, a random access memory (RAM) 29 for temporarily storing programs and data, a disc controller 31, a floppy disc system 33 for permanently storing programs and data, an interface 35 for communicating with an externally connected video input output terminal 37, and a bus structure 25 to which the CPU 27, RAM 29 disc controller 31, and interface 35 are connected.
• CPU central processing unit
• RAM random access memory
• each of the remote stations of the group can be addressed by cycling through a predetermined number of tone bursts. If 16 remote stations each containing 16 information channels are connected to each communications channel, a total of 256 tone bursts will serve to address and sequentially connect each of the information channels to the communications channel. By repeating the sequence of 256 tone bursts, the remote stations and information channels thereat can be continually addressed by computer system 23. Moreover, the sequential addressing tone bursts can be sent simultaneously over all the communications channels so that every tone burst sent will cause 32 addressed information channels to be connected to the central station over 32 communications channels.
• Fig. 2 also illustrates the information channel switching portion of each remote station by a numeral 39.
• a numeral 39 In some instances, for example where the outputs of two or more sensors are to be simultaneously connected to the central station over respective communications channels, a plurality of switching portions 39 at a remote station are connected in parallel.
• a remote station can have one or more switching portions 39 connected to the outputs of counter 89 and gates 103 and 104, as illustrated in Fig. 2.
• Each additional switching portion 39 would have its own information channels 10, input and output terminals corresponding to LG and LI, but all may derive their operative power from a common power supply circuit 63.
• the system data bus 13 also includes pin terminals for the output lines of one or more analog to digital converters. These output lines, AD ⁇ . . . AD9, are connected to the pins of system bus 13 as follows:
• Bus 13 also contains various control signal lines containing signals generated by various portions of the system as follows:
• SSPCL 26 A reset signal used to reset the automatic digital gain control system Control Signals Pin Designation Description of Signal IFIO 28 Decoded address from the CPU used to designate a controller interface input/output operation
• Each section switch portion (Fig. 4) is connected to 16 of the 32 incoming lines with the other identical portion being connected to the remaining 16 incoming lines. Since each section switch portion (Fig. 4) only services one of the 16 lines connected thereto, a pair of analog selection switches 143 and 145 is used to connect one of the 16 incoming lines to the remainder of the section switch circuit.
• the selecting data inputs to analog switches 143 and 145 are taken from lines 737, 739, 741 and 743 which are taken from the output of a latch 131 in Fig. 3.
• Inverter 147 can be disabled by a control signal CFGSEL applied to line 751, in a manner described further below, so that the signal applied to line 737 will enable both analog switches 143 and 145 at the same time.
• each section switch portion illustrated in Fig. 4 be capable of communicating with two lines simultaneously. For example, if one incoming line was coupled to a voltage sensor and the other to a current sensor at a remote station, a section switch portion could simultaneously process current and voltage information to calculate the power being monitored at a remote station.
• This so-called "split-bus" configuration is set by the CPU which addresses a latch 371 in the controller interface supplying thereto a signal CFGSEL which is applied to the section switches by a pin 44 of system bus 13.
• the section switches incorporate a voltage offset compensation circuit for adding to the sensor output a predetermined DC voltage level which serves to normalize the sensor output voltages to be within a predetermined voltage range, or to convert a resistance sensor output to a voltage signal.
• the voltage offset compensation is provided by an analog switch 161 and jumper selectable reference voltage bus 159.
• Analog switch 161 contains a plurality of inputs 163, 165, 167, 169, 171 and 173 which can be jumper connected through respective resistors to one of four reference voltage lines provided at bus 159. For example, the four lines illustrated may respectively receive voltages of 0, 2.5, 5 and 10 volts.
• Gain control circuit 245 receives as an input on line 231 the output of the four quadrant multiplier and supplies this output to a window comparison circuit 225 consisting of a pair of comparison amplifiers 233 and 235.
• Window comparator 225 determines if the output of the multiplier is within a predetermined range. If it is not, an output signal is applied through inverter 229 to gate 227 as an enable signal allowing gate 227 to pass 15 KHz clocking signals on line 749 to the clock terminal of counter 221. These clocking signals originate in the controller interface. As a result, the counter counts clock pulses occurring at a 15 KHz rate whenever the signal at the output of the four quadrant multiplier exceeds a predetermined signal level range.
• An undesirable by-product of the current sensor signal path through the automatic gain control circuit 245 and into multiplying A/D converter 185 is a DC offset voltage produced by the various amplifiers in the chain.
• capacitors 205 and 203 are respectively provided in the outputs of amplifier 211 and 189. Prior to the occurrence of an AC power measurement, these capacitors are allowed to charge to the inherent offset voltages by connecting the output side of each to ground while at the same time grounding the AC path input 243 through switch 241 using control input 747 more fully described below.
• the outputs of capacitors 205 and 203 are grounded by respective switches 207 and 201 which are activated by CPU 27 prior to an AC measurement being taken.
• DELACGRD is generated by a delay circuit 137 provided in the section switches (Fig. 3) on line 747 which is supplied to switch 241.
• DELACGRD controls switch 241 to connect amplifier 217 input signal line 243 to line 154 a predetermined period of time after capacitors 205 and 203 are released from ground by ACGRD. Accordingly, a sensor output signal is applied to the input of the automatic gain control circuit 245 only after capacitors 205 and 203 have been charged to the DC offset voltages.
• Fig. 4 also shows that the input to the multiplying A to D converter 185 may come from system bus 13 pins 30, 37, 87, 86, 85, 84, 83, 82, 76, 75 and 74. These pins are connected to another tracking analog to digital converter provided in the controller interface 15 which can be used if a tracking A to D converter 181 is not provided in the section switches.
• the tracking A to D converter 181, when provided in the section switches in the manner illustrated in Fig. 4, is enabled by a signal applied to pin 30 of the system bus 13 which receives a signal SSADOFF sent by CPU 27 to latch 371 in the controller interface.
• the controller interface 15 (Fig. 1) will now be described.
• the controller interface supplies to system bus 13 many of the control signals which the section switches use to configure them for a particular function, either receiving sensor outputs or supplying tone control signals to an addressed information channel 10 which is temporarily connected through a communications channel to a respective section switch portion (Fig. 4).
• the controller interface also generates the addressing tones which are sent to the remote stations to connect an information channel to a respective communications channel.
• the controller interface includes an address decoder 359 which is connected to address line A ⁇ , A1, A 2 and A3. These address lines, as well as signal line PWR collectively identified by numeral 821 in Fig. 6, are output lines from the master controller 19 as is signal line 825 containing IFIO.
• the address decoder 359 when enabled by the output of NAND gate 367, decodes four different addresses for respective latches 369, 371, 373 and 375.
• NAND gate 367 is enabled by the presence of the signal PWR which is applied to one input thereof via buffer 361 and NAND gate 365 and by the signal IFIO which is applied through buffer 363 to its other input. These signals which come from the master controller (Fig. 7), are supplied by CPU 27 whenever the controller interface is to perform an input/output operation.
• a precision reference voltage generator 351 (Fig. 6B) is provided which supplies output voltages V7, V8 and V9 to six of the eight input lines to switch 347.
• the other two input lines to switch 347 are respectively connected to a 60 hz line voltage input on line 813 and ground.
• the output line of switch 347 is connected to amplifier 355, the output of which is connected in common to four of the input lines of switch 349.
• the output of amplifier 355 also passes through inverting amplifier 357 and the inverted signal is connected to the 4 remaining input lines of switch 349.
• switch 337 couples one of the outputs from lines Al-N, A2- ⁇ , B2- ⁇ , or C2- ⁇ to the input of buffer amplifier 335, the output of which is connected to pin 34 of the system bus 13.
• the voltages of pins 33 and 34 appear as inputs to analog switch 175 of the section switches (Fig. 4) as described earlier.
• the controller interface also includes a programmable frequency divider 313 (Fig. 5) which receives as an input an output of oscillator 301.
• the frequency of oscillator 301 is divided by a value programmed into the frequency divider 313 on data lines 817.
• These data lines receive data from latch 369 (Fig. 6A) which is addressed by the CPU 27 to apply data to the latch representative of a desired tone frequency which is to be sent from the section switches to the remote station lines connected thereto.
• One tone frequency e.g. 100Khz, is used for addressing the information channels 10 at the remote stations, while other tone frequencies can be used to control an operative device connected to an addressed information channel 10 at a remote station.
• Signals FTP and CTP are applied to counter sections 679 and 681 after passing through respective buffer amplifiers 798 and 796.
• CPU 27 programs the two sections 679 and 681 of the programmable counter, it successively outputs the signals FTP and CTP by providing appropriate address signals to address decoder 792, along with the data which is to be loaded into the counter sections 679 and 681 (applied to lines 781) by the FTP and CTP load signals.
• the three interrupt control signals VI4, PTO and MTO are each connected to respective identical latching and reset circuits in the master controller.
• the PTO control signal on line 783 is applied to a clock input of a flip-flop 603 the output of which enables buffer amplifiers 607 and 609 to apply a ground condition to respective pins 73 and 9 of the S-100 bus.
• Amplifie rs 607 and 609 respectively generate output signals PINT and PTI.
• the PINT signal which is applied to pin 73 of the S-100 bus goes "low" to indicate to the CPU 27 that an interrupt has occurred.
• the CPU 27 then examines its interrupt lines respectively connected to pins 10, 9 and 8 of the S-100 bus to determine which interrupt(s) is occurring.
• the CPU then processes the interrupt program for the highest priority interrupt then occurr ing.
• flip-flop 603 After the interrupt PTI occurs, flip-flop 603 must be reset before the occurrence of the next interrupt, otherwise it will not be detected. For this pur pose, flip-flop 603 is reset by a signal PTIR which is provided on an output line of latch 601. CPU 27 sup plies the signal PTIR to the latch 601 to reset flip- flop 603 during pro cessing of the interrupt program(s) associated with the PTI interrupt.
• the interrupt control signal VI4 received on line 310 clocks flip-flop 617 which is reset by the signal VI4EN supplied by latch 601. Whenever any of the interrupt outputs to respective pins 10, 9 or 8 is generated, the associated inter rupt request signal PINT is also generated to notify CPU 27 that an interrupt signal is present.
• the analog offset voltage output of D/A converter 511 is fed to a summing amplifier 512 which receives at its other input the output of 1 of 32 line select switch 503.
• This device is similar to previously described analog selection switches. A particular switch is closed to pass one of the input lines to the output line 901 in accordance with the addressing data signal applied thereto.
• the selecting of an appropriate input line is accomplished by connecting the data select input 505 of the line select switch 503 to the address bus lines A ⁇ . . . A4 of the S-100 bus.
• the line inputs to the line select switch 503 are the respective lines J ⁇ . . . J31 exiting from the section switches. Two lines exit each section switch, one for each of the Fig. 4 portions. These lines represent the 32 wire pairs which are respectively connected to 32 groups of remote stations.
• Buffer 565 has five upper inputs connected to the output of a gate 557 through inverter 568 and the next input to the MSB or MSB output of converter 553 as described below.
• the last two bits of buffer 565 go to bits 9 and 8 of A/D converter 553.
• Buffer 567 has its 8 inputs connected to the 8 least significant bits of A/D converter 553.
• decoder 551 with the control signal 11 BIT and operating flip flop 548 with the outputs of gates 531 and 533 (respectively applied to the 3 and CL inputs)
• various output bits of the A/D converter 553 can be gated under control of CPU 27 to its data inputs.
• the A/D converter 21 also includes various gating circuits which are used to control operation of the A/D converter 553 as well as to enable decoder 551 and operate flip flop 548.
• Negative input AND gate 529 receives the output of NOR gate 523 and the output of an inverter 527 connected through the buffer 525 to the pin 78 of the S-100 bus which contains the PDBIN signal. Accordingly, when the CPU 27 outputs either an SOUT or an SINP signal and a PDBIN signal, gate 529 is enabled.
• the output of gate 529 is supplied to the input of NAND gate 531 which has at its other input the output signal on line 903 which is an address decoded by address decoder 501.
• NAND gate 533 The output of NAND gate 533 is also connected through inverter 535 to one input of NAND gate 541 which receives as its other input the PSYNC signal on pin 76 of the S-100 bus through buffer 525.
• NAND gate 541 supplies an enable signal to wait state generator 545.
• Wait state generator 545 is similar to the wait state generator on the master controller. When enabled, it counts a predetermined number of clock pulses before emitting an output signal.
• the purpose of wait state generator 545 is to allow data to settle on the incoming section switch lines before A/D converter 553 is instructed to perform a conversion operation.
• the output signal from wait state generator 545 is supplied to a convert input terminal of the A/D converter 553 and this starts the A/D conversion operation.
• NAND gate 541 which enables the wait state generator is also applied as a clear (CL,) input to flip-flop 575.
• the output of flip-flop 575 passes through NOR gate 573 and activates buffer 569 to pull the line connected to pin 72 of the S-100 bus "low". This supplies a PRDY signal to the CPU 27 placing it in a wait state.
• the wait state counter counts to its predetermined value (approximately a two micro-second delay)
• the A/D converter 553 is instructed to begin conversion. At this time the status line STA of A/D converter 553 goes high and remains high during the conversion process.
• the present invention can also be used to economically measure temperature, fluid flow and heat flow at a multiplicity of locations. This is done by using a combination of resistance and precision resistance change measurements in conjunction with various temperature and flow sensors which have been developed to supply resistance and precision resistance outputs to the information channels 10.
• Air flow is determined by measuring the temperature difference between a first conventional temperature sensor e.g. a thermistor, provided in an air stream and a second temperature sensor provided in the air stream at a location downstream of the first.
• a first conventional temperature sensor e.g. a thermistor
• a second temperature sensor provided in the air stream at a location downstream of the first.
• Fig. 27 illustrates an air flow sensing system using a thermistor 214 and a thermistor 218, the latter being thermally bonded to a fixed resistor 216 by a thermally conductive epoxy 224, as the first and second temperature sensors.
• Resistor 216 is connected across a voltage source 222.
• a conventional humidity detector 220 Also illustrated is also illustrated.
• the temperature difference between thermistor 218 and thermistor 214 determines the air flow since for any given air handling system a curve of air flow rate versus temperature differences can be experimentally derived. Although these curves vary somewhat with absolute air temperature and humdity, it is possible to construct families of curves for air flow rate versus temperature difference which are entered into CPU 27 and used as look up tables for determining an air flow knowing the absolute air temperature and the humidity.
• a thermistor/resistor sensor similar to that for the air flow, has been devised which is housed in a tiny metal can.
• This flow sensor is illustrated in Fig. 28A and 28B.
• the sensor 226 comprises a chip resistor 234 which is connected to a voltage source 238 for providing a constant temperature adjacent a thermistor 236 which is mounted by means of highly thermally conductive epoxy 232 in thermal contact with resistor 234.
• the entire assembly then is encased in a metal can 230 which is provided in a housing 228.
• CPU OPERATION Sensor data gathering and processing for the system is handled under interrupt control of the CPU 27. Further processing of the sensor data into more meaningful information for the display of gathered and processed data is handled by an operator interactive sequential program (OIP) which runs continuously, except when interrupted by the various system interrupts.
• OIP operator interactive sequential program
• the system uses three interrupts to control the operation of CPU 27. These have been briefly described above with reference to the system hardware.
• the highest priority interrupt MTI is generated under control of the master timer signal MTO which is the output of divider 683 in the master controller.
• MTO is a pulse signal generated, for example, at the rate of 512 pulses per hour (one every 7.03125 seconds).
• NIPAD now contains the address of the program "Step to sensor #1", which is generally shown at the top of Fig. 13 as a "Step to next sensor” program
• the next sensor interrupt causes CPU 27 to execute this program in step 606 of the sensor interrupt program (Fig. 14).
• the tone is enabled as previously described. This tone causes sensor #1 of each group of remote stations to be connected to a respective communications channel.
• the sensor interrupt timer is then set for 1 millisecond in step 516 to define the tone duration and the address of the "Sensor #1 data gathering" program is set in NIPAD at step 518.
• the CPU then returns at step 519.
• CPU 27 proceeds to execute a "Sensor #1 data gathering" program and then a "Sensor #1 data processing" program corresponding to steps 469 through 487 described earlier with reference to sensor #0.
• the data stored in NIPAD at step 518 will be the address of the "sensor #0 data gathering" program; however, for subsequent sensor interrupts, this address will change to correspond with the next sensor, i.e. 1, 2 . . . etc. data gathering program which must be executed.
• the "Step to next sensor" program includes step 614 where a tone is enabled, step 616 where the sensor interrupt timer is set for 1 millisecond and step 618 where the address of a "Wait for data to settle" program is stored at NIPAD. Steps 614 and 616 correspond directly with steps 514 and 516 described above with reference to Fig. 13.
• Fig. 15 The programs illustrated in Fig. 15 are repeated for each of the sensors of a remote station in the manner described above with reference to Figs. 13A and 13B.
• the CPU executes a routine consisting of steps 502 . . . 512 (Fig. 13B) to determine if all remote stations of a group have been processed. If not, the Fig. 15 programs are repeated until all sensors of all remote stations of a group have been processed at which time the CPU will return to OIP (step 512, Fig. 13B).
• the CPU 27 sets a line counter N to one. It then fetches the present sensor calibration data from the buffer in step 806 for line N of the current set of remote stations (units) (N represents one of the 32 incoming communications channels.
• N represents one of the 32 incoming communications channels.
• the 32 lines can be identified by a section switch S (0-15) and line L (0, 1) numbers, but for purposes of simplicity line number N (1-32) can and will also be used in the subsequent description.).
• the CPU fetches the previous sensor calibration data for line N. A comparison is then made by CPU 27 in step 810 between the present and previous sensor calibration data.
• step 810 If in step 810 the present calibration data differs from the previous calibration data for a given line N by more than +1%, the line number N and the unit (remote station) number are all stored in an error buffer in step 818 after which CPU 27 sets an error flag in step 820. The CPU then proceeds to step 812. If the gathered data represents an air temperature, the application program illustrated in Fig. 21 is executed at step 642 of Fig. 15. This application program begins at a step 836 in which CPU 27 sets a line counter value N to one. In step 838, a present sensor air sample value is fetched from a buffer for line N of the current set of units. This value is corrected with a previously stored correction value for line N of the current set of units, and an equivalent air temperature value is determined in step 840.
• step 842 the CPU then adds the temperature value to an hourly accumulator and proceeds to step 844 where it increments N.
• step 862 If it finds one in step 862 it proceeds to step 856 and stores information relating to the unit number (remote station number) and current time in the action buffer as described previously. If step 862 indicates that there was no previous potential fire indicated, the CPU proceeds to step 866 where it stores an indication of a potential fire in a reference buffer for the current unit for comparison with a subsequent sample of that unit sensor output upon the next execution of the program. From step 866, the CPU then proceeds to step 863 where it increments the line number N. If, in step 854, the CPU determines that there is no potential fire, it proceeds to step 863 to increment to the unit number N.
• step 885 of this program the CPU sets a line counter value N to 1.
• the CPU fetches first sensor data TWI (temperature of water in) for line N (e.g. an upstream temperature sensor). This data was previously acquired and stored by the CPU in a temporary buffer when processing the data gathering program for this sensor.
• the CPU fetches second sensor data TWF (temperature of water flow) for line N (e.g. a downstream temperature sensor), subtracting it from the sensor data fetched in step 887 to yield TWI-TWF.
• the subtracted data is then further subtracted from previously acquired and stored calibration data ⁇ TWF ⁇ for line N of the current set of units representing the difference between the data of the first and second sensors under known flow conditions.
• the CPU proceeds to step 892 where it uses the value calculated in step 890 ( ⁇ TWFO- (TWI-TWF)) in a table look-up operation to determine flow rate through a heat exchanger corresponding to the value calculated.
• the CPU then proceeds to step 894 where it fetches third sensor data TWO for line N (sensor 245, Fig. 29), which was also previously acquired and stored by the CPU when processing the data gathering program for this sensor.
• the third sensor data represents a downstream fluid temperature at the output of a heat exchanger.
• This data is corrected with previously acquired calibration data ( ⁇ TWO), and is subtracted from the data TWI obtained in step 887 to determine the difference in temperature between the input and output of a heat exchanger.
• This value is then used in step 896 by the CPU as a value which is multiplied by the flow rate acquired in step 892 for calculation of a thermal energy usage rate; that is, the BTU rate.
• the calculated BTU rate is applied to an accumulating buffer and the CPU then increments the unit counter N in step 899, after which it determines in step 902 if data from the sensors of all lines has been processed. If not, CPU returns to step 887 where data for the next line is processed. If all units have been processed as determined in step 902, the CPU returns at step 903.
• Fig's. 16A, 16B illustrate the programs executed by the CPU 27 when measuring a sensor output which is in the form of a precision resistance change.
• Some of this program is identical with that illustrated in Fig. 15 and accordingly like boxes have been numbered with the same reference numerals. The principal difference between this program and that of Fig. 15 occurs in how the resistance data which has been taken is processed and this begins at step 904 of Fig. 16A and discussion will begin at this point.
• step 914 converts the analog delta resistance value for the incoming line (one of the 32 incoming lines) to a binary form, storing this in a buffer area in step 916.
• the line counter is incremented in step 918 and the line counter value is tested in step 920 to determine whether it exceeds a predetermined line maximum of 1. If not, the CPU then proceeds back to step 908 where it sets the calibration resistance data for the next line (identified by L and S) into the D/A analog converter latches 513 and 509. If the line counter is greater than a maximum of 1 in step 920, the line counter is set to zero in step 922 and the section counter is incremented in step 924.
• the section and line counters (S, L) are used to point to one of the 32 incoming lines.
• the reason for using these counters is that previous resistance data for an incoming line must be fetched in step 908 and inserted into D/A converter 511 for summation with present resistance data for the same line, as each sensor output is processed.
• the S and L counters enable the CPU to locate and fetch this previously stored data.
• the sensors which may be used in the system can also produce a DC voltage output and when such sensors are used, the program of Fig. 17 is executed by the CPU to gather and process sensor data.
• certain steps are the same as in the program illustrated in Fig. 15 and these have been labeled with the same reference numerals.
• the principal difference in a DC voltage measurement program is that a step 936 appears after the sensor interrupt timer is set in step 624 to allow sufficient time for data to settle on the lines. Step 936 sets the section switches for a DC voltage measurement mode.
• the Section Switc hes are set for a DC voltage mode by first setting the ACMEN signal and resetting the ACGRD signal at the controller interface latch 373 and then resetting the L0 and L1 REFEN signal on latch 119 of all the Section Switches. Following this, the address of a "Take DC voltage data" program is stored at NIPAD in step 938 following which the CPU returns in step 940 to await a next interrupt. When the next interrupt occurs, the "take DC voltage data" program is executed which begins at step 634 where the sensor interrupt timer is set for one millisecond.
• step 942 converts the DC voltage on each of the 32 section switch lines into binary data and stores it in a buffer area.
• the CPU then proceeds to step 944 where it stores the address of the "step to next sensor" program at NIPAD in step 944 and it then enables the interrupts in step 946 and calls the program used to process the data stored in the buffer area in step 948.
• this can be any one of the application programs described earlier with references to Figs. 19 and 21-24.
• the DC voltage measurement program returns at step 950.
• a principal feature of the present invention is the ability of the CPU to monitor power consumption in an electrical path at one of the remote stations.
• Figs. 18A, 18B, 18C, 18D illustrate the flow chart for the program executed by CPU 27 to take the necessary AC measurements which are used to calculate power consumption.
• step 1012 the CPU proceeds to step 1014 where it selects a current multiplied by current mode of the section switches.
• the current multiplied by current mode is set by first resetting signals VSSEL-L ⁇ , VSSEL-L1 and MODESEL at latch 119 of all the Section Switches.
• the CFGSEL signal of latch 371 is reset. The net effect of these controls signals is to connect section switch input line 150 to the input of tracking A/D converter 181.
• the third step is to set the AC path gain to a minimum. This is accomplished by first setting the SS signal of latch 371 after which the SSP signal of latch 373 is alternately reset and then set again to set the AC path gain to maximum. Now the signal SS at latch 371 is alternately reset and set eight times. The AC path gain has now been clocked to minimum gain.
• step 1014 the CPU advances to step 1016 where it selects a proper DC test voltage which is applied through a resistor which best matches the current transducer impedance.
• This matching resistor is shown in Fig. 4 between pin 24 and switch 175.
• an incoming current from a current transducer (in the form of a voltage signal) will be applied to both the A/D converter 181 (via path 150) and the automatic gain control 245 (via input 243) causing A/D multiplier 181 to produce a current squared output.
• step 1020 the CPU fills a current transducer impedance buffer with data corresponding to hexidecimal "FF" following which the CPU sets an AC measurement interrupt counter to zero in step 1022.
• step 1024 the CPU sets the maximum AC measurement interrupts which will occur to 16.
• step 1026 the CPU proceeds to step 1026 where it stores the address of a program "Set AC current gain” at NIPAD which will be executed upon the occurrence of the next sensor interrupt.
• step 1028 the CPU enables the AC measurement interrupts.
• the AC measurement interrupts are enabled by setting V14EN of the Master Controller latch 601. There are 32 AC measurement interrupts generated for each cycle of the 60 Hz main power waveform at the output of the phase lock loop multiplier 307 in the controller interface 15.
• step 1030 the CPU enables the interrupts and then returns in step 1032.
• the next sensor interrupt will cause the CPU to execute the "Set AC current gain" program.
• 16 AC measurement interrupts will occur which will cause the AC measurement programs, identified as steps 1034 . . . 1056 (Figs. 18A, 18B), to be executed.
• the CPU upon the occurrence of an AC interrupt the CPU will first disable all interrupts and push its present register contents to the stack before executing step 1034. Also, prior to executing the return steps 1039, 1049 and 1056, described below, the stack must be popped to restore the register contents and the interrupts again enabled.
• the first step of the AC measurement program 1034 causes the CPU to take the current squared reading of all 32 lines running from the section switches to the groups of remote stations and this data is stored in a buffer.
• the CPU then proceeds to step 1036 where it increments an AC measurement interrupt counter and then proceeds to step 1038 where it tests whether the AC measurement counter is greater than 16. If not, the CPU pops the stack, enables the interrupts and returns and waits for the next AC interrupt which will again cause it to execute the "Check current transducer impedance" program which begins at step 1034. After this program has been executed 16 times, a yes decision will be produced at step 1038 causing the CPU to execute step 1042 which disables the AC measurement interrupts.
• the AC measurement interrupts are disabled by resetting V14EN of the Master Controller latch 601.
• the CPU After disabling the AC measurement interrupts, the CPU proceeds to step 1044 where it again enables the interrupts. Following this, the CPU 27 proceeds to step 1046 where it compares the lowest value stored in the buffer for each of the 32 lines with the data stored during calibration of the system. The lowest readings occur when the AC current is zero. Thus the lowest reading representing transducer output impedance amounts to nothing more than a DC resistance reading which is similar to other DC resistance readings previously described herein. A significant change in transducer impedance may occur by someone deliberately shorting, disconnecting or putting resistive or reactive components in parallel or in series with the current transducer in an attempt to make the system read a smaller current than is actually being consumed in the electrical path at a remote station. Accordingly, this portion of the program is designed to test for tampering or line faults.
• a tampering flag is set in step 1052. This flag is periodically monitored by a failure scan program to provide an indication of tampering. After the tampering flag is set, the CPU proceeds to step 1054 where it stores the section switch number, line number, unit number and voltage phase in a tampering buffer. This information can then be displayed along with location information to help identify a remote station which has been tampered with and to help in the repair process for a faulty line condition. After step 1054, the CPU pops the stack, enables the interrupts and returns in step 1056. If there was no significant change in the current transducer output impedance detected in step 1048, the CPU would also return in step 1049 after first popping the stack and enabling the interrupts.
• step 1066 the AC measurement path is enabled following which the address of a "Zero AC path offset" program is stored at NIPAD in step 1068. After this, the CPU returns in step 1070.
• step 1072 the sensor interrupt timer is set for nine milliseconds.
• step 1074 the AC measu rement path is disabled by resetting ACGRD and setting ACMEN at latch 373.
• step 1076 CPU 27 stores the address of the "Take and process AC power data" program at NIPAD following which it returns in step 1078.
• step 1094 When the next AC measurement interrupt occurs and at each AC measurement thereafter, a voltage multiplied by current reading is taken on all 32 lines and stored in a buffer by the CPU in a step 1094.
• step 1096 the AC measurement interrupt counter is incremented and in step 1098 the AC measurement interrupt counter is tested to see if its content is greater than 32. If not, the CPU returns following step 1098.
• the process of disabling interrupts, pushing the register contents to the stack at the beginning of the AC measurement program and popping the stack and enabling the interrupts before a return are all performed by CPU 27, although not shown in Figs. 18A . . . 18D.
• the operator interactive program 403 of Fig. 9 is illustrated in detail in Figs. 25A . . . 25M.
• This program is continuously executed by CPU 27 when it is not processing an interrupt program. It is used to extract and further manipulate processed data which has been provided by the sensor interrupt programs described above.
• a terminal operator is instructed to select either a "look" mode or a "maintenance” mode.
• the look mode is primarily designed to enable an operator to inspect the data acquired from individual remote stations, e.g. apartment units, while the maintenance mode performs various housekeeping and data processing functions. For the purposes of further description, it will be assumed that each remote station is located at an apartment unit of a building.
• step 1208 the CPU then proceeds to step 1214 where it performs the operations noted above for calculating the various memory addresses for the data requested corresponding to the S, L and U information.
• the configuration code for the input of S, L and U is also determined in the manner previously described.
• step 1220 the CPU proceeds to step 1222 where it determines if an operator has inputted a control signal instructing the CPU to proceed. If no control signal has been entered, the CPU proceeds to step 1223 where it waits for the next input sample of energy data for the apartment selected which occurs under master and sensor interrupt control as described earlier. When the next energy data sample arrives, the CPU returns to step 1218 where it recalculates energy use data using the new energy data samples.
• step 1224 (Fig. 25C) where it asks the operator if he wants to view the data for a new parameter. If yes, the CPU proceeds back to step 1216 and begins the sequence of steps described earlier.
• the flow rate data is multiplied by a cost factor to provide data representative of total water usage.
• the CPU then proceeds to step 1362 where it displays data corresponding to the rate of water usage as well as cost.
• the CPU Upon completing the calculation and display of water use in step 1362, the CPU then proceeds to the next step which is identical to step 1222 in Fig. 25B, being labeled 1222 in Fig. 25K.
• the WFR program operation proceeds as described above for the ELC program shown in Fig. 25B, so that description will not be repeated.
• step 1230 If during initial execution of step 1230, the CPU detects an input for ECAL, this routine will be entered at branching step 1246 to step 1252.
• the ECAL routine is designed to compare power calculated by the invention with an independent calibration meter having a very high degree of accuracy. The purpose of this is to determine the calibration scale factor described earlier. Any differences between power calculated by the system of the invention and power calculated by the calibration meter is set into the system as a calibration scale factor which is used by the system when calculating power consumed. In this manner, the system can be periodically calibrated to a high accuracy.
• the CPU prompts the operator to insert how many samples he wishes the calibration routine to extend over. Twenty samples would be typical. The samples correspond to the updating of the data samples which occurs during processing of the sensor interrupt routines described earlier. The number of samples input by an operator is stored as a value N. Following this, the CPU proceeds to step 1254 where it prints the apartment number, section line and unit numbers corresponding to the sensor and associated line path being calibrated. Also in step 1254, the CPU asks the operator whether calibration is desired for input phases A, B or C. In many cases, a three phase power line runs to an apartment and each may be separately calibrated. In some installations, only a single phase power line enters an apartment in which case the operator will only select that single phase for calibration in step 1254.
• step 1254 the CPU proceeds to step 1256 (Fig. 25F) where it prints the message to the operator to get ready to start the calibration meter. Then in step 1257 the CPU activates a tone generator which signals an operator to begin operation of the calibration meter. From there the CPU proceeds to step 1258 where it calculates and displays corrected and uncorrected power values for the phase selected by the operator in step 1254.
• the uncorrected power is that stored by the CPU during sensor interrupt processing which has not been corrected with the calibration scale factor.
• the corrected power calculation is effected by applying a calibration scale factor to the uncorrected power which was derived during a previous execution of an ECAL routine.
• step 1258 the CPU also prints the corrected and uncorrected power for the operator selected phase, e.g.
• step 1258 the CPU increments the sample counter in 1260 and in step 1262 determines whether the sample count is greater than the value entered by the operator in step 1252. If not, the CPU proceeds to a wait for the next sample at step 1263. In this step, the CPU determines when the next sample of power data is inputted into the system under the master and sensor interrupt processing routines. When the next data samples for power have been stored in the appropriate buffer registers, the CPU proceeds back to step 1258 where it updates the uncorrected and corrected power information for each of the values described previously. Steps 1258, 1260 and 1263 are continuously repeated until in step 1262 the CPU determines that the number of samples which have occurred exceeds that set by the operator at step 1252.
• step 1265 the CPU proceeds to step 1266 and 1268 (Fig. 25G) where it determines whether a "1", a "99", or a scale factor has been entered by the operator. If a "1" has been entered, the CPU proceeds from step 1266 to step 1272 where it prints the present calibration value. From there it proceeds to step 1276 where it asks the operator if he wishes to calibrate another phase. If the answer is yes, the CPU proceeds to step 1254 and repeats the ECAL routine for a different phase. If the operator does not desire to calibrate another phase, the CPU proceeds from step 1276 to step 1278 where it inquires if the operator wishes to calibrate the power lines for another apartment. If yes, the CPU proceeds from step 1278 to step 1234 (Fig.
• step 1280 the CPU then proceeds directly to step 1280 where it asks the operator if he wishes to have the new calibration data stored on disk. If yes, the CPU proceeds to step 1282 where it stores the new calibration data on a disk and from there returns to the beginning of the OIP program at step 1200 (Fig. 25A). If the new calibration data is not to be stored on disk, the CPU proceeds from step 1280 to the beginning of the OIP program at step 1200 (Fig. 25A).
• step 1266 determines that the operator input at step 1265 was not a "1"
• step 1268 determines if it was a "99". If not it proceeds to step 1270 where a scale factor calculated from the calibration meter reading which was entered by the operator in step 1265 is stored as a new scale factor to be used for subsequent calibration of incoming power data. From there the CPU proceeds to step 1272 where it executes steps 1272, 1276, 1278, 1280 and 1282 (Fig. 25G) in the manner described above.
• step 1284 the CPU consults the apartment index and identifies the apartment number associated with the input S, L and U information following which in step 1288 the CPU asks the operator if he wants another apartment number from available S, L and U information. If not, this routine returns to the entry point step 1200 (Fig. 25A) of the OIP program. If in step 1288 the operator indicates that an additional apartment number is desired, the CPU proceeds back to step 1284 where it requests new S, L and U information.
• step 1304 If as a result of step 1304 it is determined that an apartment index is to be input, the CPU proceeds to step 1310 (Fig. 251) of the apartment index input routine. There it prompts the operator to input an "I” if an apartment index is to be input or a "C” if a previously stored apartment index is to be corrected. Following step 1310, the CPU proceeds to steps 1312 and 1314 where it determines whether the operator has input an "I” or a "C".
• the CPU then assigns the inputted apartment number to the S, L and U numbers which were printed on the screen prior to the operator entered apartment number.
• the CPU then steps the section counter to a new value and displays new S, L and U numbers on the screen following which it awaits a new apartment number entry by the operator.
• the CPU then cycles through the section counter until it reaches its maximum value after which 16 S, L and U numbers will have been assigned to 16 entered apartment numbers by the operator.
• the CPU increments the line counter and resets the section counter to zero and repeats the process for the next 16 apartment entries until the section counter again reaches its maximum. After this the unit counter is incremented and the section and line counters reset to zero. After the next 32 entries, the unit counter is again incremented.
• step 1232 another operator selected input mode is TIME. If this is selected, at step 1232 the CPU branches to a TIME routine where in step 1332 (Fig. 25L) it reads a real time clock and prints the present time after which it returns to the beginning of the OIP program, step 1200 (Fig. 25A).
• Another maintenance mode input command is TIME SET and if this is selected in step 1230 by an operator the CPU proceeds to a TIME SET routine (Fig. 25L) where it prompts an operator to enter the present time which the CPU then sets into the system real time clock. After this, the CPU returns to step 1200 of the OIP program.
• step 1230 Another input mode co ⁇ mand which an operator can select at step 1230 is DATE.
• the CPU reads the present month, day and year from the system clock and displays it to the operator. After this, the CPU returns to step 1200 of the OIP program.

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• 1981
  • 1981-06-09 US US06/272,011 patent/US4415896A/en not_active Expired - Lifetime
• 1982
  • 1982-05-27 EP EP19820902139 patent/EP0080504A4/de not_active Withdrawn
  • 1982-05-27 WO PCT/US1982/000727 patent/WO1982004492A1/en not_active Application Discontinuation
  • 1982-06-04 CA CA000404493A patent/CA1196406A/en not_active Expired

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