WO1982003919A1 - Ultrasonic rail testing system - Google Patents

Ultrasonic rail testing system Download PDF

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Publication number
WO1982003919A1
WO1982003919A1 PCT/US1982/000566 US8200566W WO8203919A1 WO 1982003919 A1 WO1982003919 A1 WO 1982003919A1 US 8200566 W US8200566 W US 8200566W WO 8203919 A1 WO8203919 A1 WO 8203919A1
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WO
WIPO (PCT)
Prior art keywords
improvement
pulse
counting
ultrasonic
transducer
Prior art date
Application number
PCT/US1982/000566
Other languages
French (fr)
Inventor
Ind Inc Automation
Frank X Linder
Ronald M Keenan
Original Assignee
Ind Inc Automation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ind Inc Automation filed Critical Ind Inc Automation
Priority to BR8207680A priority Critical patent/BR8207680A/en
Priority to AU85277/82A priority patent/AU8527782A/en
Publication of WO1982003919A1 publication Critical patent/WO1982003919A1/en

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N29/00—Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic waves; Visualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object
    • G01N29/36—Detecting the response signal, e.g. electronic circuits specially adapted therefor
    • G01N29/38—Detecting the response signal, e.g. electronic circuits specially adapted therefor by time filtering, e.g. using time gates
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N29/00—Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic waves; Visualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object
    • G01N29/04—Analysing solids
    • G01N29/12—Analysing solids by measuring frequency or resonance of acoustic waves
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N29/00—Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic waves; Visualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object
    • G01N29/22—Details, e.g. general constructional or apparatus details
    • G01N29/30—Arrangements for calibrating or comparing, e.g. with standard objects
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N29/00—Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic waves; Visualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object
    • G01N29/34—Generating the ultrasonic, sonic or infrasonic waves, e.g. electronic circuits specially adapted therefor
    • G01N29/348—Generating the ultrasonic, sonic or infrasonic waves, e.g. electronic circuits specially adapted therefor with frequency characteristics, e.g. single frequency signals, chirp signals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N29/00—Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic waves; Visualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object
    • G01N29/44—Processing the detected response signal, e.g. electronic circuits specially adapted therefor
    • G01N29/4445—Classification of defects
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N2291/00—Indexing codes associated with group G01N29/00
    • G01N2291/04—Wave modes and trajectories
    • G01N2291/044—Internal reflections (echoes), e.g. on walls or defects
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N2291/00—Indexing codes associated with group G01N29/00
    • G01N2291/26—Scanned objects
    • G01N2291/262—Linear objects
    • G01N2291/2623—Rails; Railroads

Definitions

  • the field of this invention is the automatic ultrasonic testing of railroad rails in track.
  • a suitable electromechani- cal transducer such as a piezoelectric crystal, is en ⁇ ergized by a short electrical pulse or wave train of radio frequency called a "ping. " The crystal is thereupon caused
  • This echo signal is received by the same or a different transducer, which thereupon generates an electrical echo signal. Proper gating, timing, and counti circuits are then employed to evaluate the size of the defect, its location, and various other factors.
  • a wheel search unit is basically a liquid-filled rubber tire which rolls along the surface of the rail and contains the necessary trans ⁇ ducers, thus presenting a liquid path from the transducers to the surface of the rail.
  • Rail rails contain a number of ultrasoni discontinuities not caused by flaws, such as bolt holes, bond pin holes, and the ends of the rails themselves. The are in close physical juxtaposition at or near the end of each rail. Moreover, some of the kinds of defects sought are most likely to occur near rail ends because of the stresses imposed by relative motion between adjacent rails. These facts cause the rate at which data is received by automatic systems to have a very high value near rail ends.
  • the running surface of the rail presents a number of variables, such as wear, grease, rust, ice, leav and other foreign objects, which affect the coupling be-
  • Methods which have been employed to overcome t problem of high data rate include: (a) use of time gat to reject echoes from regions seldom, if ever, associate with defects; (b) categorization of echoes according to amplitude and rejection of those falling outside a speci ⁇ fied range; (c) comparison of incoming signals with pre specified "masks", or patterns supposed to represent typi cal defects or combinations thereof; (d) buffering techniques to reduce the ratio of peak to average data rate for processing; and (e) parallel processing of data from different transducers.
  • the objects of the present inventi are to provide an automatic rail-testing system capable o making immediate defect classification decisions based on data received at high peak rates, automatically adaptable to minor changes in operating parameters, and quickly and easily adjustable to compensate for major variations in operating parameters.
  • a highly flexible ultrasonic testing system includes two pulse sources. One source is responsive t the speed of the testing car and generates trigger pulses at a rate proportional to the car speed. The other source is a system clock which generates pulses at a preselected constant rate. A plurality of ultrasonic transducers are actuated in response to the trigger pulses. The pulse ech information from the transducers is operated upon by circu units which are responsive to the generated pulses and in ⁇ clude data storage capability. The formation of these uni may be altered by means of a microprocessor. In this man ⁇ ner, defect indications are stored and classified and acti- vate suitable alarm indications.
  • FIG. 1 is a simplified functional diagram of a two channel system in accordance with the present invention
  • FIG. 2 is a block diagram of a sequencer as em- ployed in the system of FIG. 1;
  • FIG. 3 is a block diagram of a coherence circuit as employed in the system of FIG. 1;
  • FIG. 4 illustrates a pair of wheel search units o a section of rail under test
  • FIG. 5 is a diagram of the flag field portion of computer memory, with its inputs
  • FIG. 6 is a flow chart of exemplary logic which might be employed to evaluate rail defects.
  • the invention is concerned with improving the performance of transducers and the automatic high-speed processing of data from a plurality of such transducers.
  • the design, number, and arrangement of transducers in each wheel search unit and the number of search units do not form a part of this invention.
  • channel refers to a transducer which receives echo signals and the data- processing functions associated with that transducer, whether the transmitted signal originated with that trans ⁇ ducer or another.
  • the word "sequencer” is employed for a de ⁇ vice which will be described in detail, infra. It includes: (1) a clock, to generate a pulse train at a controlled rate;
  • a counter which counts clock pulses beginning at a time controlled by an external event and ending when the counter has reached full scale or some other predetermined value
  • FIG. 1 illustrates a simplified two-channel embodiment.
  • the ultrasonic transmitting and receiving functions are performed by co- herence circuits 10 and 10* . When employed for testing rails, these functions may be performed through the use of liquid filled tires T, T' rolling along the rail R, as shown in FIG. 4.
  • the transmitting function is initiated by a trigger generator 12, which may be a tachometer, shaf encoder, or other means of producing electrical impulses at intervals corresponding to distance travelled along the track. For example, in one embodiment a pulse is generate each 1/6 inch of travel. Each impulse from the trigger generator initiates a cycle of activity in a channel se- quencer 14.
  • the channel sequencer is preloaded with ins ⁇ tructions from a microprocessor 16 by means of a parallel data and address bus 18. Its two functions are: (1) to initiate operation of the coherence circuits, and (2) to alter the state of a gain sequencer 20, both at precise times depending on the instructions in the channel se ⁇ quencer and count of a system clock 22.
  • the mode of oper ⁇ ation of the channel sequencer 14, the coherence circuits 10, 10*, and the gain sequencer 20 will be described in de tail later. Their joint effect is to cause ultrasonic sig nals to be transmitted at times selected by channel se ⁇ quencer 14 and received at later times determined by the location of discontinuities in the rail, with receiver gains at all times determined by the gain sequencer 20.
  • the signals received by the coherence circuits are preloaded with ins ⁇ tructions from a microprocessor 16 by means of a parallel data and address bus 18. Its two functions are: (1) to initiate operation of the coherence circuits, and (2) to alter the state of a gain sequence
  • the pur ⁇ pose of the interface sequencer 24 is to establish a time reference based on the time a wheel/rail interface echo wa received in a previous calibration cycle.
  • the purpose of gate sequencers 26, 26' is to establish range gates, re ⁇ ferred to the time reference from the interface gate and based on echo data obtained in a previous calibration cycl
  • These sequencers also communicate with the microprocessor 16 by means of the address and data bus 18 for the purpose of preloading the interface time and range gate times de ⁇ sired.
  • a trip bit i output to an area of computer memory called a flag field 28.
  • the address to which the bit is sent depends upon which gate sequencer originated the trip.
  • a second trip signal is output to a range counter 30 or 30*.
  • the range counters preferably include microprocessors as discussed be low. In addition, however, each range counter includes a high-speed counter which counts pulses from system clock 22, beginning at a channel time reference supplied by inter face sequencer 24 and ending on receipt of a trip signal
  • the range counter associated with that address contains a count proportional to the distance from the surface of the rail to the discontinuity which produced the trip in the gate sequencer.
  • the count stored in each range counter is. accessible to the microprocessor 16 b way of the address and data bus 18.
  • the range counter itself may also output a second trip bit to the flag field 28 under circumstances described below.
  • the data output of each channel is presented to the microprocessor 16 as the stored range count in counter 30, 30' and the presence or absence of one or more bits in the flag field 28.
  • the flag field and the range counters are reset at each "ping" by lines 32 and 34 respectively, so data are always current.
  • Operation of the micropro ⁇ cessor 16 is controlled by programs stored in a read-only memory (ROM) 36 and a random-access memory (RAM) 38. The latter is also used for temporary storage of data.
  • the microprocessor 16 communicates by means of lines 40 with various peripheral devices, such as a data terminal, output display, and various annunciation functions, whose details are well known to those skilled in the art and outside the scope of this invention. Special instructions, such as pro gram modifications or the initiation of specialized oper ⁇ ating sequences, may be introduced through the data termina
  • the microprocessor employs combinatory logic to deduce rail condition from the combination of trip bits and range counts available to it.
  • the details of this logic depend on transducer number and arrangement, rail test cri ⁇ teria, and other factors. It is readily deterrainable by those skilled in the art and an example is set forth below. It is not necessary that all the functions be performed by a single microprocessor. So long as they employ compatible data/address formats and are properly synchronized by the common system clock, any number may be employed at the convenience of the designer.
  • FIGURE 2 is representative of the several types of sequencer used in this system.
  • a flip-flop 42 is set by a trigger signal on line 44 to enable an AND-gate 46. This allows impulses from system clock 22 to input seriall to a counter 48 by way of line 50. As the counter advance its parallel outputs select consecutive addresses in a memory unit 52.
  • thi memory unit may be a read-only memory, because the content of this sequencer are seldom changed.
  • the other types of sequencers incorporate read/write (RAM) memory because their contents are frequently changed.
  • FIGURE 2 illustrates a 4-channel RAM system. Th four Channel Input/Output lines are connected to the data bus 18 of the microprocessor 16 through bi-directional buf fers (not shown) . A particular sequencer is identified to the microprocessor by assigning a particular port number o memory address to that sequencer. In the calibration mode the microprocessor can enter a sequence of 256 binary num- bers into the memory element, or read a sequence of 256 binary numbers from it.
  • each channel input/output is connected to some other element of the system that is to be actuated at a particular time.
  • each output line goes to the trig ⁇ ger input of a different gate sequencer 26, 26* .
  • there may be only a single output line from a
  • each output line goes to the trigger input of one or more coherence circuits 10, 10'.
  • the sequencer advances, address by address in accordan with the counter output, the presence of a binary 1 in a given bit position causes a positive voltage output to th device associated with that bit position at the precise t when the counter calls up the address where the bit is pre sent.
  • One embodiment of the syste employs a 0.5 MHz clock and memory units 8 bits wide and 256 addresses long. Such a sequencer provides 8 different outputs at 2 microsecond intervals over a period 512 micro seconds long. These are used for such purposes as firing ' the ultrasonic transducers, setting receiver gain at parti cular times, sending out a channel interface reference sig nal, defining range gates, and starting and resetting counters. ⁇
  • the gain sequencer 20 operates in the same manne but its outputs are used differently.
  • the output lines of the gain sequencer go to a digital-to-analog converter 54 (FIG. 1) whose output sets the gain of the receivers.
  • a 4-channel gain sequencer would provide 1 of 16 possible voltages, in accordance with a preset program, each time it is advanced by an output from the channel sequencer 14.
  • channel sequencer 14 determines when receiver gain is to be changed, and gain sequencer 20 determines which of 16 possible values is to be implemented at that time.
  • the gate sequencers only, also incorporate coin ⁇ cidence detectors — the AND-gates 56, 58, 60, 62 in FIG. 2
  • sequencers employing R memory can also be used to store time-dependent data. If each of the input/output lines of the interface sequencer 24 is connected to the output of a different coherence cir cuit 10, 10' , the presence or absence of an echo return in each time slot of each search unit can be recorded in the sequencer memory. This data can be accessed by the micro ⁇ processor 16 for display or other action in the calibratio process.
  • FIGURE 3 shows the essential elements of a co ⁇ herence circuit, so called because the received signal is correlated with the waveform of the transmitted signal on a cycle-by—cycle basis. This largely eliminates ultrasoni "noise” and can be used to eliminate crosstalk between dif ferent transducers.
  • the coherence circuit operates as follows.
  • a flip-flop 66 Before receipt of a ping command from the channe sequencer, a flip-flop 66 is in RESET state. The resultin negative voltage on line 68 holds counters 70 and 72 in a CLEAR state and flip-flop 74 in a RESET state. Receipt of the ping command sets flip-flop 66, which enables the two counters, flip-flop 74, and two tri-state core drivers 76 and 78. Counter 70 then counts the output of a high-fre ⁇ quency clock 80. This clock operates at a frequency which is an integral multiple of the desired ultrasonic transduce
  • ⁇ £ output frequency In the example shown, it operates at 8 times the transducer output frequency.
  • Counter 70 is used as a frequency divider. One output at 1/4 clock frequency toggles flip-flop 74 at the beginning of each half-cycle of the transducer output fre quency. The other.output at 1/8 clock frequency advances counter 72. The two outputs of flip-flop 74 alternately actuate core drivers 76 and 78, which drive an ultrasonic transducer crystal 82 at the desired frequency. Counter counts complete cycles of the transducer frequency.
  • Switches 84 allow a number from 0 to 15 to be preset into counter 72. It will therefore reach full scale when the transducer has generated 1 to 16 cycles, depending on the setting of switches 84. When counter 72 reaches full sca it resets flip-flop 66, terminating the transmission. Th effect of these provisions is to cause the ultrasonic tra ducer 82 to produce a predetermined number of cycles of a ultrasonic wave, whose frequency is precisely determined the high-frequency clock 80 rather than by the natural re- sonance of transducer 82.
  • ultrasonic echoes are converted into electric waves by transducer 82. These are amplified by an amplifier 86, whose gain is set the gain sequencer 20 as previously described. Additional fixed gain can be provided by an amplifier 88 if needed.
  • the amplifiers 86, 88 drive the serial input of a register 90. This may be a conventional serial-in-parallel-out shi register or a charge-coupled, analog delay line. (The term "register” is so defined as used in the appended claims.) Register 90 is clocked by high-frequency clock 8
  • the incoming signal is clocked through the register at 8 times the transmitted frequency. This is th same as 8 times the received frequency except for doppler shift, which is negligible in this application. If a tap is provided at every fourth stage of the register 90, the incoming signal can be sampled at time intervals corres ⁇ ponding to each half-cycle of the signal wave. The number of taps required depends on the number of transmitted cycl 5 which was set by switches 84. The example shown assumes that four cycles were selected by the switches.
  • register 96 may receive a negative signal for fewer than four clock cycles.
  • the combination of a NOR-gate 98 and a switch 100 provides a positive output to a one-shot mult vibrator 102 when either two or three consecutive clock 0 cycles produce a negative output from gate 92.
  • each range counter 30, 30* counts the system clock 22 from its channel reference time until interrupted by a pulse from its coherent searc unit 10, 10* which coincides with a range gate in its gat sequencer 26, 26*.
  • the parallel output of the counter is accessible to the microprocessor 16 as a memory (or port) address. In addition it performs a simple arithmetic tes In rail testing it is useful to be able to dis ⁇ tinguish between "walking" and fixed echoes. Rail ends an transverse rail defects decrease in range as the test whee approaches them, while the return from a horizontal defect the bottom of the rail, and some kinds of reverberations maintain approximately constant range once detected.
  • the rate of change of a walking echo is proportional to the test car speed and the sine of the angle of incidence of the ultrasonic beam.
  • the angle of incidence for any parti cular channel is fixed, but in general will be different for different channels. Therefore, it is convenient to pr vide in each range counter means for detecting the charac ⁇ teristic range rate of that channel and sending an additio al flag bit to the flag/interrupt memory area whenever it is detected. This is done by temporarily storing each ran count and subtracting it from the range count of the next ping (or vice versa) . If the difference falls between pre set limits depending on the angle of incidence of that channel, the flag bit is sent out. This permits the O O
  • a preferred embodiment employs a separate single-chip micro ⁇ processor to perform the functions of each range counter.
  • the preferred type of microprocessor for range-counter use comprises an arithmetic/logic module, random-access memory and electrically programmable read-only memory (EPROM) .
  • EPROM electrically programmable read-only memory
  • the programmability afforded by the use of micro processors in the range counters is advantageous because it permits range counters of common design to be used in different ways in di erent channels or in special cir ⁇ cumstances. For example, a channel whose transducer is directed vertically downward (transducer 82v, FIGURE 4) wi seldom if ever encounter walking echoes of the kind des ⁇ cribed above. It will encounter sudden changes in echo range caused by bolt holes and horizontal defects. For vertical channels, therefore, it may be preferable to pro ⁇ gram the range counter to compare the current range count with a ixed reference rather than with the count of the previous ping.
  • the flag field memory area 28 is similar to the general random access memory 38 except that some additional logic is provided. The purpose of this logic is to cause
  • ⁇ 4-_ WIPO an interrupt of the microprocessor 16 in a selected case such as: (1) if one or more flags has been stored in the current operating cycle; (2) if no flag has been stored in the current operating cycle; or (3) if a condition is detected which indicates malfunction of the system.
  • the interrupt if used, is enabled by a channel of one of the sequencers at an address near the end of its operating cycle. It is not necessary to employ the interrupt capa ⁇ bility, but it affords flexibility to the programmer in designing an operating system.
  • the leading wheel T contains three tran ducers, each capable of both transmission and reception.
  • One of these, 82v is directed vertically downward along th axis labelled “VERT”; one, 82w is directed along the axis "WEB” at an angle of incidence of about 45°; and one, 82h i directed along the axis "HEAD,” at about 75°.
  • the vertical 82v and web 82w transducers are over the center of the rail so that signals can be sent through the rail and reflected from the discontinuity at the rail bottom.
  • the head trans ⁇ ducer 82h need not be over the center, since it is concerne only with signals in the rail head.
  • the trailing wheel con tains a transducer 82w' which receives the bottom-reflected WEB signal. It also contains a pair of transducers, one of which 82z is shown, which pass a signal diagonally across the head of the rail. This pair is labelled the "Z" channe Details of the Z channel will be found in copending appli ⁇ cation S.N. , filed by George D. Martens and assigned to the same assignee as the present application. The disclosure of that application is incorp rated herein by reference.
  • the vertical channel has five range gates which distinguish the following regions of the rail:
  • the web channel has two range gates: a BH gate covering * i bolthole region, and a THRU gate allowing recognition by the transducer 82w* in the trailing wheel of the signal re ⁇ flected by the rail bottom.
  • the head channel has a single wide gate covering the entire region of the "HEAD" dashed arrow in FIG. 4.
  • the Z-channel has ' only a THRU gate, en ⁇ abling reception of the through-transmission from one trans ducer 82Z to the other of the Z-pair.
  • the head channel is configured to recognize only "walking" echoes (see “Range Counter” above) .
  • the vertical and web channels respond to all kinds of echoes.
  • the Z-channel responds only to inter ⁇ ruption of the normally present through-signal by a rail end, split head, or other large head discontinuity.
  • a separate trip line from each gate of each transducer goes to a different bit position of that portion of the computer's random-access memory called the flag field 28.
  • the flag field 28 begins at (decimal) address 100 and ends at address 164.
  • the presenc or absence of each of the nine-trip bits here considered i written into its proper bit position.
  • the memory address is then incremented by 1. This process is repeated until data has been stored- at address 164, whereupon the address register is reset to 100.
  • the data associated with any ping number P is stored at address K + P MOD 64, where K is the starting address of the flag field (in this case 100) and P MOD 64 signifies P (modulo 64) in the nota ⁇ tion of congruence arithmetic.
  • K + P MOD 64 is addressed for current data and K +(P - N) MOD 64 is addressed for data stored N pings ago.
  • N is generally the channel offset.
  • Individual bits are selected for attentio by a programmed Boolean AND operation in the computer. For example, suppose it is desired to know whether a signal was present in the bolthole gate of the web channel 15 pings ago. The required data will be found at bit position 2 of address 100 +(P-15) MOD 64. The system's ping counter furn ⁇ ishes P; the computer program furnishes the constant 15 an the algorithm for "MOD 64." The.
  • This exemplary system identifies arid classifies rail defects according to the presence of certain combin- ations of nine "flags.”
  • a flag is defined as a “set” or binary 1 condition in a particular bit in a special flag register (or memory address) .
  • a flag is set whenever a specified trip bit is observed for D consecutive pings in a specified channel offset "window" defined by the limits Wl and W2. The table below defines the flags used in this
  • Flag A is set whenever the HEAD WALK trip bit is found to be "1" for any 8 consecutive pings of the last 30.
  • Flag B is set if 8 of the 9 Z-channel trip bits at addresses (P - 56) to (P - 64) are "1.”
  • Flag H is set if 10 of the last 11 VERT-channel BH trip bits are set, and so on.
  • FIGURE 6 is a flow chart of a computer routine that tests for these logic combinations.
  • the notation "B?” means "is the B flag set?".
  • the program first tests for presence of both the B and C flags to determine whether a rail end is present. Although a ra end is not a defect, its presence would veto a possible HD diagnosis and therefore must be determined. If either B o C is not present, an additional flag RE (not rail end) is set for later reference.
  • the program tests for presence of both D and H. If both are present, "bolthole crack” is diagnosed and output for appropriate action. If one or both are missing, block 6 tests for the presence of E, the alternative indication of BHC. If E is present, "bolthole crack” is diagnosed and output. If not, the flag BHC (not bolthole crack) is set for later refer ⁇ ence.
  • Block 9 permits omission of the head-defect sequence 10-14 if a rail end has been found in 1 and 2. Otherwise, the ' program tests for A or F or B-and-not-D and outputs "head defect" if any of these are found. Then it proceeds to the final sequence 15-19 to test for web defects in similar manner.
  • the program exits at block 20 to perform other functions, such as loading data from the next ping into the flag field 28, and then repeats for the next ping.
  • interface sequencer 24 Read the contents of interface sequencer 24 into microprocessor 16 and display on data terminal, or per form equivalent automatic action. 4. Identify the interface time for each channel from known track geometry and time and order of returns. 5. Identify normally present echoes for each channel, such as rail bottom, direct transmission from one transducer to another, and bolthole returns. 6. Identify spurious returns, such as reverbera ⁇ tions.
  • An advantage of a microprocessor-controlled system is the variety of self-test and diagnostic proce ⁇ dures that can be incorporated in program routines. Like calibration, these can be called manually, at regular in ⁇ tervals, or on occurrence of anomalous events. Details of such self-test routines are system dependent and outside the scope of this description.
  • RAM 38 MM257
  • Microprocessor 16 MC6800L
  • Gain Sequencer 20 Gain memory HM6551-9
  • Divider 70 74LS161 a 74LS74 Pulse train div. 72 74LS193

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Abstract

A highly flexible ultrasonic testing system, especially well suited for testing railroad rail in track from a testing car. It includes two pulse sources (12) and (22), one (12) generating trigger pulses at a rate proportional to car speed, the other (22) generating pulses at a constant rate. A plurality of ultrasonic transducers (82v), (82h), (82w), (82w<1>) and (82z) are actuated in response to the trigger pulses. The information from the transducers is operated upon by circuit elements which are responsive to the generated pulses and include data storage capability. These elements may be altered by means of a microprocessor (16). With this system, defect indications are stored and classified and caused to activate suitable alarm indications.

Description

ULTRASONIC RAIL TESTING SYSTEM
Technical Field
The field of this invention is the automatic ultrasonic testing of railroad rails in track.
Reference may be had to an appendix filed here- with and made a part hereof. It is a program listing used in a simulation of the disclosed system on an IBM 3033 computer. It operates on data magnetically recorded from actual rail to evaluate the effectiveness of various com¬ binations of criteria in detecting and classifying rail de- fects. It is written in PL/I language.
Background Art
The inspection of solid materials by means of the ultrasonic echo reflection technique is widely known and applied in inspection systems. A suitable electromechani- cal transducer, such as a piezoelectric crystal, is en¬ ergized by a short electrical pulse or wave train of radio frequency called a "ping. " The crystal is thereupon caused
OMPI e -"~. WH>0 to vibrate, producing a mechanical wave of ultrasonic fre¬ quency which is passed into the material to be inspected. Any discontinuity within the test object reflects the mechanical wave. This echo signal is received by the same or a different transducer, which thereupon generates an electrical echo signal. Proper gating, timing, and counti circuits are then employed to evaluate the size of the defect, its location, and various other factors.
When testing rails in track by an ultrasonic system, it is customary to couple the transducers to the rail by means of a wheel search unit. A wheel search unit is basically a liquid-filled rubber tire which rolls along the surface of the rail and contains the necessary trans¬ ducers, thus presenting a liquid path from the transducers to the surface of the rail. It will of course be obvious that one of the ultimate objectives in rail testing is to test rails automatically and at high speed. This objectiv has not been fully achieved with previous rail-testing systems for a number of reasons. These may be summarized as follows:
1. Railroad rails contain a number of ultrasoni discontinuities not caused by flaws, such as bolt holes, bond pin holes, and the ends of the rails themselves. The are in close physical juxtaposition at or near the end of each rail. Moreover, some of the kinds of defects sought are most likely to occur near rail ends because of the stresses imposed by relative motion between adjacent rails. These facts cause the rate at which data is received by automatic systems to have a very high value near rail ends.
2. The running surface of the rail presents a number of variables, such as wear, grease, rust, ice, leav and other foreign objects, which affect the coupling be-
"fcURE OMPI tween the search wheel and the interior of the rail and cause the amplitude of reflections to vary over a wide range.
Methods which have been employed to overcome t problem of high data rate include: (a) use of time gat to reject echoes from regions seldom, if ever, associate with defects; (b) categorization of echoes according to amplitude and rejection of those falling outside a speci¬ fied range; (c) comparison of incoming signals with pre specified "masks", or patterns supposed to represent typi cal defects or combinations thereof; (d) buffering techniques to reduce the ratio of peak to average data rate for processing; and (e) parallel processing of data from different transducers.
Though these means have considerable effective¬ ness, especially in combination, no fully successful auto matic rail testing system has been realized for a number of reasons.
a. The effective use of time gates requires that they be adjusted within narrow limits, or they will unacceptably decrease the probability of detecting defect near the part of the rail rejected by the gates. Because of differences in age, composition, wear, etc., between individual rails, maintenance of narrow limits imposes a requirement for frequent recalibration which has not been operationally feasible.
b. The use of amplitude classification has had limited success, not only because of the variability of rail surface coupling but also because a small change in orientation of a crack can cause a large change in the amplitude of its reflection in a particular direction. A lowance for this variability causes amplitude classes to become so broad as to be meaningless.
c. Variability in rail size and shape, and the complexity of defect patterns that arise in real rail, ma the prespecificatipn of defect patterns an impracticable task.
d. The use of buffering is acceptable in off¬ line systems that record track data for later analysis, but is not satisfactory in real time systems that require immediate defect identification. Such systems are con¬ strained by the peak, rather than the average, data rate.
e. Parallel processing has been successfully used, but the problem is how to combine the output of numerous processors in real-time defect classification. Experience has shown that human interpreters are unable to keep up with the peak rail-end data rate, and no practi cable computer-based system has been proposed.
More success has been attained in coping with surface coupling variability. Good results have been ob¬ tained with systems which use a combination of (a) gain which increases uniformly and periodically after each transmitted pulse in order to compensate for the decrease in strength of returns from increasingly distant dis- continuities, and (b) non-periodic automatic gain control derived from "track noise," the strength of the wheel/rail discontinuity reflection, or some other parameter that can be correlated with wheel-to-rail coupling. Experience has shown, however, that the uniformly increasing gain of (a) is not necessarily optimum. It would be better to be
"fcURE O PI able to vary the gain periodically in an arbitrary manner in order to emphasize certain time slots (and their dis¬ tance analogues) and de-emphasize others.
Accordingly, the objects of the present inventi are to provide an automatic rail-testing system capable o making immediate defect classification decisions based on data received at high peak rates, automatically adaptable to minor changes in operating parameters, and quickly and easily adjustable to compensate for major variations in operating parameters.
Disclosure of Invention
In accordance with the present invention, there is provided a highly flexible ultrasonic testing system. It includes two pulse sources. One source is responsive t the speed of the testing car and generates trigger pulses at a rate proportional to the car speed. The other source is a system clock which generates pulses at a preselected constant rate. A plurality of ultrasonic transducers are actuated in response to the trigger pulses. The pulse ech information from the transducers is operated upon by circu units which are responsive to the generated pulses and in¬ clude data storage capability. The formation of these uni may be altered by means of a microprocessor. In this man¬ ner, defect indications are stored and classified and acti- vate suitable alarm indications.
OMPI BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a simplified functional diagram of a two channel system in accordance with the present invention FIG. 2 is a block diagram of a sequencer as em- ployed in the system of FIG. 1;
FIG. 3 is a block diagram of a coherence circuit as employed in the system of FIG. 1;
FIG. 4 illustrates a pair of wheel search units o a section of rail under test; FIG. 5 is a diagram of the flag field portion of computer memory, with its inputs; and
FIG. 6 is a flow chart of exemplary logic which might be employed to evaluate rail defects.
BEST MODE FOR CARRYING OUT THE INVENTION The invention is concerned with improving the performance of transducers and the automatic high-speed processing of data from a plurality of such transducers. The design, number, and arrangement of transducers in each wheel search unit and the number of search units do not form a part of this invention.
In the following description of the invention, reference will be made to systems having different numbers of "channels." In this context, the word "channel" refers to a transducer which receives echo signals and the data- processing functions associated with that transducer, whether the transmitted signal originated with that trans¬ ducer or another.
Also, the word "sequencer" is employed for a de¬ vice which will be described in detail, infra. It includes: (1) a clock, to generate a pulse train at a controlled rate;
(2) a counter, which counts clock pulses beginning at a time controlled by an external event and ending when the counter has reached full scale or some other predetermined value;
(3) a digital memory, whose consecutive locations are ad- dressed by a parallel output from the counter; (4) means for entering digital data from a common source or from dif¬ ferent sources, independently to each bit location
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W- W WIIPP \ of a memory address as that address is called by the counter; and (5) means for extracting the contents of eac bit location of a memory address as that address is calle by the counter and sending the bits to a common destinati or independently to different destinations. In addition, sequencer may contain coincidence gates, which direct bit to different locations when an external event coincides i time with particular bits in the current memory address. The figures illustrating this invention are functional diagrams, in which closely related functions are grouped in blocks. It is recognized that an actual e bodiment may physically separate functions which are grouped in these figures and that physical modules may gr different functions at the convenience of the designer. Although the invention is not limited in number of channels, FIG. 1 illustrates a simplified two-channel embodiment. It employs two transducers, each of which is used for both transmitting and receiving. The ultrasonic transmitting and receiving functions are performed by co- herence circuits 10 and 10* . When employed for testing rails, these functions may be performed through the use of liquid filled tires T, T' rolling along the rail R, as shown in FIG. 4. The transmitting function is initiated by a trigger generator 12, which may be a tachometer, shaf encoder, or other means of producing electrical impulses at intervals corresponding to distance travelled along the track. For example, in one embodiment a pulse is generate each 1/6 inch of travel. Each impulse from the trigger generator initiates a cycle of activity in a channel se- quencer 14. The channel sequencer is preloaded with ins¬ tructions from a microprocessor 16 by means of a parallel data and address bus 18. Its two functions are: (1) to initiate operation of the coherence circuits, and (2) to alter the state of a gain sequencer 20, both at precise times depending on the instructions in the channel se¬ quencer and count of a system clock 22. The mode of oper¬ ation of the channel sequencer 14, the coherence circuits 10, 10*, and the gain sequencer 20 will be described in de tail later. Their joint effect is to cause ultrasonic sig nals to be transmitted at times selected by channel se¬ quencer 14 and received at later times determined by the location of discontinuities in the rail, with receiver gains at all times determined by the gain sequencer 20. The signals received by the coherence circuits
10, 10' are transmitted to an interface sequencer 24, whic is common to all channels, and to individual gate se¬ quencers 26 and 26*, - peculiar to each channel. The pur¬ pose of the interface sequencer 24 is to establish a time reference based on the time a wheel/rail interface echo wa received in a previous calibration cycle. The purpose of gate sequencers 26, 26' is to establish range gates, re¬ ferred to the time reference from the interface gate and based on echo data obtained in a previous calibration cycl These sequencers also communicate with the microprocessor 16 by means of the address and data bus 18 for the purpose of preloading the interface time and range gate times de¬ sired.
If a signal from a coherence circuit coincides i time with a range gate in its gate sequencer, a trip bit i output to an area of computer memory called a flag field 28. The address to which the bit is sent depends upon which gate sequencer originated the trip. A second trip signal is output to a range counter 30 or 30*. The range counters preferably include microprocessors as discussed be low. In addition, however, each range counter includes a high-speed counter which counts pulses from system clock 22, beginning at a channel time reference supplied by inter face sequencer 24 and ending on receipt of a trip signal
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O PI fro its associated gate sequencer 26 or 26'. Therefore, if an address in the flag field 28 contains a trip bit, the range counter associated with that address contains a count proportional to the distance from the surface of the rail to the discontinuity which produced the trip in the gate sequencer. The count stored in each range counter is. accessible to the microprocessor 16 b way of the address and data bus 18. The range counter itself may also output a second trip bit to the flag field 28 under circumstances described below.
The data output of each channel is presented to the microprocessor 16 as the stored range count in counter 30, 30' and the presence or absence of one or more bits in the flag field 28. The flag field and the range counters are reset at each "ping" by lines 32 and 34 respectively, so data are always current. Operation of the micropro¬ cessor 16 is controlled by programs stored in a read-only memory (ROM) 36 and a random-access memory (RAM) 38. The latter is also used for temporary storage of data. The microprocessor 16 communicates by means of lines 40 with various peripheral devices, such as a data terminal, output display, and various annunciation functions, whose details are well known to those skilled in the art and outside the scope of this invention. Special instructions, such as pro gram modifications or the initiation of specialized oper¬ ating sequences, may be introduced through the data termina
The microprocessor employs combinatory logic to deduce rail condition from the combination of trip bits and range counts available to it. The details of this logic depend on transducer number and arrangement, rail test cri¬ teria, and other factors. It is readily deterrainable by those skilled in the art and an example is set forth below. It is not necessary that all the functions be performed by a single microprocessor. So long as they employ compatible data/address formats and are properly synchronized by the common system clock, any number may be employed at the convenience of the designer.
Reference has been made to a calibration cycle. This process will be easier to understand after more de- tailed description of some of the components, which follow
Sequencers
FIGURE 2 is representative of the several types of sequencer used in this system. A flip-flop 42 is set by a trigger signal on line 44 to enable an AND-gate 46. This allows impulses from system clock 22 to input seriall to a counter 48 by way of line 50. As the counter advance its parallel outputs select consecutive addresses in a memory unit 52. In the case of the channel sequencer, thi memory unit may be a read-only memory, because the content of this sequencer are seldom changed. The other types of sequencers incorporate read/write (RAM) memory because their contents are frequently changed.
FIGURE 2 illustrates a 4-channel RAM system. Th four Channel Input/Output lines are connected to the data bus 18 of the microprocessor 16 through bi-directional buf fers (not shown) . A particular sequencer is identified to the microprocessor by assigning a particular port number o memory address to that sequencer. In the calibration mode the microprocessor can enter a sequence of 256 binary num- bers into the memory element, or read a sequence of 256 binary numbers from it.
In the operating mode, each channel input/output is connected to some other element of the system that is to be actuated at a particular time. For example, in the interface sequencer 24, each output line goes to the trig¬ ger input of a different gate sequencer 26, 26* . In a gat sequencer, there may be only a single output line (from a
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O PI v< . W1P0 memory unit 52 having a 1 digit width) to serve as a trip to a rar,ge counter 30, 30' or the flag field 28 area. In the channel sequencer 14, each output line goes to the trigger input of one or more coherence circuits 10, 10'. As the sequencer advances, address by address in accordan with the counter output, the presence of a binary 1 in a given bit position causes a positive voltage output to th device associated with that bit position at the precise t when the counter calls up the address where the bit is pre sent. In the example shown, there will be no outputs on step 1, outputs on lines 0 and 2 in step 2, 1 and 2 in ste 3, 2 only in step 254, etc.
Use of high-speed system clock 22 permits precis timing throughout the system. One embodiment of the syste employs a 0.5 MHz clock and memory units 8 bits wide and 256 addresses long. Such a sequencer provides 8 different outputs at 2 microsecond intervals over a period 512 micro seconds long. These are used for such purposes as firing' the ultrasonic transducers, setting receiver gain at parti cular times, sending out a channel interface reference sig nal, defining range gates, and starting and resetting counters.■
The gain sequencer 20 operates in the same manne but its outputs are used differently. The output lines of the gain sequencer go to a digital-to-analog converter 54 (FIG. 1) whose output sets the gain of the receivers. A 4-channel gain sequencer would provide 1 of 16 possible voltages, in accordance with a preset program, each time it is advanced by an output from the channel sequencer 14. Thus channel sequencer 14 determines when receiver gain is to be changed, and gain sequencer 20 determines which of 16 possible values is to be implemented at that time.
The gate sequencers only, also incorporate coin¬ cidence detectors — the AND-gates 56, 58, 60, 62 in FIG. 2
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<* ->. WHO These generate coincidence trips on lines 0', 1' , 2*, and 3' when a signal on an external event line 64 coincides wi a range-gate enable bit in the memory output. The externa event line 64 comes from the coherence circuit 10, 10* out put, and the coincidence outputs go to range counters 30, 30' and the flag field 28.
It should'be evident that sequencers employing R memory can also be used to store time-dependent data. If each of the input/output lines of the interface sequencer 24 is connected to the output of a different coherence cir cuit 10, 10' , the presence or absence of an echo return in each time slot of each search unit can be recorded in the sequencer memory. This data can be accessed by the micro¬ processor 16 for display or other action in the calibratio process.
Coherence Circuit
FIGURE 3 shows the essential elements of a co¬ herence circuit, so called because the received signal is correlated with the waveform of the transmitted signal on a cycle-by—cycle basis. This largely eliminates ultrasoni "noise" and can be used to eliminate crosstalk between dif ferent transducers. The coherence circuit operates as follows.
Before receipt of a ping command from the channe sequencer, a flip-flop 66 is in RESET state. The resultin negative voltage on line 68 holds counters 70 and 72 in a CLEAR state and flip-flop 74 in a RESET state. Receipt of the ping command sets flip-flop 66, which enables the two counters, flip-flop 74, and two tri-state core drivers 76 and 78. Counter 70 then counts the output of a high-fre¬ quency clock 80. This clock operates at a frequency which is an integral multiple of the desired ultrasonic transduce
OMPI
^ £ output frequency. In the example shown, it operates at 8 times the transducer output frequency.
Counter 70 is used as a frequency divider. One output at 1/4 clock frequency toggles flip-flop 74 at the beginning of each half-cycle of the transducer output fre quency. The other.output at 1/8 clock frequency advances counter 72. The two outputs of flip-flop 74 alternately actuate core drivers 76 and 78, which drive an ultrasonic transducer crystal 82 at the desired frequency. Counter counts complete cycles of the transducer frequency.
Switches 84 allow a number from 0 to 15 to be preset into counter 72. It will therefore reach full scale when the transducer has generated 1 to 16 cycles, depending on the setting of switches 84. When counter 72 reaches full sca it resets flip-flop 66, terminating the transmission. Th effect of these provisions is to cause the ultrasonic tra ducer 82 to produce a predetermined number of cycles of a ultrasonic wave, whose frequency is precisely determined the high-frequency clock 80 rather than by the natural re- sonance of transducer 82.
After transmission is completed, ultrasonic echoes are converted into electric waves by transducer 82. These are amplified by an amplifier 86, whose gain is set the gain sequencer 20 as previously described. Additional fixed gain can be provided by an amplifier 88 if needed. The amplifiers 86, 88 drive the serial input of a register 90. This may be a conventional serial-in-parallel-out shi register or a charge-coupled, analog delay line. (The term "register" is so defined as used in the appended claims.) Register 90 is clocked by high-frequency clock 8
Therefore, the incoming signal is clocked through the register at 8 times the transmitted frequency. This is th same as 8 times the received frequency except for doppler shift, which is negligible in this application. If a tap is provided at every fourth stage of the register 90, the incoming signal can be sampled at time intervals corres¬ ponding to each half-cycle of the signal wave. The number of taps required depends on the number of transmitted cycl 5 which was set by switches 84. The example shown assumes that four cycles were selected by the switches.
As the incoming signal is clocked from left to right through register 90, there will ideally be a time when taps 1, 9, 17, and 25 are all positive and taps 5, 13
1021, and 29 are all negative. When this occurs, the com¬ bination of a NAND-gate 92 and a NOR-gate 94. will produce a negative output to a shift register 96 for four conse¬ cutive clock cycles under ideal conditions. Because of jitter, noise, and the fact that the waveform of the signa 5 passing through register 90 is not a perfect squarewave, register 96 may receive a negative signal for fewer than four clock cycles. The combination of a NOR-gate 98 and a switch 100 provides a positive output to a one-shot mult vibrator 102 when either two or three consecutive clock 0 cycles produce a negative output from gate 92. In the switch position shown, three consecutive cycles are requir Multivibrator 102 produces a positive output pulse of con¬ sistent amplitude and duration when the selected consecu¬ tive-clock-cycle criterion is met. 5 It will be noted that all of the inputs to gate must be positive and all the inputs to gate 94 must be negative in order to produce a negative output to register 96. This condition will not be fulfilled unless (a) the length of the incoming wave train is at least N cycles, whe 0 N is the count selected by switches 84-, and (b) the fre¬ quency of the incoming signal is within + _T of the fre-. quency f„ sent out by transducer 82. This 2Nrequirement dis criminates against false returns produced by ultrasonic noise in the rails or echoes produced by transducers oper- 5 ating at frequencies other than f„. Another advantage of
<*gtS O this design is that the voltages and currents required to drive the transducer 82 to a desired transmitter power ou put are quite modest in comparison to those of the single pulse required to produce the more conventional damped wa output. This minimizes interference to electronic system from the transmitter pulse.
Range Counter
As mentioned previously, each range counter 30, 30* counts the system clock 22 from its channel reference time until interrupted by a pulse from its coherent searc unit 10, 10* which coincides with a range gate in its gat sequencer 26, 26*. The parallel output of the counter is accessible to the microprocessor 16 as a memory (or port) address. In addition it performs a simple arithmetic tes In rail testing it is useful to be able to dis¬ tinguish between "walking" and fixed echoes. Rail ends an transverse rail defects decrease in range as the test whee approaches them, while the return from a horizontal defect the bottom of the rail, and some kinds of reverberations maintain approximately constant range once detected. The rate of change of a walking echo is proportional to the test car speed and the sine of the angle of incidence of the ultrasonic beam. The angle of incidence for any parti cular channel is fixed, but in general will be different for different channels. Therefore, it is convenient to pr vide in each range counter means for detecting the charac¬ teristic range rate of that channel and sending an additio al flag bit to the flag/interrupt memory area whenever it is detected. This is done by temporarily storing each ran count and subtracting it from the range count of the next ping (or vice versa) . If the difference falls between pre set limits depending on the angle of incidence of that channel, the flag bit is sent out. This permits the O O
WI ?N walking test to be performed on all channels simultaneous¬ ly, rather than requiring microprocessor 16 to make simila calculations in sequence for a variety of different counts and angles. Though a number of different hardware configura¬ tions are capable of performing the foregoing function, a preferred embodiment employs a separate single-chip micro¬ processor to perform the functions of each range counter. The preferred type of microprocessor for range-counter use comprises an arithmetic/logic module, random-access memory and electrically programmable read-only memory (EPROM) . T range-counter program and the arithmetic criteria for walk ing pulse detection are stored in the EPROM at the time of assignment of a particular range counter to a particular channel. The programmability afforded by the use of micro processors in the range counters is advantageous because it permits range counters of common design to be used in different ways in di erent channels or in special cir¬ cumstances. For example, a channel whose transducer is directed vertically downward (transducer 82v, FIGURE 4) wi seldom if ever encounter walking echoes of the kind des¬ cribed above. It will encounter sudden changes in echo range caused by bolt holes and horizontal defects. For vertical channels, therefore, it may be preferable to pro¬ gram the range counter to compare the current range count with a ixed reference rather than with the count of the previous ping.
Flag Field
The flag field memory area 28 is similar to the general random access memory 38 except that some additional logic is provided. The purpose of this logic is to cause
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<4-_. WIPO an interrupt of the microprocessor 16 in a selected case such as: (1) if one or more flags has been stored in the current operating cycle; (2) if no flag has been stored in the current operating cycle; or (3) if a condition is detected which indicates malfunction of the system. The interrupt, if used, is enabled by a channel of one of the sequencers at an address near the end of its operating cycle. It is not necessary to employ the interrupt capa¬ bility, but it affords flexibility to the programmer in designing an operating system.
Defect Classification From Flag Logic
To aid in understanding how rail condition can be inferred from the history of trip bits stored in the flag field 28, a simple five-channel system will be described. A practical system would employ more gates and channels th considered here, but would operate in the same general manner.
In FIG. 4 the leading wheel T contains three tran ducers, each capable of both transmission and reception. One of these, 82v, is directed vertically downward along th axis labelled "VERT"; one, 82w is directed along the axis "WEB" at an angle of incidence of about 45°; and one, 82h i directed along the axis "HEAD," at about 75°. The vertical 82v and web 82w transducers are over the center of the rail so that signals can be sent through the rail and reflected from the discontinuity at the rail bottom. The head trans¬ ducer 82h need not be over the center, since it is concerne only with signals in the rail head. The trailing wheel con tains a transducer 82w' which receives the bottom-reflected WEB signal. It also contains a pair of transducers, one of which 82z is shown, which pass a signal diagonally across the head of the rail. This pair is labelled the "Z" channe Details of the Z channel will be found in copending appli¬ cation S.N. , filed by George D. Martens and assigned to the same assignee as the present application. The disclosure of that application is incorp rated herein by reference.
The vertical channel has five range gates which distinguish the following regions of the rail:
H - head; ABH - above bolthole; BH - bolthole region; BBH - below bolthole; BOT - rail bottom. The web channel has two range gates: a BH gate covering* i bolthole region, and a THRU gate allowing recognition by the transducer 82w* in the trailing wheel of the signal re¬ flected by the rail bottom. The head channel has a single wide gate covering the entire region of the "HEAD" dashed arrow in FIG. 4. The Z-channel has' only a THRU gate, en¬ abling reception of the through-transmission from one trans ducer 82Z to the other of the Z-pair. The head channel is configured to recognize only "walking" echoes (see "Range Counter" above) . The vertical and web channels respond to all kinds of echoes. The Z-channel responds only to inter¬ ruption of the normally present through-signal by a rail end, split head, or other large head discontinuity.
It is evident that a discontinuity in the rail wil be seen at different times by the different channels becaus of the location and orientation of the transducers 82. For instance, a bolthole will be seen by the web channel about 15 pings after it has been recognized by the vertical channel. An interruption of the Z-channel may occur as muc as 64 pings after its cause has been traversed by the vertical channel. This condition is called channel offset. To correlate different "views" of the same condition, the presence or absence of some trip bits must be carried in computer memory for as many as 64 consecutive pings.
A convenient method of accomplishing this may be explained by reference to FIG. 5. A separate trip line from each gate of each transducer goes to a different bit position of that portion of the computer's random-access memory called the flag field 28. In this example, it is assumed that the flag field 28 begins at (decimal) address 100 and ends at address 164. After each ping, the presenc or absence of each of the nine-trip bits here considered i written into its proper bit position. The memory address is then incremented by 1. This process is repeated until data has been stored- at address 164, whereupon the address register is reset to 100. As a result, the data associated with any ping number P is stored at address K + P MOD 64, where K is the starting address of the flag field (in this case 100) and P MOD 64 signifies P (modulo 64) in the nota¬ tion of congruence arithmetic.
To recall stored data for processing, K + P MOD 64 is addressed for current data and K +(P - N) MOD 64 is addressed for data stored N pings ago. (N is generally the channel offset.) Individual bits are selected for attentio by a programmed Boolean AND operation in the computer. For example, suppose it is desired to know whether a signal was present in the bolthole gate of the web channel 15 pings ago. The required data will be found at bit position 2 of address 100 +(P-15) MOD 64. The system's ping counter furn¬ ishes P; the computer program furnishes the constant 15 an the algorithm for "MOD 64." The. contents' of this address is loaded into the computer accumulator in binary form and then subjected to the Boolean "AND" operation with the binary constant 000000100. The result will be 1 if a sig¬ nal was present, 0 if it was not.
This exemplary system identifies arid classifies rail defects according to the presence of certain combin- ations of nine "flags." A flag is defined as a "set" or binary 1 condition in a particular bit in a special flag register (or memory address) . A flag is set whenever a specified trip bit is observed for D consecutive pings in a specified channel offset "window" defined by the limits Wl and W2. The table below defines the flags used in this
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^ M example.
FLAG WINDOW DURATION CONDITION
LOCATION (pings)
(pings)
Wl W2 D
A 0 - 30 8 Walking target in HEAD channel
-B 56 - 64 - 8 Signal loss in Z-channel
C 56 - 64 8 Signal loss in WEB chann
D 0 - 10 10 Loss of bottom reflectio in VERT
E 10 - 20 10 Reflection in WEB BH gat
F 0 - 8 8 Reflection in VERT H gat
G 0 - 8 8 ** " ABH
H 0 - 10 10 " II H BH
J 0 - 8 8 " BBH
Flag A is set whenever the HEAD WALK trip bit is found to be "1" for any 8 consecutive pings of the last 30. Flag B is set if 8 of the 9 Z-channel trip bits at addresses (P - 56) to (P - 64) are "1." Flag H is set if 10 of the last 11 VERT-channel BH trip bits are set, and so on. By this means, the presence of a predefined anomalous conditio its persistence over at least a specified minimum length of rail, and the proper channel offset for simultaneous consi- deration of all channels in diagnosis are all encoded into a single bitI
It is evident that most rail defects can be characterized by combinations of these flag bits. The following distinctions can be made by this simple system:
RE (rail end) = B * C
BHC (bolthole crack) = (D*H) + E
HD (head defect) = RE * (A + F + (B *" D))
WD (web defect other than BHC) = D * (G+J) * BHC. In this notation, A through J represent the flags just de- fined; "*" and "÷" represent the Boolean "AND" and "OR" operators; and the superscribed "~~* represents negation.
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WI Thus the conditions for HD are read "NOT rail end AND (A OR F OR (B AND NOT D) ) . This could be translated "If you are not at a rail end, then a head defect is character ized by (1) a walking target in the head channel OR (2) a reflection in the H gate of the vertical channel OR (3) a loss of the Z-channel, provided that the bottom reflecti of the vertical channel is not also missing."
FIGURE 6 is a flow chart of a computer routine that tests for these logic combinations. The notation "B?" means "is the B flag set?". In this diagram, the program first tests for presence of both the B and C flags to determine whether a rail end is present. Although a ra end is not a defect, its presence would veto a possible HD diagnosis and therefore must be determined. If either B o C is not present, an additional flag RE (not rail end) is set for later reference. In blocks 4 and 5, the program tests for presence of both D and H. If both are present, "bolthole crack" is diagnosed and output for appropriate action. If one or both are missing, block 6 tests for the presence of E, the alternative indication of BHC. If E is present, "bolthole crack" is diagnosed and output. If not, the flag BHC (not bolthole crack) is set for later refer¬ ence.
Block 9 permits omission of the head-defect sequence 10-14 if a rail end has been found in 1 and 2. Otherwise, the'program tests for A or F or B-and-not-D and outputs "head defect" if any of these are found. Then it proceeds to the final sequence 15-19 to test for web defects in similar manner. The program exits at block 20 to perform other functions, such as loading data from the next ping into the flag field 28, and then repeats for the next ping.
The order in which the tests are performed are no material to this invention, nor are the particular tests themselves, the combinatory logic, the definition of the flag criteria, the number and orientation of transducers, the number and location of range gates, etc. The purpose of this disclosure is to show one way in which typical rai defect conditions can be identified from a time history of trip bits, which have been generated in one of the ways pr viously described.
Calibration " "
There are several ways in which calibration of the system can be accomplished. The following elements are common to all:
1. On a representative section of rail which co tains no defects, go through at least one cycle of the channel sequencer 14, so that each search unit is actuated at least once. . 2. Store all echo returns in the interface se¬ quencer 24.
3. Read the contents of interface sequencer 24 into microprocessor 16 and display on data terminal, or per form equivalent automatic action. 4. Identify the interface time for each channel from known track geometry and time and order of returns. 5. Identify normally present echoes for each channel, such as rail bottom, direct transmission from one transducer to another, and bolthole returns. 6. Identify spurious returns, such as reverbera¬ tions.
7. Determine the range gate boundaries required to accept normally present returns and reject spurious re¬ turns. 8. Load the range gate data into gate sequencers
26, 26'.
9. Erase interface sequencer 24 and input channe interface time data.
10. Restore to operating mode". Although these actions can be performed with a single ping and a stationary search head, a preferred method is for th microprocessor 16 to average the results of a number of operating cycles, with the search heads in motion. This averages out minor fluctuations. An initial calibration would generally be performed under operator supervision, but the microprocessor executive program can also incorpo¬ rate provisions for automatic recalibration. This can be done at regular intervals, or the interrupt capability of the flag field can be used to call a recalibration routine whenever anomalous conditions are encountered that are not attributable to rail defects.
Self-Test
An advantage of a microprocessor-controlled system is the variety of self-test and diagnostic proce¬ dures that can be incorporated in program routines. Like calibration, these can be called manually, at regular in¬ tervals, or on occurrence of anomalous events. Details of such self-test routines are system dependent and outside the scope of this description.
Listed below are representative components actu¬ ally used in an embodiment of this invention.
Sequencers 14, 24, and 26 Control flip-flop 42 74ES74
Address counter 48 74LS569
256x4 RAM 52 2111A-4
Ext. event NAND 56 74LSOO
System Clock 22: MC6875 Flag Field 28: Storage buffer 74LS377
Data bus interface 74LS257 ROM 36: 2716 and 2532
RAM 38: MM257 Microprocessor 16: MC6800L Gain Sequencer 20 : Gain memory HM6551-9
Address decoder 74LS138 D/A Converter 54: Converter DAC-08
Output amplifier 3140 Range Counter 30 : Microprocessor 3874
Counter 74LS161 Coherence Circuit 10 : HF clock 80 74LS124
Divider 70 74LS161 a 74LS74 Pulse train div. 72 74LS193
Transducer driver 76 75325 Log amp 86 . T1L441
Post-amp 88 - CA3140
Shift register 90,96 74LS164 NOR gate 94 74LS260
NOR gate 98 74LS27
NAND gate 92 74LS133
One-shot MV 102 74LS123 It is believed that the many advantages of this invention will now be apparent to those skilled in the art It will also be apparent that many variations and modifica tions may be made therein without departing from its spiri and scope. For example, the system disclosed herein is directed to the testing of rail in track but may have appl cation to the non- estructive testing of unlaid rail or of other test pieces altogether. Also, other types of data acquisition apparatus can be employed in lieu of ultrasoni transducers liquid-coupled to the test piece. An example is electromagnetic acoustic transducers which do not requi liquid filled wheels. Accordingly, the foregoing descript is to be construed as illustrative only. This invention i limited only by the scope of the following claims.
( OOMFPII

Claims

C I M S
1. In an ultrasonic tester including at least one search unit movable along an elongated workpiece, a plurality of ultrasonic transducers within said search un positioned to direct ultrasonic energy into said workpiec and receive ultrasonic echoes therefrom, and means for pr ducing a series of. electrical trigger signals having a repetition rate proportional to the relative speed betwee said search unit and said workpiece, the improvement whic comprises: means for producing a series of clock pulses; means for counting said clock pulses; means responsive to said trigger signals for enabling said counting means upon receipt of each of said trigger signals; means responsive to the accumulation of a pre¬ selected limiting count in said counting means for there¬ upon disabling said counting means; and means responsive to the accumulation of counts i said counting means for sequentially activating said trans ducers upon the accumulation of a number of preselected counts less than said limiting count.
2. In an ultrasonic tester including at least o search unit movable along an elongated workpiece, a plural of ultrasonic transducers within said search unit position to direct ultrasonic energy into said workpiece and receiv ultrasonic echoes therefrom, means for producing a series of electrical trigger signals, and means responsive to sai trigger signals to activate said transducers, the improve- ment which comprises: means for producing a series of clock pulses; means for counting said clock pulses upon the occurrence of each of said trigger signals;
*βl3REAi
OMPI
3&SΪX a memory unit having a plurality of address positions corresponding to sequentially occurring count accumulations in said counting means; and means responsive to echo signal pulses from sai transducers for storing each of said pulses in said memor unit at an address position corresponding to the elapsed time -between a trigger signal and subsequent receipt of s echo signal pulse.
3. The improvement of claim 2 wherein each stor pulse is stored in a channel which is unique to its trans¬ ducer.
4. The improvement of claim 3 wherein each stor pulse is an interface pulse corresponding to an entrant surface echo from said workpiece.
5. The improvement of claim 4 further comprisin means responsive to the contents of one of said channels for counting said clock pulses upon the playback of a stored interface pulse in said channel; a gate memory unit having a plurality of address positions corresponding to the elapsed time following the playback of a stored interface pulse, said address positio containing gating-instructions-stored therein; means responsive to echo signal pulses from said transducer and to gating instructions at each address for passing said pulses during gating periods; and flag field memory means for storing each pulse s passed.
6. The improvement of claim 5 further comprisin range counting means for counting said clock pulses;
"BU AU OMPI
^^NATlOg eans responsive to the contents of said one channel for actuating said range counting means upon the playback of said stored interface pulse in said channel; means responsive to a pulse passed during a gat period to thereupon stop said range counting means.
7. The improvement of claim 6 further comprisi means for generating an output if the count ac¬ cumulated in said range counting means exceeds a predeter mined level.
8. The improvement of claim 6 further comprisi means for comparing a count accumulated in said range counting means with a previously accumulated count and generating an output if the difference exceeds a pre¬ determined value.
9. The improvement of claim 8 wherein the pre¬ determined value is related to the sine of the angle of incidence of the direction of said ultrasonic energy.
10. In an ultrasonic tester of the type includin an ultrasonic transducer electrically energizable to gener ate ultrasonic energy during a sending period and capable of converting received ultrasonic energy into electrical energy during a receiving period, means for electrically energizing said transducer, and means for processing electrical energy produced by said transducer, the improve ment which comprises: said energizing means being operable for driving said transducer during said sending period at a preselecte frequency f„ for a preselected time; said processing means being operable to sample said produced electrical energy and provide an output signal when the waveform of said produced electrical energy is substantially equivalent to that of the trans¬ ducer energizing signal.
11. The improvement of claim 10 wherein said processing means comprises: a register connected to receive electrical energ produced by said transducer; means for clocking said register at a frequency which is a higher multiple of f„ to store in said register a preselected number, N, of cycles of said produced elec¬ trical energy? and -- • means for producing said output signal when the frequency of the energy stored in said register is within + fT 0.p ~ 2N °f
12. The improvement of claim 11 wherein said energizing means comprises: a frequency divider driven by said clocking mean and having first and second output frequencies; transducer driving means operable from said firs output frequency for driving said transducer at frequency fτ; and resetting means operable from said second output frequency for terminating the output of said transducer driving means after N cycles.
13. In an ultrasonic tester including at least one search unit movable along an elongated workpiece, a plurality of ultrasonic transducers within said search uni positioned to direct ultrasonic energy into said workpiece and receive ultrasonic echoes therefrom, and means for pro ducing a series of electrical trigger signals having a
•tjUREAf OMPI repetition rate proportional to the relative speed betw said search unit and said workpiece, the improvement wh comprises: means for producing a series of clock pulses; 5 first means for counting said clock pulses; means responsive to said trigger signals for enabling said first counting means upon receipt of each said trigger signals; means responsive to the accumulation of a pre- 10 selected limiting count in said first counting means for thereupon disabling said first counting means; means responsive to the accumulation of counts in said first counting means for sequentially activating said transducers upon the accumulation of a number of pr 15 selected counts less than said limiting count; second means for counting said clock pulses up the occurrence of each of said trigger signals; a memory unit having a plurality of address po tions corresponding to sequentially occurring count accu 2.0 lations in said second counting means; and means responsive to echo signal pulses from sa transducers for storing each of said pulses in said memo unit at an address position corresponding to the elapsed time between a trigger signal and subsequent receipt of s 5 echo signal pulse.
14. The improvement of claim 13 wherein each stored pulse is stored in a channel which is unique to it transducer. 0
15. The improvement of claim 14 wherein each stored pulse is an interface pulse corresponding to an en trant surface echo from said workpiece.
16. The improvement of claim 15 further com¬ prising: separate means responsive, respectively, to the contents of each of said channels for counting said clock pulses upon the playback of a stored interface pulse in an associated channel; a separate gate memory unit associated with each of said channels having a plurality of address positions corresponding to the elapsed time following the playback of a stored interface pulse, said address positions con¬ taining gating instructions stored therein; means associated with each channel and responsiv to echo signal pulses from its associated transducer and to gating instructions at each address for passing said pulses during gating periods; and memory means for storing each pulse so passed.
17. The improvement of claim 16 further com¬ prising: separate range counting means associated with each of said channels for counting said clock pulses; means responsive to the contents of each of said channels for actuating the associated range counting means upon the playback of an interface pulse stored in said channel, and means in each channel responsive to a pulse pass during a gating period to thereuponstop the associated range counting means.
18. The improvement of claim 17 further com¬ prising: means for generating an output if the count ac¬ cumulated in each range counting means exceeds a predeter¬ mined level.
19. The improvement of claim 18 further com¬ prising: means for comparing the count accumulated in ea range counting means with a count previously accumulated the same range counting means and generating an output if the difference exceeds a predetermined value.
20. The improvement of claim 19 wherein the pr determined value is related to the sine of the angle of 0 incidence of the direction of said ultrasonic energy.
21. The improvement of claim 13 wherein said transducer activating means comprises: means for driving each of said transducers at a preselected frequency fτ for a preselected pulse time.
22. The improvement of claim 21 wherein said echo signal responsive means comprises: means for sampling the echo signal pulses from • each of said transducers and storing said pulses only when the waveform of said pulse is substantially equivalen to that of the driving pulse of the same transducer.
23. In the method of ultrasonic testing wherein a plurality of ultrasonic transducers are movable along a workpiece to direct ultrasonic energy therein and receive ultrasonic echoes therefrom, and a series of electrical tr ger signals are produced having a repetition rate proportio al to the relative speed between said transducers and said workpiece, the improvement which comprises: producing a series of clock pulses; counting said clock pulses upon receipt of each of said trigger signals; terminating said counting upon the accumulation of a preselected limiting count; and
. -B- REA OMPI fy 4>- . m wi ?NAPru TO1C sequentially activating said transducers upon reaching a number of preselected counts less than said limiting count.
24. In the method of ultrasonic testing wherein plurality of ultrasonic transducers are movable along a wor piece to direct ultrasonic energy therein and receive ultra sonic echoes therefrom, a series of electrical trigger sig¬ nals are produced, and said transducers are activated by sa trigger signals, the improvement which comprises: producing a series of clock pulses; counting said clock pulses upon the occurrence of each of said trigger signals; and storing each of said echo signal pulses from sai transducers in a memory unit at an address position corre¬ sponding to the elapsed time between a trigger signal and subsequent receipt of said echo signal pulse.
25. The improvement of claim 24 comprising stor ing each stored pulse in a channel which is unique to its transducer.
26. The improvement of claim 25 wherein each stored pulse is an interface pulse corresponding to an en¬ trant surface echo from said workpiece.
27. The improvement of claim 26 further compris ing: counting said clock pulses upon the playback of stored interface pulse in a channel; storing gating instructions in a plurality of address positions corresponding to the elapsed time follow¬ ing the playback of a stored interface pulse? passing echo signal pulses from said transducer in response to gating instructions at each address; and storing each pulse so passed.
28. The improvement of claim 27 further com¬ prising: counting said clock pulses beginning with the playback of a stored interface pulse in a channel; and 5 terminating counting responsive to a pulse pass during a gating period to thereupon establish a range cou
29. The improvement of claim 28 further compris ing: - - generating an output if said range count exceeds 10 a predetermined level.
30. The improvement of claim 28 further compris ing: comparing an accumulated range count with a pre¬ viously accumulated range count and generating an output i 15 the difference exceeds a predetermined value.
31. The improvement of claim 30 wherein the pre determined value is related to the sine of the angle of incidence of the direction of said ultrasonic energy.
32. In the method of ultrasonic testing wherein 20 an ultrasonic transducer is electrically energized to gen¬ erate ultrasonic energy during a sending period and receiv ultrasonic energy is converted into electrical energy by said transducer during a receiving period, and processing electrical energy produced by said transducer, the improve-
' 25 ment which comprises: driving said transducer during said sending perio at a preselected frequency fm for a preselected time; and sampling said produced electrical energy and pro¬ viding an output signal when the waveform of said produced 30 electrical energy is substantially equivalent to that of the transducer energizing signal.
33. The improvement of claim 32 wherein said
- U E OMPI
SΛ,^. wWiIpPoO ^i?NATl processing step comprises: storing a preselected number, N, of cycles of said produced electrical energy; and producing said output signal when the frequency of the energy stored is within * T of fφ.
"2N
34. The improvement of claim 33 wherein said energizing comprises: establishing control signals having first and seco frequencies; driving said transducer from one of said control signals at frequency f„; and terminating the output of said transducer after N cycles in response to the other of said control signals.
35. In the method of ultrasonic testing wherein a search unit containing a plurality of ultrasonic trans¬ ducers is moved along a workpiece to direct ultrasonic energy into said workpiece and receive ultrasonic echoes therefrom, and a series of electrical trigger signals is produced having a repetition rate proportional to the re- lative speed between said search unit and said workpiece, the improvement which comprises: producing a series of clock pulses; counting said clock pulses beginning with each of said trigger signals; sequentially activating said transducers upon the accumulation of a number of preselected counts; and storing the echo signal pulses from said transducers in address positions corresponding to the elapsed times be¬ tween a trigger signal and subsequent receipt of an echo signal pulse.
36. The improvement of claim 35 wherein each stored pulse is stored in a channel which is unique to its trans¬ ducer. ijURE
OMPI ^0
37. The improvement of claim 36 wherein each stored pulse is an interface pulse corresponding to an en trant surface echo from said workpiece.
38. The improvement of claim 37 further com- prising: counting said clock pulses upon the playback of a stored interface pulse in an associated channel; storing gating instructions for each of said channels in address positions corresponding to the elapsed time following the playback of a stored interface pulse; passing echo signal pulses during gating periods and storing each pulse so passed.
39. The improvement of claim 38 further com- prising: counting said clock pulses beginning with the playback of an interface pulse stored in a channel? and terminating the count responsive to a pulse pass in said channel during a gating period to provide a range count.
40. The improvement of claim 39 further com¬ prising: generating an output if the count accumulated in each range count exceeds a predetermined level.
41. The improvement of claim 39 further com¬ prising: comparing the accumulated range count with a pre¬ viously accumulated range count in the same channel and generating an output if the difference exceeds a predeter- mined value.
" ϋREAl
OMPI e4ϋ>_ W^0
42. The improvement of claim 41 wherein the predetermined value is related to the sine of the angle of incidence of the direction of said ultrasonic energy.
43. The improvement of claim 35 wherein: ' each of said transducers is driven at a presele¬ cted frequency f„ for a preselected pulse time.
44. The improvement of claim 43 wherein: the echo signal pulses from each of said trans¬ ducers are sampled and stored only when the waveform of a pulse is substantially equivalent to that of the driving pulse of the same transducer.
"gU EA
OMPI
PCT/US1982/000566 1981-05-06 1982-05-03 Ultrasonic rail testing system WO1982003919A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
BR8207680A BR8207680A (en) 1982-05-03 1982-05-03 ULTRASOUND TEST SYSTEM FOR RAILWAYS
AU85277/82A AU8527782A (en) 1981-05-06 1982-05-03 Ultrasonic rail testing system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US26060481A 1981-05-06 1981-05-06
US260604810506 1981-05-06

Publications (1)

Publication Number Publication Date
WO1982003919A1 true WO1982003919A1 (en) 1982-11-11

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JP (1) JPS58500673A (en)
ES (1) ES511951A0 (en)
IT (1) IT8267593A0 (en)
WO (1) WO1982003919A1 (en)
ZA (1) ZA822585B (en)

Cited By (9)

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Publication number Priority date Publication date Assignee Title
WO1992019963A1 (en) * 1991-05-07 1992-11-12 Dapco Industries Real-time ultrasonic testing system
EP0532448A2 (en) * 1991-09-03 1993-03-17 Krautkramer Branson Incorporated Quiet bus for the busing of analog and digital data
DE102007042325A1 (en) * 2007-09-06 2009-04-02 Fgb A. Steinbach Gmbh & Co. Kg Non-destructive material testing e.g. eddy-current testing, device, has retaining unit storing values of response signal responding to trigger pulses, and signal generator for displaying trigger pulses depending on excitation signal
EP2208994A3 (en) * 2009-01-20 2010-08-04 National Railroad Passenger Corporation Multi-probe rail scanning/encoder system and certified method of use thereof
RU2603332C1 (en) * 2015-09-30 2016-11-27 Открытое акционерное общество "Радиоавионика" Method of adjusting sensitivity of the rail ultrasonic flaw detector
CN107356680A (en) * 2017-07-12 2017-11-17 辽宁红阳检测有限公司 A kind of rail track broken detector
RU2726277C1 (en) * 2019-12-31 2020-07-10 Федеральное государственное бюджетное образовательное учреждение высшего образования "Сибирский государственный университет путей сообщения" (СГУПС) Method of adjusting sensitivity of an ultrasonic flaw detector
RU2753810C1 (en) * 2021-02-02 2021-08-23 Открытое акционерное общество "Радиоавионика" Method for evaluating the performance of flaw detection equipment during high-speed inspection of rails
RU2774096C1 (en) * 2021-10-20 2022-06-15 Акционерное общество "РАДИОАВИОНИКА" Method for dynamic adjustment of the sensitivity of flaw detection tools during high-speed testing of long objects

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US3415110A (en) * 1964-07-31 1968-12-10 Automation Ind Inc Ultrasonic inspection
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US4222275A (en) * 1978-10-02 1980-09-16 Dapco Industries, Inc. System for non-destructively acquiring and processing information about a test piece

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US3415110A (en) * 1964-07-31 1968-12-10 Automation Ind Inc Ultrasonic inspection
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US4222275A (en) * 1978-10-02 1980-09-16 Dapco Industries, Inc. System for non-destructively acquiring and processing information about a test piece

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992019963A1 (en) * 1991-05-07 1992-11-12 Dapco Industries Real-time ultrasonic testing system
EP0532448A2 (en) * 1991-09-03 1993-03-17 Krautkramer Branson Incorporated Quiet bus for the busing of analog and digital data
EP0532448A3 (en) * 1991-09-03 1993-09-08 Krautkramer Branson Incorporated Quiet bus for the busing of analog and digital data
DE102007042325A1 (en) * 2007-09-06 2009-04-02 Fgb A. Steinbach Gmbh & Co. Kg Non-destructive material testing e.g. eddy-current testing, device, has retaining unit storing values of response signal responding to trigger pulses, and signal generator for displaying trigger pulses depending on excitation signal
DE102007042325B4 (en) * 2007-09-06 2017-05-18 Fgb A. Steinbach Gmbh & Co. Kg Apparatus and method for non-destructive material testing
US9128034B2 (en) 2009-01-20 2015-09-08 National Railrod Passenger Corporation Multi-probe rail scanning/encoder system and certified method of use thereof
US8196469B2 (en) 2009-01-20 2012-06-12 National Railroad Passenger Corporation Multi-probe rail scanning/encoder system and certified method of use thereof
EP2208994A3 (en) * 2009-01-20 2010-08-04 National Railroad Passenger Corporation Multi-probe rail scanning/encoder system and certified method of use thereof
RU2603332C1 (en) * 2015-09-30 2016-11-27 Открытое акционерное общество "Радиоавионика" Method of adjusting sensitivity of the rail ultrasonic flaw detector
CN107356680A (en) * 2017-07-12 2017-11-17 辽宁红阳检测有限公司 A kind of rail track broken detector
RU2726277C1 (en) * 2019-12-31 2020-07-10 Федеральное государственное бюджетное образовательное учреждение высшего образования "Сибирский государственный университет путей сообщения" (СГУПС) Method of adjusting sensitivity of an ultrasonic flaw detector
RU2753810C1 (en) * 2021-02-02 2021-08-23 Открытое акционерное общество "Радиоавионика" Method for evaluating the performance of flaw detection equipment during high-speed inspection of rails
RU2774096C1 (en) * 2021-10-20 2022-06-15 Акционерное общество "РАДИОАВИОНИКА" Method for dynamic adjustment of the sensitivity of flaw detection tools during high-speed testing of long objects

Also Published As

Publication number Publication date
ES8308636A1 (en) 1983-09-01
ZA822585B (en) 1983-02-23
IT8267593A0 (en) 1982-05-06
JPS58500673A (en) 1983-04-28
ES511951A0 (en) 1983-09-01

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