WO1982002988A1 - Logic select circuit - Google Patents

Logic select circuit Download PDF

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Publication number
WO1982002988A1
WO1982002988A1 PCT/US1982/000184 US8200184W WO8202988A1 WO 1982002988 A1 WO1982002988 A1 WO 1982002988A1 US 8200184 W US8200184 W US 8200184W WO 8202988 A1 WO8202988 A1 WO 8202988A1
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WO
WIPO (PCT)
Prior art keywords
circuit
logic
coupled
terminal
diode
Prior art date
Application number
PCT/US1982/000184
Other languages
French (fr)
Inventor
Inc Motorola
John J Price Jr
Original Assignee
Inc Motorola
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inc Motorola filed Critical Inc Motorola
Publication of WO1982002988A1 publication Critical patent/WO1982002988A1/en

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Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175Coupling arrangements; Interface arrangements
    • H03K19/017509Interface arrangements

Definitions

  • This present invention is related to threshold level setting circuits and more particularly to a circuit for use in combination with an interface system to make such system compatible with both T 2 L and CMOS logic.
  • DACs digital to analog converters
  • T 2 L or CMOS logic input signals In addition to interfacing easily with T 2 L or CMOS logic, DACs as aforementioned should also be able to operate with either logic using either +5 volt or +15 volt supplies.
  • Another object of the present invention is to provide a logic select circuit for supplying a multi-level logic threshold signal. Another object of the invention is to provide a circuit for use with an interface system to make the system compatible with several different logic drive signals and different power supply voltages.
  • a logic select circuit comprising a series combination of a first pair of diodes coupled to a pair of serially connected matched resistors which in turn are coupled to a second pair of diodes.
  • a constant source for providing a predetermined constant current is connected at the interconnection between the serially connected resistors to the second pair of diodes with an output of the circuit being taken at the interconnection between the pair of resistors.
  • the select circuit is provided on board of an integrated interface circuit to provide a selectable threshold level function to the interface circuit.
  • the select circuit would be coupled to first and second terminals with the second terminal receiving a ground reference potential. By allowing the first terminal to float, a T 2 L logic threshold level is obtained and, by connecting the first terminal to a power supply source, a CMOS logic threshold is provided.
  • the single Figure is a schematic diagram of the preferred embodiment of the invention.
  • logic select circuit 10 which is suitable to be fabricated in monolithic circuit form.
  • Logic select circuit 10 includes a first pair of diode means 12 and 14 coupled between a select terminal 16 and one lead of resistor 18.
  • Resistor 18 is serially connected to resistor 20 which in turn is coupled in series with a second pair of diode means 22 and 24.
  • the resistors 18 and 20 function as circuit means interconnecting the first and second diode pair means.
  • the cathode of diode means 24 is adapted to be connected to a ground reference potential supplied at terminal 26.
  • a constant current source 28 is connected to power supply connector 30 to V CC at terminal 32 and supplies a constant current to diode means pair 22 and 24.
  • logic select circuit 10 is taken at the interconnection between resistors 18 and 20 to set the threshold logic level, via lead 34, to utilization means 36.
  • utilization means 36 is a digital to analog converter (DAC) such as a MC-3512 DAC manufactured by Motorola Inc.
  • DAC digital to analog converter
  • logic select circuit 10 could be incorporated on the same integrated chip comprising the MC-3512 DAC such that the DAC could be driven by both T 2 L and CMOS logic input signals as will be explained.
  • utilization means 36 In operation, if utilization means 36 is to be driven by T 2 L logic signals, the threshold level must be set to approximately 1.4 volts, as understood.
  • diode means 22 and 24 By allowing select input terminal 16 to float, assuming that the output via lead 34 is well buffered, diode means 22 and 24 would be rendered conductive by current source 28 providing a minimum current, for example, of 100 ⁇ -amps thereto. Hence a voltage drop of approximately 2.4 volts (0.7 volts across each diode 22 and 24) appears at lead 34 regardless of the magnitude of V C C (within a range between 5 volts to 15 volts). Hence, utilization means 36 could function with T 2 L logic drive signals.
  • utilization means 36 functions with CMOS logic signals as the threshold level set via lead 34 is then equal to V CC /2.
  • the voltage potential V C C / 2 is caused to appear by making resistors 18 and 20 equal valued and matching diode means 12, 14, 22 and 24 to each other, neglecting the small current from current source 28, wherein the two symmetrical circuit portions are formed comprising first, diodes 12 and 14 and resistor 18 and secondly, diodes 22 and 24 and resistor 20 .
  • Th us what h as been des c ri bed is a novel logic select circuit for setting the logic threshold of an interface system coupled thereto wherein the interface system is made compatible to several logic drive input signals, i.e., T 2 L and CMOS. By selectively floating or connecting a select terminal of the logic select circuit the logic threshold level is set for either T 2 L or CMOS logic.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

A circuit for use with interface systems for providing a threshold setting function wherein the system can be made to interface with T2L or CMOS logic with either 5 or 15 volt power supply capabilities. The circuit comprises a pair of matched resistors (18, 20) coupled in series to one another. The first one of the resistors (18) is returned to a select terminal (16) via a first pair of diodes (12, 14). The second resistor (20) is returned to a terminal at which may be supplied a ground reference potential (26) via a second pair of diodes (22, 24). A source of current (28) is provided that is coupled to the interconnection of the second resistor with the second pair of diodes. A treshold output is provided to the interface system at the interconnection between the serially connected resistors.

Description

LOGIC SELECT CIRCUIT
BACKGROUND OF THE INVENTION
Field of the Invention:
This present invention is related to threshold level setting circuits and more particularly to a circuit for use in combination with an interface system to make such system compatible with both T2L and CMOS logic.
Description of the Prior Art:
Nearly all interface systems require a threshold setting function in order that they be compatible with several different logic signal drive. For example, digital to analog converters (DACs) are a type of interface circuit which in most cases should be capable of accommodating T2L or CMOS logic input signals. In addition to interfacing easily with T2L or CMOS logic, DACs as aforementioned should also be able to operate with either logic using either +5 volt or +15 volt supplies.
Hence, there is a need for a simple logic select circuit suitable to be manufactured on "chip" with an integrated interface system to provide multiple threshold level for the system without requiring external circuitry in order to make the interface system compatible with several different logic input signals that may be supplied thereto and which can operate from either a 5 volt or 15 volt power supply.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a logic select circuit for supplying a multi-level logic threshold signal. Another object of the invention is to provide a circuit for use with an interface system to make the system compatible with several different logic drive signals and different power supply voltages.
In accordance with the foregoing and other objects there is provided a logic select circuit comprising a series combination of a first pair of diodes coupled to a pair of serially connected matched resistors which in turn are coupled to a second pair of diodes. A constant source for providing a predetermined constant current is connected at the interconnection between the serially connected resistors to the second pair of diodes with an output of the circuit being taken at the interconnection between the pair of resistors.
It is a feature of the invention that the select circuit is provided on board of an integrated interface circuit to provide a selectable threshold level function to the interface circuit. The select circuit would be coupled to first and second terminals with the second terminal receiving a ground reference potential. By allowing the first terminal to float, a T2L logic threshold level is obtained and, by connecting the first terminal to a power supply source, a CMOS logic threshold is provided.
DESCRIPTION OF THE DRAWING
The single Figure is a schematic diagram of the preferred embodiment of the invention.
DESCRIPTION OF THE EMBODIMENT
Turning to the Figure, there is shown within the dashed outline form logic select circuit 10 which is suitable to be fabricated in monolithic circuit form. Logic select circuit 10 includes a first pair of diode means 12 and 14 coupled between a select terminal 16 and one lead of resistor 18. Resistor 18 is serially connected to resistor 20 which in turn is coupled in series with a second pair of diode means 22 and 24. The resistors 18 and 20 function as circuit means interconnecting the first and second diode pair means. The cathode of diode means 24 is adapted to be connected to a ground reference potential supplied at terminal 26. A constant current source 28 is connected to power supply connector 30 to VCC at terminal 32 and supplies a constant current to diode means pair 22 and 24. The output of logic select circuit 10 is taken at the interconnection between resistors 18 and 20 to set the threshold logic level, via lead 34, to utilization means 36. If, for example, utilization means 36 is a digital to analog converter (DAC) such as a MC-3512 DAC manufactured by Motorola Inc., logic select circuit 10 could be incorporated on the same integrated chip comprising the MC-3512 DAC such that the DAC could be driven by both T2L and CMOS logic input signals as will be explained.
In operation, if utilization means 36 is to be driven by T2L logic signals, the threshold level must be set to approximately 1.4 volts, as understood. By allowing select input terminal 16 to float, assuming that the output via lead 34 is well buffered, diode means 22 and 24 would be rendered conductive by current source 28 providing a minimum current, for example, of 100 μ-amps thereto. Hence a voltage drop of approximately 2.4 volts (0.7 volts across each diode 22 and 24) appears at lead 34 regardless of the magnitude of VC C (within a range between 5 volts to 15 volts). Hence, utilization means 36 could function with T2L logic drive signals. If select terminal 16 is connected to VCC, utilization means 36 functions with CMOS logic signals as the threshold level set via lead 34 is then equal to VCC/2. The voltage potential VC C / 2 is caused to appear by making resistors 18 and 20 equal valued and matching diode means 12, 14, 22 and 24 to each other, neglecting the small current from current source 28, wherein the two symmetrical circuit portions are formed comprising first, diodes 12 and 14 and resistor 18 and secondly, diodes 22 and 24 and resistor 20 .
Th us , what h as been des c ri bed is a novel logic select circuit for setting the logic threshold of an interface system coupled thereto wherein the interface system is made compatible to several logic drive input signals, i.e., T2L and CMOS. By selectively floating or connecting a select terminal of the logic select circuit the logic threshold level is set for either T2L or CMOS logic.

Claims

CLAI MS
1. A logic select circuit for providing a multi-level logic threshold signal at an output thereof, comprising: first diode means adapted to be coupled between a first terminal and a first circuit node; second diode means adapted to be coupled between a second terminal at which is supplied a ground reference potential and a second circuit node; circuit means coupled between said first and second circuit nodes and to the output of the logic select circuit; and current source means coupled to said second circuit node for providing a predetermined current thereto such that a first logic threshold signal of a first level is produced at the output of the logic select circuit and a second logic threshold signal of a second level is produced when said first terminal is adapted to be connected to a source of operating potential supplied to the logic select circuit.
2. The logic select circuit of claim 1 wherein: said first diode means includes first and second serially connected diodes; and said second diode means includes third and fourth serially connected diodes.
3. The logic select circuit of claim 2 wherein said circuit means includes: a first resistor; and a second resistor connected in series with said first resistor with the output of the logic select circuit being coupled to the interconnection point between said first and second resistors.
4. A logic select circuit to be utilized to provide a logic threshold level signal to a utilization means, the logic select circuit and the utilization means being fabricated in integrated circuit form, comprising: first and second symmetrical circuit means serially connected between a first terminal and a second terminal, said second terminal being adapted to receive a ground reference potential; current source means for supplying a current of predetermined magnitude to said second symmetrical circuit means; output circuit means coupled to the interconnection between said first and second symmetrical circuit means for supplying said logic threshold signal to the utilization means; and said first terminal being open circuited such that a first logic threshold signal of a first level is provided to the utilization means, said first terminal being adapted to receive a source of operating potential supplied to the logic select circuit for providing a second logic threshold signal of a second level to the utilization means.
5. The logic select circuit of claim 4 wherein said first symmetrical circuit means includes a first diode, a second diode and a first resistor serially connected between said first terminal and a circuit node, said circuit node being coupled to said output circuit means.
6. The logic select circuit of claim 5 wherein said second symmetrical circuit means includes a third diode, a fourth diode, said third and fourth diode being serially coupled to said second terminal and a second resistor coupled between said serially coupled third and fourth diodes and said circuit node, said current source means being coupled to said third and fourth serially coupled diodes.
PCT/US1982/000184 1981-02-18 1982-02-16 Logic select circuit WO1982002988A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US235397810218 1981-02-18
US06/235,397 US4392067A (en) 1981-02-18 1981-02-18 Logic select circuit

Publications (1)

Publication Number Publication Date
WO1982002988A1 true WO1982002988A1 (en) 1982-09-02

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1982/000184 WO1982002988A1 (en) 1981-02-18 1982-02-16 Logic select circuit

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US (1) US4392067A (en)
EP (1) EP0071644B1 (en)
JP (1) JPS58500100A (en)
WO (1) WO1982002988A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4472647A (en) * 1982-08-20 1984-09-18 Motorola, Inc. Circuit for interfacing with both TTL and CMOS voltage levels
JP2751422B2 (en) * 1988-06-27 1998-05-18 日本電気株式会社 Semiconductor device
US6605974B2 (en) * 2001-07-31 2003-08-12 Telefonaktiebolaget Lm Ericsson(Publ) Level shifter with gain

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3974404A (en) * 1973-02-15 1976-08-10 Motorola, Inc. Integrated circuit interface stage for high noise environment
US4147940A (en) * 1977-01-24 1979-04-03 Westinghouse Electric Corp. MOS Interface circuit
US4220876A (en) * 1978-08-17 1980-09-02 Motorola, Inc. Bus terminating and decoupling circuit
US4309693A (en) * 1974-09-12 1982-01-05 Analog Devices, Incorporated Solid state digital to analog converter

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3974404A (en) * 1973-02-15 1976-08-10 Motorola, Inc. Integrated circuit interface stage for high noise environment
US4309693A (en) * 1974-09-12 1982-01-05 Analog Devices, Incorporated Solid state digital to analog converter
US4147940A (en) * 1977-01-24 1979-04-03 Westinghouse Electric Corp. MOS Interface circuit
US4220876A (en) * 1978-08-17 1980-09-02 Motorola, Inc. Bus terminating and decoupling circuit

Also Published As

Publication number Publication date
US4392067A (en) 1983-07-05
EP0071644B1 (en) 1986-07-30
EP0071644A4 (en) 1984-04-27
JPS58500100A (en) 1983-01-13
EP0071644A1 (en) 1983-02-16
JPH0342733B2 (en) 1991-06-28

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