WO1981002078A1

WO1981002078A1 - Nmos amplifier using unimplanted transistors

Info

Publication number: WO1981002078A1
Application number: PCT/US1980/000507
Authority: WO
Inventors: I Young
Original assignee: Mostek Corp
Priority date: 1980-01-11
Filing date: 1980-05-05
Publication date: 1981-07-23
Also published as: FR2473791A1; DE3050202A1; GB2078462A; CA1161965A; FR2473791B1; NL8020488A; JPS56501904A

Abstract

An amplifier (20) is provided and is fabricated using NMOS technology to provide for an amplifier having low noise operating characteristics. The amplifier (20) includes transconductance transistors (22, 24) for receiving a differential input signal. A current source (30) is provided for biasing the amplifier (20). A load (26, 28) is interconnected to the transconductance transistors (22, 24) for generating an amplified output signal. The transconductance transistors (22, 24) comprise unimplanted semiconductor transistor devices for substantially eliminating the generation of low frequency noise in the operation of the amplifier (20).

Description

NMOS AMPLIFIER USING UNIMPLANTED TRANSISTORS

TECHNICAL FIELD

This invention relates to differential amplifiers, and more particularly to an NMOS differential amplifier having improved noise performance operating characteristics.

BACKGROUND ART

Differential amplifiers have been utilized in numerous applications. In particular, differential amplifiers are utilized in telecommunications systems for signal amplification. Of particular importance in such telecommunications systems is the minimization of noise introduced into the signal being processed and amplified. With the introduction of metal-oxide-semiconductor (MOS) technology, it has been advantageous to fabricate numerous circuit components on a single semiconductor substrate such as, for example, filter networks, in which differential amplifiers are also fabricated on the same semiconductor substrate. However, it has been found that noise generated by differential amplifiers used in such circuits is extremely detrimental to the operation of these telecommunications systems.

The dominant source of noise in an MOS differential amplifier arises from the noise generated by the differential input transconductance devices. A generally accepted previously developed practice for the design of differential amplifiers was to fabricate the transconductance devices within these differential amplifiers using an enhancement fabrication technique in which a channel is implanted at the surface of the semiconductor substrate. In an enhancement transistor fabricated in standard N-channel, silicon-gate technology, current flows within the channel region close to the surface of the semiconductor substrate when the device is on.

It has recently been realized that buried channel devices generate less noise than surface channel type devices. In a buried channel device, current flows below the surface of the semiconductor substrate. Typically, a depletion mode transistor is a slightly buried channel device when fabricated in standard N-channel silicon-gate depletion-load technology. However, for low noise operation, the N-channel depletion transistor requires a large negative threshold voltage, resulting in a channel that is well below the surface of the semiconductor substrate. A depletion transistor with a large negative threshold voltage is unacceptable for use as a transconductance device in a differential amplifier design. because of DC biasing considerations for the amplifier circuit,

A need has thus arisen for an NMOS differential amplifier having low noise operating characteristics to provide improved operating results. A need has further arisen for an NMOS differential amplifier having transconductance devices operable at a low threshold voltage.

DISCLOSURE OF THE INVENTION

In accordance with the present invention, a differential amplifier is provided which substantially eliminates the problems heretofore associated with differential amplifiers including minimizing the introduction of noise in a signal, such as an audio frequency signal, being processed.

In accordance with the present invention, in an amplifier fabricated using NMOS technology, a transconductance transistor is provided. The transistor comprises a semiconductor in which surface states resulting from the fabrication of the semiconductor is decreased by minimization of crystal damage at the surface and below the surface of the semiconductor to thereby minimize a source of noise in the operation of the amplifier.

In accordance with the present invention, a low noise amplifier is fabricated using NMOS technology including transconductance transistors. The transconductance transistors comprise unimplanted semiconductor transistors having a low concentration of surface states, thereby minimizing source of noise in the operation of the amplifier.

In accordance with another aspect of the present invention, an amplifier is fabricated using NMOS technology having low noise operating characteristics. The amplifier includes transconductance transistors for receiving a differential input signal. A current source is provided for biasing the amplifier. A load is interconnected to, the transconductance transistors for generating an amplified output signal. The transconductance transistors are unimplanted semiconductor transistor devices for substantially eliminating the generation of low frequency noise in the operation of the amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and for further objects and advantages thereof, reference will now be made to the following Detailed Description taken in conjunction with the accompanying Drawings in which:

FIGURE 1 is a diagrammatic representation of a enhancement transistor and an unimplanted, natural transistor;

FIGURE 2 is a schematic circuit diagram of the present differential amplifier; and

FIGURE 3 is a graphical representation of data showing the improved results of the present invention over previously developed differential amplifiers.

DETAILED DESCRIPTION

The present invention implements the realization that the major source of noise in the design of differential amplifiers is generated by the transconductance devices within such differential amplifiers. The heretofore accepted premise that the minimization of noise generation in enhancement MOS devices could be achieved by utilizing depletion MOS devices to minimize transistor noise is rejected by the present invention. It has been determined that the principal source of noise in transistor devices is caused by surface states.

Surface states are due to discontinuities and contaminants at the surface of a semiconductor device caused by damage and impurities, damage to the silicon of a semiconductor substrate, deposits in the silicon oxide interface and impurities in the oxide and silicon itself.

Surface states and noise in MOS transistors are discussed in an article by M.B. Das et al entitled "Measurements and Interpretation of Low-Frequency Noise In FET's", IEEE Transactions On Electron Devices, Vol. Ed-21, No. 4, April, 1974 at pages 247-257. Since, in an MOS device, the major damage is at its surface, the surface states are high resulting in high noise generation when the current flow is in that region. An enhancement transistor, fabricated in standard N-channel, silicon-gate technology, and biased on has current flow from source to drain occurring at the surface, where the high surface state concentration contributes to its high noise generation properties.

Previous developed devices therefore have minimized noise generation by burying the channel of an MOS device below the surface of the semiconductor substrate resulting in a depletion MOS device. The concept that a buried channel depletion device minimized sources of noise has been widespread since this type of device does minimize noise, to some extent, over an enhancement type device. However, such depletion devices have had large negative threshold voltages making them incompatible with the amplifier design constraints.

Through experimentation, it has been determined that the process of fabricating MOS devices having buried channels, with a more acceptable negative threshold voltage, introduces more noise sources than was thought to have been eliminated using buried channel devices. The damage introduced by implantation of the buried channel device introduces substantial noise sources deep into the silicon substrate, such that the area where charge is flowing is substantially damaged. The buried channel devices have a large negative threshold voltage in N-channel technology, which is not compatible with other circuit constraints in a differential amplifier design. The present invention therefore utilizes natural transistors in which no implants are utilized to substantially minimize any damage to the semiconductor substrate and in turn minimize the number of. surface states formed. By eliminating implants, the concentration of surface states within the device is substantially lessened. With the minimization of surface state concentration, noise generation by the transistors of an operational amplifier is drastically reduced. In addition, the resulting threshold voltage is approximately zero volts which is highly desirable in the operation of the differential amplifier.

FIGURE 1 illustrates in a simplified form the difference between an implanted transistor device and a natural transistor device. A semiconductor substrate 10 includes element sites 12 and 14. At element site 12, an enhancement type device is fabricated having an ion implant identified by the numeral 16. In contradistinction, at element site 14, a transistor device is fabricated which is natural, such that no . ion implantation takes place below the surface of semiconductor substrate 10. It is this unimplanted type of transistor at element site 14 that is utilized in the present differential amplifier to minimize noise sources in the transistors utilized therein to thereby improve the noise operating characteristics of the present amplifier.

FIGURE 2 represents a simplified circuit diagram of a differential amplifier, generally identified by the numeral 20. Differential amplifier 20 operates in a manner well known to those skilled in the art. Briefly, differential amplifier 20 has an inverting and noninverting input applied to transconductance transistor devices 22 and 24. Transconductance transistor devices 22 and 24 are interconnected to resistive load devices 26 and 28 to form the amplified voltage at the output of differential amplifier 20. Current source 30 provides a DC bias for differential amplifier 20. Transconductance transistor devices 22 and 24 are unimplanted transistors in accordance with the present invention to minimize the generation of noise with amplifier 20. FIGURE 3 illustrates a graphical representation of experimental data of the transconductance devices, natural devices produced in a standard N-channel silicon-gate depletion-load technology, of the present amplifier when compared to data of N-channel enhancement transistors produced in a standard N-channel silicon-gate depletion-load technology of previously developed amplifiers. The natural device and the enhancement device used in the experiment to generate this data were of the same geometries, having the same width and length dimensions and same oxide thicknesses. The plot of noise generated at frequencies of 250 Hz and 1000 Hz clearly illustrate the reduction in noise generation of the present amplifier. In FIGURE 3, the vertical axis represents the RMS voltage noise present at a single frequency referred to transistor input

. The horizontal axis represents drain current in the transconductance device being tested (I_D ) which equals the current of source 30 (FIGURE 2) divided by two. The range of drain current shown is the standard range of current used in MOS differential amplifiers. Plot A represents the input noise at 250 Hz for an enhancement (implanted) transistor. Data points for Plot A are represented by

Plot B represents the input noise at 250 Hz for a natural (unimplanted) transistor. Data points for Plot B are represented by

Plot C represents the input noise at 1000 Hz for an enhancement (implanted) transistor. Data points for Plot C are represented by

Plot D represents the input noise at 1000 Hz for a natural (unimplanted) transistor. Data points for Plot D are represented by ^•

It therefore can be seen that the present differential amplifier manufactured using NMOS technology utilizes transistor devices in which surface states are minimized thereby reducing their accompanying noise sources by eliminating implantation into the semiconductor substrate of MOS semiconductor devices utilized in the present amplifier. When compared to buried channel depletion type devices, that might be acceptable to the amplifier design constraints, the present amplifier has improved noise operating characteristics.

Whereas the present invention has been described with respect to specific embodiments thereof, it will be understood that various changes and modifications will be suggested to one skilled in the art and it is intended to encompass such changes and modifications as fall within the scope of the appended claims.

Claims

CLAIMS :

1. In an amplifier fabricated using NMOS technology, a transconductance transistor comprising: semiconductor means in which surface states resulting from the fabrication of said semiconductor are decreased by minimization of crystal damage at the surface and below the surface of said semiconductor means to thereby minimize a source of noise in the operation of the amplifier.

2. The transconductance transistor of Claim 1 wherein said semiconductor means comprises an unimplanted semiconductor transistor means.

3. A low noise amplifier fabricated using NMOS technology including transconductance transistors, wherein the transconductance transistors comprise: unimplanted semiconductor transistor means having a low concentration of surface states, thereby minimizing source of noise in the operation of the amplifier.

4. In a differential amplifier fabricated using NMOS technology, a transconductance transistor comprising: an unimplanted semiconductor transistor device for substantially eliminating the generation of low frequency noise in the operation of the amplifier.

5. An amplifier fabricated using NMOS technology having low noise operating characteristics comprising: means for receiving a differential input signal including transconductance transistor means; current source means for biasing the amplifier; load means interconnected to said transconductance transistor means for generating an amplified output signal; and said transconductance transistor means comprising an unimplanted semiconductor transistor device for substantially eliminating the generation of low frequency noise in the operation of the amplifier.