Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B20/00—Read-only memory [ROM] devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
  • H10W20/43—Layouts of interconnections

Definitions

• FIG. 1 The formation of the gate insulator region of the transistor is shown in FIG. 1.
• First a field oxide layer 101 is thermally grown over a lightly doped silicon bulk region 102.
• the substrate is either n-type or p-type, respectively.
• a portion of the field oxide region is etched away and a thin oxide region 103 which serves as the gate insulator region for the transistor is thermally grown.
• FIG. 2 illustrates the formation of the gate electrode of the transistor.
• a polysilicon path 201 running over both field oxide and thin oxide regions is formed.
• Each branch of the driver section consists of a different series connected combination of branch transistors Tl through T13.
• the gate electrodes of each branch transistor is connected to one of the input signal lines GNl through GN7.
• the signal lines of the circuit are hereafter referred to as gate nodes.
• the gate electrodes of branch transistors within a given branch are each connected to a different gate node.
• the gate electrode of the load transistor T14 is connected to gate node GNA.
• the circuit also includes an output portion 602 which consists of a single load transistor T15 connected from the VDD node to an output node 604 and a single driver transistor T16 connected from the output node to a VSS power supply node.
• the gate electrode of T15 is connected to the signal node 603 of the logic portion and the gate electrode of T16 is connected to gate node GNB.
• FIGS. 7 through 10 there are shown surface views of a chip illustrating the sequence of steps used to layout the circuit of FIG. 6 in accordance with the present invention.
• the processing steps used to form the device feature are the same as those described in connection with FIGS. 1 through 5. It is convenient from the standpoint of explaining the present method to treat the layout of the logic and output portions and the load and driver sections of each portion separately. Therefore, FIGS. 7 through 9 illustrate only the layout of the driver section of the logic portion, while FIG. 10 illustrates the layout of the entire circuit.
• the thin oxide regions corresponding to all branch transistors belonging to a given branch are situated in the column corresponding to the given branch.
• the thin oxide regions corresponding to branch transistors Tl through T4 belonging to branch Bl are all situated in the column designated by Bl.

Landscapes

• Design And Manufacture Of Integrated Circuits (AREA)
• Catalysts (AREA)
• Organic Low-Molecular-Weight Compounds And Preparation Thereof (AREA)
• Semiconductor Integrated Circuits (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Priority Applications (2)

Applications Claiming Priority (2)

Publications (1)

Family

ID=22321345

Family Applications (1)

Country Status (6)

Cited By (1)

Families Citing this family (15)

Citations (5)

Family Cites Families (4)

• 1979
  • 1979-12-28 US US06/108,289 patent/US4319396A/en not_active Expired - Lifetime
• 1980
  • 1980-10-15 EP EP81900279A patent/EP0042420B1/en not_active Expired
  • 1980-10-15 JP JP81500500A patent/JPS56501586A/ja active Pending
  • 1980-10-15 DE DE8181900279T patent/DE3072027D1/de not_active Expired
  • 1980-10-15 JP JP56500500A patent/JPH0544191B2/ja not_active Expired - Lifetime
  • 1980-10-15 WO PCT/US1980/001355 patent/WO1981001913A1/en not_active Ceased
  • 1980-10-22 CA CA000363014A patent/CA1143072A/en not_active Expired

Patent Citations (5)

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