UST940013I4 - Network design process using multiple performance functions - Google Patents

Network design process using multiple performance functions Download PDF

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Publication number
UST940013I4
UST940013I4 US50680574A UST940013I4 US T940013 I4 UST940013 I4 US T940013I4 US 50680574 A US50680574 A US 50680574A US T940013 I4 UST940013 I4 US T940013I4
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United States
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equations
user
input information
performance functions
given
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Priority to US50680574 priority Critical patent/UST940013I4/en
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/36Circuit design at the analogue level
    • G06F30/367Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

THIS IS AN AUTOMATED PROCESS FOR ANALYZING ELECTRICAL NETWORKS. THE USER OF THE PROCESS INTRODUCES INTO A COMPUTER SYSTEM, INITIALIZED WITH A PROGRAM FOR CARRYING OUT THE PROCESS, INPUT INFORMATION CONSISTING OF A SYMBOLIC REPRESENTATION OF AN ELECTRICAL NETWORK STRUCTURE PLUS A PLURALITY OF NETWORK PERFORMANCE FUNCTIONS, TOGETHER WITH THE NETWORK ELEMENTS, SOME OF WHICH ARE DEFINED AS DESIGN PARAMETERS. THE INPUT INFORMATION IS PLACED IN A DATA STORAGE MEANS AND IS ARRANGED INTO A PLURALITY OF ARRAYS, POINTERS, AND TABLES NEEDED BY THE PROCESS TO OPERATE ON THE INPUT INFORMATION INTRODUCED BY THE USER. THE PROCESS PERFORMS EITHER A STEADY STATE OR TRANSIENT ANALYSIS OF THE GIVEN ELECTRICAL NETWORK AND PROVIDES AS OUTPUT A LIST OF VALUES FOR THE DESIGN PARAMETERS WHICH OPTIMIZE THE GIVEN PLURALITY OF PERFORMANCE FUNCTIONS. THE PROCESS SOLVES A SET OF NODE EQUATIONS, PERFORMANCE EQUATIONS, AND PARAMETER EQUATIONS FOR EITHER THE STEADY STATE OR TRANSIENT STATE CASES. THEN, THE ADJOINT EQUATION IS SOLVED BY UTILIZING A WEIGHTING VECTOR Z WHICH ATTACHES A RELATIVE SIGNIFICANCE TO EACH OF THE PERFORMANCES. BOTH SETS OF EQUATIONS ARE SOLVED IN AN ITERATIVE LOOP TO GENERATE A SENSITIVITY VECTOR WHICH IS USED TO CONVERGE ON AN OPTIMIZED SOLUTION THE MULTIPLE PERFORMANCES GIVEN BY THE USER.

Description

W? K OFFICE n1 Notice 0r Dec. 11;, 1930 nbered scrlcsaml are m eluding elnlms and sheets 0; drawings (in are man-Able i0 the public for inspection and 1:
Published at the roquert of the applicant or own abstracts of Defens Minn 1111; :qtlons are Mont The heaiiing: of each absiuict incllcltcs the 111 in the an cation as originally filed. The 11in may be .ased for 30 cents a shoot.
hove not men ex:
merits of alleged invention. The Patent and to the novelty 0;. the L: 1.
made
rsrzrwcnrr DESEGN l nto a computer sysfor the proc- COllSlSYlZZg of a symbolic represennsiworl; structure plus a plurality functions, together with the net- 5 which are defined as design ormalion is paced in a data lurality of arrays, d by the process to operate on odncccl by the usor. The procy stair: or transient analysis of network provides as output a list pararnstsrs whic 1 optimize the s of a1: eioclri nppplimiiion E33. (Ii. G'Mi 15/96, 15/56 U i l.
of node equations, performance E'TUEiiOZE for either ths steady es. Then, the adjoint equation wed by utilizing a We 0 each of tho performances. Both of squaiions are solved in an iterative loop to gensrzxto a ssnsitivity vector which is ussd to converge on an GEHEWE o iiz'nizcd solution of the multiyie performances given by usrr.
NEWTON RslLFHSW ncomnm Nov. 4, 1975 C. W. HO
NETWORK DESIGN PROCESS USING MULTIPLE PERFORMANCE FUNCTIONS Original Filed Sept. 17, 1974 FIG.1
ENTER USER INPUTS I0 I SET UP TABLES FROM INPUT DATA GENERATE INDICES AND CODES FOR CIRCUIT EQUATIONS Sheet 1 of 10 DETERMINE PIVOTING SEQUENCE XII;
y 24 NO IS D.C. ANALYSIS REQUESTED "-18 SETI=Lf EQUATIONS,PARAMETER EQUATIONS.
GENERATE NODE EQUATIONS,PERFORMANCE FUNCTION 22 SOLVING EQUATIONS BY USING GAUSSIAN ELIMINATION IS THERE CONVERGENCE NEWTON RALPHSON ALGORITHM 36 YES YES IMPLICIT INTEGRATION ALGORITHM YES 48 ARE DESIGN CONSTRAINTS SATISFIED? "mmt DETERMINE THE WEIGHTING VECTOR Z END SOLVE THE ADJOINT EQUATION UPDATING DESIGN ALGORITHM FOR PARAMETERS THE NOV. 4, 1975 c. W. HO T940,013
NETWORK DESIGN PROCESS USING MULTIPLE PERFORMANCE FUNCTIONS Original Filed Sept. 17, 1974 Sheet 2 of 10 FIG. 2
EXEC1 i FIG. 3A
DISSCV COMBINE ELE1 EXEC ELE2 HELER MATBH FUNS PARS PARL FLOC FLOC EXEC2 Fl G. 38
INTGRT PMAT EVAL CAUSS SENSITY FLETCHER I l l INTGRT LU EVAL GAUSS F1 F2 F3 1 I F1 F2 F3 NOV. 4, 1975 c. w. HO T940,013
NETWORK DESIGN PROCESS USING MULTIPLE PERFORMANCE FUNCTIONS Original Filed Sept. 17, 1974 Sheet 3 of 10 K? O FIG. 4 -0 FUNS J=RUNNING COUNTER FOR NAM1 IS K NF NO YES END x os zI 108 X-NODES [INDU] J16 /114 PARL 2 PARL 1 x-(xo)/x FIG.6
FLOC
TEMP (PX) xpY 256 X+TEMP NOV. 4, 1975 c. w. HO T940,013
NETWORK DESIGN PROCESS USING MULTIPLE PERFORMANCE FUNCTIONS Original Filed Sept. 17, 1974 Sheet 4 of 10 0055 M=2? R/ZO? FIG. 5 N0 k PARI- M FLOC 2o4 i V OUT-0UT,X 206 L002 *LOC2,Y
1&0 ,210
/214 |SI FUN [m]? NO YES Y--NEQ[P[11] \216 END 21s ISM=2? NO YES /22o FLOC 0UT*0UT,X LOCP'LOCKY OUTHFQ-COUTHJ /222 LOCH LOCH,Y v
Nov. 4, 1975 C. W. HO
NETWORK DESIGN PROCESS USING MULTIPLE PERFORMANCE FUNCTIONS Original Filed Sept. 17, 1974 Sheet 5 of 10 PARS 300 F I G. 7
END
RDV J; 2] ,0x
308 FLOC 510 RDEGN [J -,51*x
LOCD-LOCD,Y
s12 J J 1 314 IS J NDR Nov. 4, 1975 On'ginal Filed Sept.
C. W. HO
NETWORK DESIGN PROCESS USING MULTIPLE PERFORMANCE FUNCTIONS FIG. 8
PMAT
Sheet 6 of 10 FIG.9
MATBH LOCBT [2;] RILOCBT [2;]
LOCBT- LOCBT CPH] LOCVD- LZ LOCDV LOCB -L LOCB LOCH Z LOCH Nov. 4, 1975 C. W. HO
NETWORK DESIGN PROCESS USING MULTIPLE PERFORMANCE FUNCTIONS Original Filed Sept.
*i INTGRT I MAT*LL0C, 0
MAT[LOCC] -CON PMAT IS 0.00015F/|XX-XX1 NO ms IStZtf? IS KzNP? .E J-0 YES FLETCHER STOP Sheet 7 of 10 Fl G. 10
EXEC 2 NOV. 4, 1975 0. W. HO
T940,013 NETWORK DESIGN PROCESS USING MULTIPLE PERFORMANCE FUNCTIONS Original Filed Sept. 17, 1974 Sheet 9 of 10 SENSITY /soo FIG. 12A FIG. 12
no. ,5o2 12A ARE STATES GIVEN BY USER? NO YES FIG. 12B z-2 0 /506 IS THE Ith. PERFORMANCE 0? NO YES 514 I 7 z z,0 Z Z, 1
' 504 Z-STATE[ -,K
IS I NQ /516 YES N0 C. W. HO
NETWORK DESIGN PROCESS USING MULTIPLE PERFORMANCE FUNCTIONS Original Filed Sept. 17, 1974 Sheet 10 of 10 LOCH EVAL OUTH FIG. 12B
IS MODE=0 INTGRT 540 GAUSS SfS to? /544 YES YES
END
US50680574 1974-09-17 1974-09-17 Network design process using multiple performance functions Pending UST940013I4 (en)

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4593362A (en) 1983-05-16 1986-06-03 International Business Machines Corporation Bay packing method and integrated circuit employing same
US4593363A (en) 1983-08-12 1986-06-03 International Business Machines Corporation Simultaneous placement and wiring for VLSI chips
US5047971A (en) * 1987-06-23 1991-09-10 Intergraph Corporation Circuit simulation
US5081590A (en) * 1988-02-29 1992-01-14 Westinghouse Electric Corp. Computer aided technique for post production tuning of microwave modules
US5111413A (en) * 1989-03-24 1992-05-05 Vantage Analysis Systems, Inc. Computer-aided engineering
US5257201A (en) * 1987-03-20 1993-10-26 International Business Machines Corporation Method to efficiently reduce the number of connections in a circuit
US5400270A (en) * 1991-08-30 1995-03-21 Mitsubishi Denki Kabushiki Kaisha Simulator for conducting timing analysis of a circuit
US5402358A (en) * 1990-05-14 1995-03-28 Vlsi Technology, Inc. Method and structure for the automated design of analog integrated circuits

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4593362A (en) 1983-05-16 1986-06-03 International Business Machines Corporation Bay packing method and integrated circuit employing same
US4593363A (en) 1983-08-12 1986-06-03 International Business Machines Corporation Simultaneous placement and wiring for VLSI chips
US5257201A (en) * 1987-03-20 1993-10-26 International Business Machines Corporation Method to efficiently reduce the number of connections in a circuit
US5047971A (en) * 1987-06-23 1991-09-10 Intergraph Corporation Circuit simulation
US5081590A (en) * 1988-02-29 1992-01-14 Westinghouse Electric Corp. Computer aided technique for post production tuning of microwave modules
US5111413A (en) * 1989-03-24 1992-05-05 Vantage Analysis Systems, Inc. Computer-aided engineering
US5402358A (en) * 1990-05-14 1995-03-28 Vlsi Technology, Inc. Method and structure for the automated design of analog integrated circuits
US5400270A (en) * 1991-08-30 1995-03-21 Mitsubishi Denki Kabushiki Kaisha Simulator for conducting timing analysis of a circuit

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