UST105403I4 - Method of manufacturing a sealing cap for an integrated circuit carrying substrate - Google Patents
Method of manufacturing a sealing cap for an integrated circuit carrying substrate Download PDFInfo
- Publication number
- UST105403I4 UST105403I4 US06/636,877 US63687784A UST105403I4 US T105403 I4 UST105403 I4 US T105403I4 US 63687784 A US63687784 A US 63687784A US T105403 I4 UST105403 I4 US T105403I4
- Authority
- US
- United States
- Prior art keywords
- integrated circuit
- manufacturing
- sealing cap
- carrying substrate
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
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- H10W99/00—
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- H10W76/12—
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- H10W72/07251—
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- H10W72/20—
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- H10W72/877—
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/16—Two dimensionally sectional layer
- Y10T428/161—Two dimensionally sectional layer with frame, casing, or perimeter structure
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
A cap for sealing a substrate having integrated circuit chips thereon is manufactured by ultrasonically machining a pattern of channels in the top surface of a plate, the pattern of channels defining a plurality of pedestals at locations corresponding to integrated circuit chip locations on the substrate. The pedestal tops are then ultrasonically machined so that each top lies a predetermined distance from the top surface of the plate.
Ceramic caps manufactured according to the present invention may be mass produced with precise dimensional tolerances.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/636,877 UST105403I4 (en) | 1982-09-07 | 1984-08-02 | Method of manufacturing a sealing cap for an integrated circuit carrying substrate |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US41476482A | 1982-09-07 | 1982-09-07 | |
| US06/636,877 UST105403I4 (en) | 1982-09-07 | 1984-08-02 | Method of manufacturing a sealing cap for an integrated circuit carrying substrate |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US41476482A Continuation | 1982-09-07 | 1982-09-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| UST105403I4 true UST105403I4 (en) | 1985-05-07 |
Family
ID=27022705
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US06/636,877 Pending UST105403I4 (en) | 1982-09-07 | 1984-08-02 | Method of manufacturing a sealing cap for an integrated circuit carrying substrate |
Country Status (1)
| Country | Link |
|---|---|
| US (1) | UST105403I4 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5703397A (en) * | 1991-11-28 | 1997-12-30 | Tokyo Shibaura Electric Co | Semiconductor package having an aluminum nitride substrate |
| US6252776B1 (en) * | 1998-07-23 | 2001-06-26 | Nec Corporation | Heat radiating member for heat generating device |
-
1984
- 1984-08-02 US US06/636,877 patent/UST105403I4/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5703397A (en) * | 1991-11-28 | 1997-12-30 | Tokyo Shibaura Electric Co | Semiconductor package having an aluminum nitride substrate |
| US6252776B1 (en) * | 1998-07-23 | 2001-06-26 | Nec Corporation | Heat radiating member for heat generating device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| STPP | Information on status: patent application and granting procedure in general |
Free format text: DEFENSIVE PUBLICATION OR SIR FILE |